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// @(#)divlog.v 1.1 4/7/92
//
/* ############################################################
divlog.v 1.0 6th September 1989
DivLog Generation
############################################################ */
/* Divlog requires generation of DivMultiple From RemBits.
The RemBits are signed.
Pos Neg
Div Multiple 0 1 2 2 3 3 3 3 3 3 3 3 2 2 1 0 Divisor 1.1
0 1 2 3 3 3 3 3 3 3 3 3 3 2 1 0 Divisor 1.0
RemBits 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RemBits[3]
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RemBits[2]
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RemBits[1]
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RemBits[0]
Therfore
DivMultiple [3] 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
Divisor=1 [2] 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0
[1] 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
DivMultiple [3] 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0
Divisor=0 [2] 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
[1] 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Which can be expressed
DivMultiple [1] = ~RemBit[3].~RemBit[2].~RemBit[1].RemBit[0] +
RemBit[3].RemBit[2].RemBit[1].~RemBit[0];
DivMultiple [2] = ~RemBit[3].~RemBit[2].RemBit[1].~RemBit[0] +
~RemBit[3].~RemBit[2].RemBit[1].DivisorBit +
RemBit[3]. RemBit[2].~RemBit[1].RemBit[0] +
RemBit[3]. RemBit[2].~RemBit[1].DivisorBit;
DivMultiple [3] = ~RemBit[3]. RemBit[2] +
~RemBit[2]. RemBit[1]. RemBit[0].~DivisorBit +
RemBit[3].~RemBit[2] +
RemBit[2].~RemBit[1].~RemBit[0].~DivisorBit;
The Quotient selection is made based on the previous trial multiple and the sign of the result of the trial
The div multiple is recreated from the notDivMultiple[3:1] lines
Div Multiple -3 -2 -1 -0 0 1 2 3
Sign of trial result + - + - + - + - + - + - + - + -
Quotient bits generated 1 0 2 1 3 2 x 3 0 x 1 0 2 1 3 2
Which can be expressed
QuotientBit[1] = OldSign.DivMultiple[1].~DivMultiple[0].~NewSign +
OldSign.~DivMultiple[1] +
~OldSign.DivMultiple[1].DivMultiple[0] +
~OldSign.DivMultiple[1].~DivMultiple[0].~NewSign;
QuotientBit[0] = DivMultiple[0] XOR NewSign;
By multiplexing on the new sign
QuotientBit0[1] = OldSign.DivMultiple[1].~DivMultiple[0] +
OldSign.~DivMultiple[1] +
~OldSign.DivMultiple[1].DivMultiple[0] +
~OldSign.DivMultiple[1].~DivMultiple[0].~NewSign;
QuotientBit0[0] = DivMultiple[0];
QuotientBit1[1] = OldSign.~DivMultiple +
~OldSign.DivMultiple[1].DivMultiple[0];
QuotientBit[0] = ~DivMultiple[0];
*/
module DivLog
(Phi,
AregFPMSBM1, // Divisor Bit
BregFPMSBM1, // On first step divisor is in B
StepRemBits, // RemBits used during step
InitialRemBits, // RemBits used on first step
SelectInitial, // Select First step
FracSign, // Sign of result after operation
DivMultiple, // Latched version of Divide Step Multiple
QuotientBits); // Quotient bits, valid on cycle after
// operation
// notFracSign); // inv FracSign -- generate inside fdp (dhn 03/27/91)
input Phi
; // System Clock
input AregFPMSBM1
, BregFPMSBM1
, FracSign
;
input [3:0] StepRemBits
, InitialRemBits
;
input SelectInitial
;
output [3:1] DivMultiple
;
output [1:0] QuotientBits
;
// output notFracSign; // -- generate inside fdp (dhn 03/27/91)
// ME_INVA ifs (FracSign, notFracSign); // --generate inside fdp (dhn 03/27/91)
wire [3:1] notDivMultiple
, DivMultipleU
;
wire [3:0] notRemBits
;
wire [3:0] RemBits
;
ME_NMUX2B msld (SelectInitial, AregFPMSBM1, BregFPMSBM1, notDivisorBit
);
ME_NMUX2B msl0 (SelectInitial, StepRemBits[0], InitialRemBits[0], notRemBits[0]);
ME_NMUX2B msl1 (SelectInitial, StepRemBits[1], InitialRemBits[1], notRemBits[1]);
ME_NMUX2B msl2 (SelectInitial, StepRemBits[2], InitialRemBits[2], notRemBits[2]);
ME_NMUX2B msl3 (SelectInitial, StepRemBits[3], InitialRemBits[3], notRemBits[3]);
ME_INV_B ir3 (notRemBits[3], RemBits[3]);
ME_INV_B ir2 (notRemBits[2], RemBits[2]);
ME_INV_B ir1 (notRemBits[1], RemBits[1]);
ME_INV_B ir0 (notRemBits[0], RemBits[0]);
ME_INV_B id0 (notDivisorBit, DivisorBit
);
// DivMultiple [1] = ~RemBit[3].~RemBit[2].~RemBit[1].RemBit[0] +
// RemBit[3].RemBit[2].RemBit[1].~RemBit[0];
ME_NAND4 ds10 (notRemBits[3], notRemBits[2], notRemBits[1], RemBits[0], dm1t0
);
ME_NAND4 ds11 (RemBits[3], RemBits[2], RemBits[1], notRemBits[0], dm1t1
);
ME_NAND2 ds1m (dm1t1, dm1t0, DivMultipleU[1]);
// DivMultiple [2] = ~RemBit[3].~RemBit[2].RemBit[1].~RemBit[0] +
// ~RemBit[3].~RemBit[2].RemBit[1].DivisorBit +
// RemBit[3]. RemBit[2].~RemBit[1].RemBit[0] +
// RemBit[3]. RemBit[2].~RemBit[1].DivisorBit;
ME_NAND4 ds20 (notRemBits[3], notRemBits[2], RemBits[1], notRemBits[0], dm2t0
);
ME_NAND4 ds21 (notRemBits[3], notRemBits[2], RemBits[1], DivisorBit, dm2t1
);
ME_NAND4 ds22 (RemBits[3], RemBits[2], notRemBits[1], RemBits[0], dm2t2
);
ME_NAND4 ds23 (RemBits[3], RemBits[2], notRemBits[1], DivisorBit, dm2t3
);
ME_NAND4 ds2m (dm2t1, dm2t0, dm2t2, dm2t3, DivMultipleU[2]);
// DivMultiple [3] = ~RemBit[3]. RemBit[2] +
// ~RemBit[2]. RemBit[1]. RemBit[0].~DivisorBit +
// RemBit[3].~RemBit[2] +
// RemBit[2].~RemBit[1].~RemBit[0].~DivisorBit;
ME_NAND2 ds30 (notRemBits[3], RemBits[2], dm3t0
);
ME_NAND4 ds31 (notRemBits[2], RemBits[1], RemBits[0], notDivisorBit, dm3t1
);
ME_NAND2 ds32 (RemBits[3], notRemBits[2], dm3t2
);
ME_NAND4 ds33 (RemBits[2], notRemBits[1], notRemBits[0], notDivisorBit, dm3t3
);
ME_NAND4 ds3m (dm3t1, dm3t0, dm3t2, dm3t3, DivMultipleU[3]);
/* ************************************************
Latch next Div Multiple
************************************************ */
ME_FD1_B dv1 (Phi, DivMultipleU[1], DivMultiple[1], notDivMultiple[1]);
ME_FD1_B dv2 (Phi, DivMultipleU[2], DivMultiple[2], notDivMultiple[2]);
ME_FD1_B dv3 (Phi, DivMultipleU[3], DivMultiple[3], notDivMultiple[3]);
ME_FD1_B dv0 (Phi, notRemBits[3], notOldSign
, OldSign
);
/* ************************************************
Quotient bit generation
End of Result QuoBit Generation calculation
************************************************ */
/* Not time critical so use buffered DivMultiple */
/* Also use the encoded version of DivMultiple ie DivMultipleC */
wire [1:0] DivMultipleC
, notDivMultipleC
;
ME_NAND2 dedv0 (notDivMultiple[1], notDivMultiple[3], DivMultipleC[0]);
ME_NAND2 dedv1 (notDivMultiple[2], notDivMultiple[3], DivMultipleC[1]);
ME_INV_A dmb0 (DivMultipleC[0], notDivMultipleC[0]);
ME_INV_A dmb1 (DivMultipleC[1], notDivMultipleC[1]);
// QuotientBit0[1] = OldSign.DivMultiple[1].~DivMultiple[0] +
// OldSign.~DivMultiple[1] +
// ~OldSign.DivMultiple[1];
// QuotientBit1[1] = OldSign.~DivMultiple[1] +
// ~OldSign.DivMultiple[1].DivMultiple[0];
// QuotientBit0[0] = DivMultiple[0];
// QuotientBit1[0] = ~DivMultiple[0];
ME_NAND3 qb1t0 (OldSign, DivMultipleC[1], notDivMultipleC[0], t0
);
ME_NAND2 qb1t1 (OldSign, notDivMultipleC[1], t1
);
ME_NAND2 qb1t2 (notOldSign, DivMultipleC[1], t2
);
ME_NAND3 qb1t3 (t0, t1, t2, t3
);
ME_NAND3 qb1t4 (notOldSign, DivMultipleC[1], DivMultipleC[0], t4
);
ME_NAND2 qb1t5 (t4, t1, t5
);
ME_MUX2B qb1m (FracSign, t3, t5, QuotientBits[1]);
ME_NMUX2B qb0m (FracSign, notDivMultipleC[0], DivMultipleC[0], QuotientBits[0]);
endmodule
This page: |
Created: | Thu Aug 19 11:59:15 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_ctl/rtl/divlog.v
|