/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
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/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)fifo4_64.v
***
*** Description:
*** Implements a 4 deep, 64 bit wide fifo for holding afx write data.
***
****************************************************************************
****************************************************************************/
module fifo4_64
( reset, //fifo reset
clock, //fifo clock
data_in, //data in (variable width)
read, //read fifo
write, //write fifo
full_count, //full count
data_out); //fifo data out
// Fifo is 4 entries deep, variable width default is 64 bit
parameter WIDTH = 63;
input reset
;
input clock
;
input [WIDTH:0] data_in
;
input read
;
input write
;
output [2:0] full_count
;
output [WIDTH:0] data_out
;
wire [WIDTH:0] reg0
,reg1
,reg2
,reg3
;
reg [1:0] wr_ptr
, rd_ptr
;
reg [2:0] full_count;
wire [WIDTH:0] data_out;
MUX4to1_64 MUX0(data_out,rd_ptr,reg0,reg1,reg2,reg3);
// load fifos and increment of read and write pointers
wire write_reg0
= (write & wr_ptr == 2'b00);
wire write_reg1
= (write & wr_ptr == 2'b01);
wire write_reg2
= (write & wr_ptr == 2'b10);
wire write_reg3
= (write & wr_ptr == 2'b11);
REG64 REG64_0(.data_out (reg0),
.clock (clock),
.load_en (write_reg0),
.data_in (data_in)
);
REG64 REG64_1(.data_out (reg1),
.clock (clock),
.load_en (write_reg1),
.data_in (data_in)
);
REG64 REG64_2(.data_out (reg2),
.clock (clock),
.load_en (write_reg2),
.data_in (data_in)
);
REG64 REG64_3(.data_out (reg3),
.clock (clock),
.load_en (write_reg3),
.data_in (data_in)
);
always @(posedge clock)
begin
if (reset)
begin
rd_ptr <= 2'b00;
end
else if (read)
begin
rd_ptr <= #1 (rd_ptr + 2'b01);
end
end
always @(posedge clock)
begin
if (reset)
begin
wr_ptr <= 2'b00;
end
else if (write)
begin
wr_ptr <= #1 (wr_ptr + 2'b01);
end
end
// generate full_count; 0 at reset
// increment on write and no read
// decrement on read and no write
// holds on either no read, no write OR read and write
always @(posedge clock)
begin
if (reset )
full_count <= 3'b000;
else if (write & ~read)
full_count <= #1 (full_count + 3'b001);
else if (~write & read)
full_count <= #1 (full_count - 3'b001);
end
endmodule
This page: |
Created: | Thu Aug 19 11:59:45 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afx_slave/afx_slave_fifo/rtl/fifo4_64.v
|