/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
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/*                                                                            */ 
/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)sync.v
***
****************************************************************************
****************************************************************************/
... (truncated)
module sync(
		out, 
		in_clk,
		out_clk,
		in
		);

// synchronizes from between clock domains.
// uses posedge followed by negedge.
// uses back to back metastable hardened latches.
// in_clk and out_clk are really the same "target" frequency
// clock, just opposite edges controlled by the user.

input in;
input in_clk;
input out_clk;

output out;
reg out, sync0_out;

always @(posedge in_clk)
  sync0_out <= #1 in;

always @(posedge out_clk)
  out <= #1 sync0_out;


endmodule
  
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)REG44.v
***
*** Description:
***   44 bit wide register 
***
****************************************************************************
****************************************************************************/


module REG44(   data_out,
		clock,			//clock
		load_en,		//register load enable
		data_in);

		parameter WIDTH = 44;

input 	clock;
input   load_en;
input	[(WIDTH-1):0] data_in;
output  [(WIDTH-1):0] data_out;
reg  [(WIDTH-1):0] data_out;


wire [(WIDTH-1):0] reg_data_in = load_en ? data_in : data_out;

always @(posedge clock)
begin
  data_out <= #1 reg_data_in;
end


endmodule

/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)REG32.v
***
***  Description:
***    32 bit wide register 
*** 
****************************************************************************
****************************************************************************/


module REG32(   data_out,
		clock,			//clock
		load_en,		//register load enable
		data_in);		//data in 

		parameter WIDTH = 32;

input 	clock;
input   load_en;
input	[(WIDTH-1):0] data_in;
output  [(WIDTH-1):0] data_out;
reg  [(WIDTH-1):0] data_out;


wire [(WIDTH-1):0] reg_data_in = load_en ? data_in : data_out;

always @(posedge clock)
begin
  data_out <= #1 reg_data_in;
end


endmodule

/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)REG64.v
***
***  Description:
***    64 bit wide register 
*** 
****************************************************************************
****************************************************************************/


module REG64(   data_out,
		clock,			//clock
		load_en,		//register load enable
		data_in);		//data in 

		parameter WIDTH = 64;

input 	clock;
input   load_en;
input	[(WIDTH-1):0] data_in;
output  [(WIDTH-1):0] data_out;
reg  [(WIDTH-1):0] data_out;


wire [(WIDTH-1):0] reg_data_in = load_en ? data_in : data_out;

always @(posedge clock)
begin
  data_out <= #1 reg_data_in;
end


endmodule

/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)MUX4to1_64.v
***
***  Description:
***    4 to 1 mux, 64 bits wide to save space
*** 
****************************************************************************
****************************************************************************/


module MUX4to1_64( data_out,
		select,			//select
		data0,			//data in 0 
		data1,			//data in 1 
		data2,			//data in 2 
		data3);			//data in 3 

		parameter WIDTH = 64;

input 	[1:0]  select;
input	[(WIDTH-1):0] data0;
input	[(WIDTH-1):0] data1;
input	[(WIDTH-1):0] data2;
input	[(WIDTH-1):0] data3;

output  [(WIDTH-1):0] data_out;

wire [(WIDTH-1):0] data_out; 

assign data_out = mux4(select,data0,data1,data2,data3);

function [(WIDTH-1):0] mux4;
input [1:0]	select;
input [(WIDTH-1):0]	data0;
input [(WIDTH-1):0]	data1;
input [(WIDTH-1):0]	data2;
input [(WIDTH-1):0]	data3;

begin
	case(select)
	2'b00: mux4 = data0;
	2'b01: mux4 = data1;
	2'b10: mux4 = data2;
	2'b11: mux4 = data3;

	endcase
end
endfunction

endmodule
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)REG29.v
***
***  Description:
***    29 bit wide register 
*** 
****************************************************************************
****************************************************************************/


module REG29(   data_out,
		clock,			//clock
		load_en,		//register load enable
		data_in);

		parameter WIDTH = 29;

input 	clock;
input   load_en;
input	[(WIDTH-1):0] data_in;
output  [(WIDTH-1):0] data_out;
reg  [(WIDTH-1):0] data_out;


wire [(WIDTH-1):0] reg_data_in = load_en ? data_in : data_out;

always @(posedge clock)
begin
  data_out <= #1 reg_data_in;
end


endmodule

/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)MUX4to1_10.v
***
***  Description:
***    4 to 1 mux, 10 bits wide to save space
*** 
****************************************************************************
****************************************************************************/


module MUX4to1_10( data_out,
		select,			//select
		data0,			//data in 0 
		data1,			//data in 1 
		data2,			//data in 2 
		data3);			//data in 3 

		parameter WIDTH = 10;

input 	[1:0]  select;
input	[(WIDTH-1):0] data0;
input	[(WIDTH-1):0] data1;
input	[(WIDTH-1):0] data2;
input	[(WIDTH-1):0] data3;

output  [(WIDTH-1):0] data_out;

wire [(WIDTH-1):0] data_out; 

assign data_out = mux4(select,data0,data1,data2,data3);

function [(WIDTH-1):0] mux4;
input [1:0]	select;
input [(WIDTH-1):0]	data0;
input [(WIDTH-1):0]	data1;
input [(WIDTH-1):0]	data2;
input [(WIDTH-1):0]	data3;

begin
	case(select)
	2'b00: mux4 = data0;
	2'b01: mux4 = data1;
	2'b10: mux4 = data2;
	2'b11: mux4 = data3;

	endcase
end
endfunction

endmodule
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)MUX4to1_32.v
***
***  Description:
***    4 to 1 mux, 32 bits wide to save space
*** 
****************************************************************************
****************************************************************************/

module MUX4to1_32( data_out,
		select,			//select
		data0,			//data in 0 
		data1,			//data in 1 
		data2,			//data in 2 
		data3);			//data in 3 

		parameter WIDTH = 32;

input 	[1:0]  select;
input	[(WIDTH-1):0] data0;
input	[(WIDTH-1):0] data1;
input	[(WIDTH-1):0] data2;
input	[(WIDTH-1):0] data3;

output  [(WIDTH-1):0] data_out;

wire [(WIDTH-1):0] data_out; 

assign data_out = mux4(select,data0,data1,data2,data3);

function [(WIDTH-1):0] mux4;
input [1:0]	select;
input [(WIDTH-1):0]	data0;
input [(WIDTH-1):0]	data1;
input [(WIDTH-1):0]	data2;
input [(WIDTH-1):0]	data3;

begin
	case(select)
	2'b00: mux4 = data0;
	2'b01: mux4 = data1;
	2'b10: mux4 = data2;
	2'b11: mux4 = data3;

	endcase
end
endfunction

endmodule
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)pci_macros.v
***
***  Description:
***    36 bit wide register 
*** 
****************************************************************************
****************************************************************************/


module REG36(   data_out,
		clock,			//clock
		load_en,		//register load enable
		data_in);		// data in

		parameter WIDTH = 36;

input 	clock;
input   load_en;
input	[(WIDTH-1):0] data_in;
output  [(WIDTH-1):0] data_out;
reg  [(WIDTH-1):0] data_out;


wire [(WIDTH-1):0] reg_data_in = load_en ? data_in : data_out;

always @(posedge clock)
begin
  data_out <= #1 reg_data_in;
end


endmodule

/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)pci_macros.v
***
***  Description:
***    4 to 1 mux, 36 bits wide to save space
*** 
****************************************************************************
****************************************************************************/
 

module MUX4to1_36( data_out,
		select,			//select
		data0,			//data in 0 
		data1,			//data in 1 
		data2,			//data in 2 
		data3);			//data in 3 

		parameter WIDTH = 36;

input 	[1:0]  select;
input	[(WIDTH-1):0] data0;
input	[(WIDTH-1):0] data1;
input	[(WIDTH-1):0] data2;
input	[(WIDTH-1):0] data3;

output  [(WIDTH-1):0] data_out;

wire [(WIDTH-1):0] data_out; 

assign data_out = mux4(select,data0,data1,data2,data3);

function [(WIDTH-1):0] mux4;
input [1:0]	select;
input [(WIDTH-1):0]	data0;
input [(WIDTH-1):0]	data1;
input [(WIDTH-1):0]	data2;
input [(WIDTH-1):0]	data3;

begin
	case(select)
	2'b00: mux4 = data0;
	2'b01: mux4 = data1;
	2'b10: mux4 = data2;
	2'b11: mux4 = data3;

	endcase
end
endfunction

endmodule
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)pci_macros.v
***
***  Description:
***    37 bit wide register 
*** 
****************************************************************************
****************************************************************************/
 

module REG37(   data_out,
		clock,			//clock
		load_en,		//register load enable
		data_in);		// data in

		parameter WIDTH = 37;

input 	clock;
input   load_en;
input	[(WIDTH-1):0] data_in;
output  [(WIDTH-1):0] data_out;
reg  [(WIDTH-1):0] data_out;


wire [(WIDTH-1):0] reg_data_in = load_en ? data_in : data_out;

always @(posedge clock)
begin
  data_out <= #1 reg_data_in;
end


endmodule

/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)pci_macros.v
***
***  Description:
***    4 to 1 mux, 37 bits wide to save space
*** 
****************************************************************************
****************************************************************************/

module MUX4to1_37( data_out,
		select,			//select
		data0,			//data in 0 
		data1,			//data in 1 
		data2,			//data in 2 
		data3);			//data in 3 

		parameter WIDTH = 37;

input 	[1:0]  select;
input	[(WIDTH-1):0] data0;
input	[(WIDTH-1):0] data1;
input	[(WIDTH-1):0] data2;
input	[(WIDTH-1):0] data3;

output  [(WIDTH-1):0] data_out;

wire [(WIDTH-1):0] data_out; 

assign data_out = mux4(select,data0,data1,data2,data3);

function [(WIDTH-1):0] mux4;
input [1:0]	select;
input [(WIDTH-1):0]	data0;
input [(WIDTH-1):0]	data1;
input [(WIDTH-1):0]	data2;
input [(WIDTH-1):0]	data3;

begin
	case(select)
	2'b00: mux4 = data0;
	2'b01: mux4 = data1;
	2'b10: mux4 = data2;
	2'b11: mux4 = data3;

	endcase
end
endfunction

endmodule