/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)fpufpc_2.0.v 1.17 4/15/93
//
// **************************************************************
// High Level model of FPU/FPC
//
// This module is the top level module for the FPU/FPC. It defines
// the interface signals and instantiates the following seven modules:
//
// fp_fpc, fp_rf, fp_ctl, fp_exp, fp_frac, fp_rom
//
// **************************************************************
module fpufpc
(ss_clock, ss_reset, ld_fpu_w, inst_for_int,
iu_epc, hld_dirreg, ext_valid_decode, fold_annul_e,
ext_flush, ext_hold, ext_hold1, ext_fxack, ext_fhold,
ext_fexc, ext_fcc, ext_fccv, fhold_d1, fhold_fqfull_d1,
fload_wait_w, fp_dout_e,
fp_fpc_scan_in, fprf_scan_out, ss_scan_mode );
input [63:0] ld_fpu_w
; // Data-cache output bus
input [31:0] inst_for_int
; // Input to D-stage instruction register
input [31:2] iu_epc
; // tap from IU E-stage pc (30-bits)
input ss_clock
; // Floating pt. unit clock inputs
input ss_reset
, // Floating pt. unit reset input
hld_dirreg
, // inverted load signal for decode register
ext_valid_decode
, // Valid instr in decode
fold_annul_e
, // inst in E is annuled
ext_flush
; // FPU flush (IU trap)
input [2:0] ext_hold
; // IU pipeline held (frozen) from mhold, etc.
input ext_hold1
, // duplicate of ext_hold
ext_fxack
, // Floating pt. exception acknowledge
fp_fpc_scan_in
, // scan data input
ss_scan_mode
; // scan enable
output ext_fhold
, // Floating point hold (interlocks the IU)
ext_fexc
; // Floating point exception signal
output [1:0] ext_fcc
; // Floating point condition codes
output ext_fccv
, // Floating point condition codes valid
fhold_d1
, // delayed ext_fhold used by perf counter
fhold_fqfull_d1
, // delayed fq_full used by perf counter
fload_wait_w
; // FPop is currently executing, and may trap
output [63:0] fp_dout_e
; // Data Out Bus
output fprf_scan_out
; // scan data output
// FPP Operand & Result busses, reg file input/output busses,
wire [54:3] FracResult
;
wire [10:0] ExpResult
;
wire SignResult
, SNnotDB
;
wire [63:0] fprf_dout1
, fprf_dout2
, fprf_dout3
, fprf_din
;
// input data (from Data-cache) for the FSR register
wire [18:0] fsr_data_in
= {ld_fpu_w[31:30], ld_fpu_w[27:23], ld_fpu_w[11:0]} ;
// FPP status: cond. codes and exception bits
wire [1:0] ConditionCodes
;
wire [5:0] Excep
;
wire fpm_inx
, fpm_unfin
;
// Reg file read and write addresses, and control
wire [3:0] fprf_ra1
;
wire [3:0] fprf_ra2
;
wire [3:0] fprf_ra3
;
wire [3:0] fprf_wa
;
wire [5:0] fprf_byp1
, fprf_byp2
, fprf_byp3
;
wire [1:0] fprf_algn1
, fprf_algn2
;
wire [1:0] fprf_hold_din
;
wire [1:0] fprf_we
;
// FP instruction and rounding mode bits for Meiko core
wire [9:0] FpInst
;
wire [1:0] RoundingMode
;
// exception status from Meiko core
wire [7:0] fpstat
= {ConditionCodes, Excep};
// Datapath and FPP control signals
wire fpm_start
, fpp_fop
, fpp_ld
, fpp_reset
;
wire [1:0] res_select
, fpm_inst
;
wire rfin_select
;
wire FpBusyPhi2
; // FPP status signal (busy)
// scan signals
wire fp_fpc_scan_in, fp_fpc_scan_out
;
wire fprf_scan_out, fp_fpm_scan_out
, fp_rom_scan_out
;
wire fp_exp_scan_out
, fp_ctl_scan_out
, fp_frac_scan_out
;
// Floating Point Control unit module instance
fp_fpc fpfpc (.ss_clock(ss_clock), .ss_reset(ss_reset),
.ext_valid_decode(ext_valid_decode),
.fold_annul_e(fold_annul_e),
.ext_flush(ext_flush), .ext_hold(ext_hold[2:0]),
.ext_fxack(ext_fxack),
.hld_dirreg(hld_dirreg), .FpBusyPhi2(FpBusyPhi2),
.fpm_inx(fpm_inx), .fpm_unfin(fpm_unfin),
.fpstat(fpstat), .fsr_data_in(fsr_data_in),
.inst_for_int(inst_for_int), .iu_epc(iu_epc),
.fprf_dout3(fprf_dout3), .fp_dout_e(fp_dout_e),
.FpInst(FpInst), .fpm_inst(fpm_inst),
.RoundingMode(RoundingMode),.ext_fcc(ext_fcc),
.ext_fhold(ext_fhold), .fpm_start(fpm_start),
.fpp_fop(fpp_fop),
.fpp_ld(fpp_ld), .fpp_reset(fpp_reset), .ext_fexc(ext_fexc),
.fhold_d1(fhold_d1), .fhold_fqfull_d1(fhold_fqfull_d1),
.res_select(res_select), .rfin_select(rfin_select),
.fprf_wa(fprf_wa), .fprf_ra1(fprf_ra1), .fprf_ra2(fprf_ra2),
.fprf_ra3(fprf_ra3), .fprf_hold_din(fprf_hold_din),
.fprf_we(fprf_we),
.fprf_byp1(fprf_byp1), .fprf_byp2(fprf_byp2),
.fprf_byp3(fprf_byp3), .fprf_algn1(fprf_algn1),
.fprf_algn2(fprf_algn2), .ext_fccv(ext_fccv),
.fload_wait_w(fload_wait_w),
.ss_scan_mode(ss_scan_mode),
.fp_fpc_scan_in(fp_fpc_scan_in),
.fp_fpc_scan_out(fp_fpc_scan_out) );
// FPU Register File module instance
fp_rf fprf (.ss_clock(ss_clock), .ss_scan_mode(ss_scan_mode),
.fp_scan_in(fp_fpm_scan_out),
.hold_din(fprf_hold_din), .fp_hold_ra3(ext_hold1),
.fp_we(fprf_we),
.fp_algn1(fprf_algn1), .fp_algn2(fprf_algn2),
.fp_byp1(fprf_byp1), .fp_byp2(fprf_byp2), .fp_byp3(fprf_byp3),
.fp_wa(fprf_wa), .fp_ra1(fprf_ra1), .fp_ra2(fprf_ra2),
.fp_ra3(fprf_ra3),
.fp_din(fprf_din), .fp_dout1(fprf_dout1), .fp_dout2(fprf_dout2),
.fp_dout3(fprf_dout3), .fp_scan_out(fprf_scan_out) );
// **********************************************************
// all modules below this line are part of the Meiko FPU core
// **********************************************************
//-----------------------------------------------------------------------------
wire FpOp
, FpLd
, Reset
, FpBusy
;
assign FpOp = fpp_fop ;
assign FpLd = fpp_ld ;
assign Reset = fpp_reset ;
assign FpBusyPhi2 = FpBusy ;
// This module header is used when testing the FPU core by itself.
// Meiko FPU top-level interconnect module
//
// This interconnect module was produced by Synopsys grouping and then edited
// by hand () to remove hierarchy from signal names and make
// things more readable.
/* ***********************
module FPU ( ss_clock, FpInst, FpOp, FpLd, Reset,
fprf_dout1, fprf_dout2, RoundingMode,
FpBusy, FracResult, ExpResult, SignResult, SNnotDB,
Excep, ConditionCodes,
ss_scan_mode, fp_ctl_scan_in, fp_ctl_scan_out );
input ss_clock, FpOp, FpLd, Reset, ss_scan_mode, fp_ctl_scan_in;
input [9:0] FpInst;
output [1:0] ConditionCodes;
input [63:0] fprf_dout1;
input [63:0] fprf_dout2;
output [5:0] Excep;
input [1:0] RoundingMode;
output [54:3] FracResult;
output [10:0] ExpResult;
output FpBusy, SignResult, SNnotDB, fp_ctl_scan_out;
************************** */
wire FracAregLoadEn
, FracBregLoadEn
, FracCregLoadEn
, FracCregLC
,
FracTregLoadEn
, SROneMore
, SRToSticky
, notStickyInForSR
,
InitialMulStep
, InitialCarryBit
, SumCarryLoadEn
, SumOut0
,
CarryOut0
, CarryOut3
, RomOutputs_18
, RomOutputs_55
, notFracYFromD1A
,
notFracYFromD2A
, notFracYFromD3A
, notSticky1
, FracBregSign
,
BregFPMSBM1
, notAM31_3
, notAM2_0
, StickyForSR1
, AregMaster_32
,
notAregMasterFPMSBP1
, CALSB
, CBLSB
, CCLSB
, notFracZero
, FracZero
,
FracAgtB
, SubResultNorm
, Conditionals_10
, notPossibleOv
, notNO_1
,
RomOutputs_20
, ExpAregLoadEn
, ExpAregLC0
, ExpAregLC1
, ExpBregLoadEn
,
ExpBregLC0
, ExpBregLC1
, RomOutputs_27
, CarryIn
, Constantb
, Constantc
,
Constantd
, Constante
, Constantf
, Constantg
, Constanth
, Conditionals_12
,
Conditionals_3
, notAInfNAN
, notAZeroDenorm
, notBInfNAN
, notBZeroDenorm
,
notExpUnderflow
, notExpOverflow
, notExpException
, OprSNnotDB
;
wire [2:0] FracAregLC
;
wire [2:0] FracBregLC
;
wire [1:0] FracYbusLSBs
;
wire [1:0] InFromCregOr0
;
wire [1:0] InForCreg
;
wire [1:0] InForCregDB
;
wire [32:29] RomOutputs_32_29
;
wire [46:44] RomOutputs_46_44
;
wire [4:0] FracRound
;
wire [3:0] SRControl
;
wire [3:0] SLControl
;
wire [2:0] LIB
;
wire [8:0] TopBitsIn
;
wire [3:0] Shift
;
wire [3:0] Pos
;
wire [3:0] Zero
;
wire [4:0] MulLenSel
;
wire [3:0] notSticky4
;
wire [1:0] Sticky2
;
wire [1:0] StickyExtra
;
wire [1:0] CregSNBits
;
wire [1:0] CregInSL2SQRT
;
wire [8:0] notMultip
;
wire [57:40] AregMaster_57_40
;
wire [7:0] AregMaster_7_0
;
wire [1:0] TregLSBs
;
wire [2:0] SumInLSBs
;
wire [2:0] CarryInLSBs
;
wire [1:0] SALSBs
;
wire [1:0] SBLSBs
;
wire [1:0] SCLSBs
;
wire [3:0] StepRemBits
;
wire [3:1] notsh
;
wire [7:0] ExpIn
;
wire [12:0] notExpShiftResult
;
wire [7:0] SelectedMIptr
;
wire [63:0] U_RomOutputs
;
// Meiko FPU core control logic
fp_ctl fpctl ( .ss_clock (ss_clock), .AregMaster_32 (AregMaster_32),
.BregFPMSBM1 (BregFPMSBM1), .CALSB (CALSB), .CBLSB (CBLSB),
.CCLSB (CCLSB), .Conditionals_3 (Conditionals_3),
.Conditionals_10 (Conditionals_10), .Conditionals_12 (Conditionals_12),
.FpLd (FpLd), .FpOp (FpOp), .FracAgtB (FracAgtB),
.FracBregSign (FracBregSign), .FracZero (FracZero),
.notAInfNAN (notAInfNAN), .notAM31_3 (notAM31_3),
.notAM2_0 (notAM2_0), .notAregMasterFPMSBP1 (notAregMasterFPMSBP1),
.notAZeroDenorm (notAZeroDenorm), .notBInfNAN (notBInfNAN),
.notBZeroDenorm (notBZeroDenorm), .notExpUnderflow (notExpUnderflow),
.notExpOverflow (notExpOverflow), .notExpException (notExpException),
.notPossibleOv (notPossibleOv), .notFracZero (notFracZero),
.notSticky1 (notSticky1), .ResetIn (Reset), .RS2_63 (fprf_dout2[63] ),
.RS1_63 (fprf_dout1[63] ), .StickyForSR1 (StickyForSR1),
.SubResultNorm (SubResultNorm), .AregMaster_57_40 (AregMaster_57_40),
.AregMaster_7_0 (AregMaster_7_0), .CarryInLSBs (CarryInLSBs),
.CregInSL2SQRT (CregInSL2SQRT), .CregSNBits (CregSNBits),
.ExpIn (ExpIn), .FpInst (FpInst),
.notExpShiftResult (notExpShiftResult), .notMultip (notMultip),
.notSticky4 (notSticky4), .RoundingMode (RoundingMode),
.SALSBs (SALSBs), .SBLSBs (SBLSBs), .SCLSBs (SCLSBs),
.StepRemBits (StepRemBits), .Sticky2 (Sticky2),
.StickyExtra (StickyExtra), .SumInLSBs (SumInLSBs),
.TregLSBs (TregLSBs), .U_RomOutputs (U_RomOutputs ),
.CarryIn (CarryIn), .CarryOut0 (CarryOut0), .CarryOut3 (CarryOut3),
.Constantb (Constantb), .Constantc (Constantc), .Constantd (Constantd),
.Constante (Constante), .Constantf (Constantf), .Constantg (Constantg),
.Constanth (Constanth), .ExpAregLC0 (ExpAregLC0),
.ExpAregLC1 (ExpAregLC1), .ExpAregLoadEn (ExpAregLoadEn),
.ExpBregLC0 (ExpBregLC0), .ExpBregLC1 (ExpBregLC1),
.ExpBregLoadEn (ExpBregLoadEn), .FracAregLoadEn (FracAregLoadEn),
.FracBregLoadEn (FracBregLoadEn), .FracCregLC (FracCregLC),
.FracCregLoadEn (FracCregLoadEn), .FracTregLoadEn (FracTregLoadEn),
.FpBusy (FpBusy), .InitialCarryBit (InitialCarryBit),
.InitialMulStep (InitialMulStep), .notFracYFromD1A (notFracYFromD1A),
.notFracYFromD2A (notFracYFromD2A), .notFracYFromD3A (notFracYFromD3A),
.notNO_1 (notNO_1), .notStickyInForSR (notStickyInForSR),
.OprSNnotDB (OprSNnotDB), .RomOutputs_18 (RomOutputs_18),
.RomOutputs_20 (RomOutputs_20), .RomOutputs_27 (RomOutputs_27),
.RomOutputs_55 (RomOutputs_55), .SignResult (SignResult),
.SNnotDB (SNnotDB), .SROneMore (SROneMore), .SRToSticky (SRToSticky),
.SumCarryLoadEn (SumCarryLoadEn), .SumOut0 (SumOut0),
.ConditionCodes (ConditionCodes), .Excep (Excep),
.FracAregLC (FracAregLC), .FracBregLC (FracBregLC),
.FracRound (FracRound), .FracYbusLSBs (FracYbusLSBs),
.InForCreg (InForCreg), .InForCregDB (InForCregDB),
.InFromCregOr0 (InFromCregOr0), .LIB (LIB), .MulLenSel (MulLenSel),
.notsh (notsh), .Pos (Pos), .RomOutputs_32_29 (RomOutputs_32_29),
.RomOutputs_46_44 (RomOutputs_46_44), .SelectedMIptr(SelectedMIptr ),
.Shift (Shift), .SRControl (SRControl), .TopBitsIn (TopBitsIn),
.Zero (Zero),
.ss_scan_mode (ss_scan_mode),
.fp_ctl_scan_in (fp_exp_scan_out),
.fp_ctl_scan_out (fp_ctl_scan_out) );
// Instance of the ROM Megacell
fp_rom fprom ( .ss_clock(ss_clock),
.rom_adr(SelectedMIptr),
.rom_dout(U_RomOutputs),
.rom_scan_out(fp_rom_scan_out),
.rom_scan_in(fp_ctl_scan_out),
.ss_scan_mode(ss_scan_mode) );
// exponent datapath
fp_exp fpexp ( .ss_clock (ss_clock ), .SNnotDB (SNnotDB ),
.OprSNnotDB (OprSNnotDB ), .RS2_exp (fprf_dout2[62:52] ),
.RS1_exp (fprf_dout1[62:52] ), .FracAregForInt (AregMaster_57_40[54:47] ),
.notSLFromNorm ({notNO_1, notsh[3:1]} ), .ShiftBy8 (RomOutputs_20 ),
.ExpAregLoadEn (ExpAregLoadEn ), .ExpAregLC0 (ExpAregLC0 ),
.ExpAregLC1 (ExpAregLC1 ), .ExpBregLoadEn (ExpBregLoadEn ),
.ExpBregLC0 (ExpBregLC0 ), .ExpBregLC1 (ExpBregLC1 ),
.ExpXCtl0 (RomOutputs_32_29[29] ), .ExpXCtl1 (RomOutputs_32_29[30] ),
.ExpYCtl0 (RomOutputs_32_29[31] ), .ExpYCtl1 (RomOutputs_32_29[32] ),
.Sub(RomOutputs_27 ), .CarryIn (CarryIn ), .Constantb (Constantb ),
.Constantc (Constantc ), .Constantd (Constantd ),
.Constante (Constante ), .Constantf (Constantf ),
.Constantg (Constantg ), .Constanth (Constanth ),
.AregMasterBufOut (ExpIn ), .ExpResultBuf (ExpResult ),
.notExpShiftResult (notExpShiftResult[12:0] ),
.ExpZero (Conditionals_12 ), .ExpResult_12 (Conditionals_3 ),
.SLControl (SLControl ), .notAInfNaN (notAInfNAN ),
.notAZeroDenorm (notAZeroDenorm ), .notBInfNaN (notBInfNAN ),
.notBZeroDenorm (notBZeroDenorm ), .notUnderflow (notExpUnderflow ),
.notOverflow (notExpOverflow ), .notExpException (notExpException ),
.ss_scan_mode (ss_scan_mode),
.fp_exp_scan_in (fp_fpc_scan_out),
.fp_exp_scan_out (fp_exp_scan_out) );
// fraction datapath
fp_frac fpfrac (.ss_clock (ss_clock ), .FracAregLoadEn (FracAregLoadEn),
.FracAregLC (FracAregLC ), .FracBregLoadEn (FracBregLoadEn ),
.FracBregLC (FracBregLC ), .FracCregLoadEn (FracCregLoadEn ),
.FracCregLC (FracCregLC ), .FracTregLoadEn (FracTregLoadEn ),
.FracYbusLSBs (FracYbusLSBs ), .InFromCregOr0 (InFromCregOr0 ),
.InForCreg (InForCreg ), .InForCregDB (InForCregDB ),
.Constantb (RomOutputs_46_44[45] ), .Constantd (FracRound[4] ),
.Constante (FracRound[3] ), .Constantf (FracRound[2] ),
.Constantg (FracRound[1] ), .Constanth (FracRound[0] ),
.RS2_frac (fprf_dout2[54:0] ), .RS1_frac (fprf_dout1[54:0] ),
.SNnotDB (SNnotDB ), .OprSNnotDB(OprSNnotDB), .SRControl (SRControl ),
.SROneMore (SROneMore ), .SRToSticky (SRToSticky ),
.SLControl (SLControl ), .LIB (LIB ), .TopBitsIn (TopBitsIn ),
.notStickyInForSR (notStickyInForSR ), .Shift (Shift ),
.Pos (Pos ), .Zero (Zero ), .InitialMulStep (InitialMulStep ),
.InitialCarryBit (InitialCarryBit ),
.SumCarryLoadEn (SumCarryLoadEn ), .MulLenSel (MulLenSel ),
.SumOut0 (SumOut0 ), .CarryOut0 (CarryOut0 ), .CarryOut3 (CarryOut3 ),
.LeftnotRight (RomOutputs_18 ), .FracALUOpSub (RomOutputs_46_44[44] ),
.FracALUOpDiv (RomOutputs_55 ), .notFracYFromD1 (notFracYFromD1A ),
.notFracYFromD2 (notFracYFromD2A ), .notFracYFromD3 (notFracYFromD3A),
.FracXFromB (RomOutputs_46_44[46] ), .notSticky4 (notSticky4 ),
.Sticky2 (Sticky2 ), .notSticky1 (notSticky1 ),
.StickyExtra (StickyExtra ), .Creg_30_29 (CregSNBits ),
.Creg_56_55 (CregInSL2SQRT ), .BregMaster_57 (FracBregSign ),
.BregMaster_54 (BregFPMSBM1 ), .notMultip (notMultip ),
.notAM31_3 (notAM31_3 ), .notAM2_0 (notAM2_0 ),
.StickyForSR1 (StickyForSR1 ),
.AregMaster_57_40 (AregMaster_57_40[57:40] ),
.AregMaster_32 (AregMaster_32 ),
.AregMaster_7_0 (AregMaster_7_0[7:0] ),
.notAregMasterFPMSBP1 (notAregMasterFPMSBP1 ),
.Treg_1_0 (TregLSBs ), .SumInLSBs (SumInLSBs ),
.CarryInLSBs (CarryInLSBs ), .SALSBs (SALSBs ), .SBLSBs (SBLSBs ),
.SCLSBs (SCLSBs ), .CALSB (CALSB ), .CBLSB (CBLSB ), .CCLSB (CCLSB ),
.notFracZero (notFracZero ), .FracZero (FracZero ),
.FracResult_57 (FracAgtB ), .SubResultNorm (SubResultNorm ),
.FracResult_56 (Conditionals_10 ),
.FracResult_55_52 (StepRemBits ), .notPossibleOv (notPossibleOv ),
.FracResultBufout (FracResult ),
.ss_scan_mode (ss_scan_mode),
.fp_frac_scan_in (fp_rom_scan_out),
.fp_frac_scan_out (fp_frac_scan_out) );
fp_fpm fpfpm (.fprf_din( fprf_din[63:0] ),
.fpm_inx(fpm_inx), .fpm_unfin(fpm_unfin),
.fprf_dout1( fprf_dout1[63:0] ), .fprf_dout2( fprf_dout2[63:0] ),
.ld_fpu_w( ld_fpu_w[63:0] ),
.FracResult( FracResult[54:3] ),
.ExpResult( ExpResult[10:0] ),
.SignResult(SignResult),
.fpm_inst( fpm_inst[1:0] ),
.rnd_mode( RoundingMode[1:0] ),
.res_select( res_select[1:0] ),
.rfin_select(rfin_select),
.fpm_start(fpm_start),
.ss_clock(ss_clock),
.ss_scan_mode (ss_scan_mode),
.fp_fpm_scan_in(fp_frac_scan_out),
.fp_fpm_scan_out(fp_fpm_scan_out) );
// Added spare cells
spares fpufpc_spares ();
endmodule
This page: |
Created: | Thu Aug 19 12:01:04 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/rtl/fpufpc.v
|