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/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)fp_rw.v
***
****************************************************************************
****************************************************************************/

//  @(#)fp_rw.v	1.4  4/9/92
//
// **************************************************************
//  High-level verilog model of the FPU register file read/write datapath
//
// **************************************************************

[Up: fp_fpm fprw]
module fp_rw (ld_fpu_w, FracResult, ExpResult, SignResult,
		fpm_frac, fpm_exp, fpm_sign, res_select, rfin_select,
		fprf_din );

input [63:0] ld_fpu_w;		// data bus in from the D-cache

input [54:3] FracResult;	// Fraction result from Meiko FPP
input [10:0] ExpResult;		// Exponent result from Meiko FPP
input	SignResult;		// Sign result from Meiko FPP

input [51:0] fpm_frac;		// Fraction result from multiplier
input [10:0] fpm_exp;		// Exponent result from multiplier
input	fpm_sign;		// Sign result from multiplier

input [1:0] res_select;		// control for result select mux
input	rfin_select;		// selects result or d-cache bus


output [63:0] fprf_din;		// input to the register file


wire [63:0] result ;

ME_MUX41H32 resmux1 (result[63:32],
		 {fpm_sign, fpm_exp[10:0], fpm_frac[51:32]},	// fmul dbl
		 {fpm_sign, fpm_exp[ 7:0], fpm_frac[22: 0]},	// fmul sgl
		 {SignResult, ExpResult[10:0], FracResult[54:35]},	// dbl
		 {SignResult, ExpResult[7:0], FracResult[54:32]},	// sgl
		 res_select[0], res_select[1] );

ME_MUX41H32 resmux0 (result[31:0],
		 fpm_frac[31:0],				// fmul dbl
		 {fpm_sign, fpm_exp[ 7:0], fpm_frac[22: 0]},	// fmul sgl
		 FracResult[34:3],				// dbl
		 {SignResult, ExpResult[7:0], FracResult[54:32]},	// sgl
		 res_select[0], res_select[1] );

ME_MUX21H32 rfinmux1 (fprf_din[63:32], result[63:32], ld_fpu_w[63:32],
			rfin_select);

ME_MUX21H32 rfinmux0 (fprf_din[31:0], result[31:0], ld_fpu_w[31:0],
			rfin_select);

endmodule
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This page: Created:Thu Aug 19 12:00:52 1999
From: ../../../sparc_v8/ssparc/fpu/fp_fpm/rtl/fp_rw.v

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