/******************************************************************************/ 
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/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)fp_fpm.v
***
****************************************************************************
****************************************************************************/

//  @(#)fp_fpm.v	1.5  10/23/92
//
// **************************************************************
//  fp_fpm -- top-level interconnect for the IEEE multiplier
// **************************************************************


module fp_fpm (
	    fprf_din,
	    fpm_inx,
	    fpm_unfin,
	    fprf_dout1,
	    fprf_dout2,
	    ld_fpu_w,
	    FracResult,
	    ExpResult,
	    SignResult,
	    fpm_inst,
	    rnd_mode,
	    res_select,
	    rfin_select,
	    fpm_start,
	    ss_clock,
	    ss_scan_mode,
	    fp_fpm_scan_in,
	    fp_fpm_scan_out
	    );

    //prop CELLCLASS "MODULE"

    output [63:0] fprf_din;	// fp_fpm output bus to reg file write port
    output fpm_inx;		// Inexact flag.
				// 52-bit add + 4 gate delays into X3 stage
    output fpm_unfin;		// Multiplier unfinished signal (special
				// case detected).  Registered output.
    input  [63:0] fprf_dout1;	// 64-bit operand X (multiplicand)
				// Registered in X1 stage
    input  [63:0] fprf_dout2;	// 64-bit operand Y (multiplier)
				// Registered in X1 stage
    input  [63:0] ld_fpu_w;	// 64-bit D-cache output bus
    input  [54:3] FracResult;	// Meiko FPU fp_frac result bus
    input  [10:0] ExpResult;	// Meiko FPU fp_exp result bus
    input	  SignResult;	// Meiko FPU result sign bit
    input  [1:0] fpm_inst;	// FMULs=00, FMULd=01, FsMULd=10
				// Expected valid same time as fpm_start
    input  [1:0]  rnd_mode;	// rounding mode (same as FSR[31:30])
				// Expected valid in X3 stage
    input  [1:0] res_select;	// control for fpu result select mux
    input  rfin_select;		// selects fpu result or d-cache bus
    input  fpm_start;		// go-ahead signal
				// Should be active for 1 cycle only.
    input  ss_clock;		// single phase master clock
    input  ss_scan_mode;
    input  fp_fpm_scan_in;
    output fp_fpm_scan_out;

    wire [51:0] fpm_frac;	// 52-bit fraction (no sign, no implicit).
    wire [10:0] fpm_exp;	// 11-bit exponent (single is right justified)
    wire fpm_sign;		// Product sign bit.
    wire fpm_inx;		// Inexact flag.
    wire fpm_unfin;		// Multiplier unfinished signal (special
				// case detected)
    wire [63:0] fprf_dout1;	// 63-bit operand X (multiplicand)
    wire [63:0] fprf_dout2;	// 63-bit operand Y (multiplier)
    wire [1:0]  rnd_mode;
    wire fpm_start;
    wire ss_clock;

    wire frac_ovf ;
    wire fpm_exp_scan_out;

				// multiplier fraction (and sign) datapath
    fpm_frac fpmfrac(
                    .ss_scan_mode(ss_scan_mode),
                    .fpm_frac_scan_in(fpm_exp_scan_out),
                    .fpm_frac_scan_out(fp_fpm_scan_out),
		    .fpm_frac(fpm_frac[51:0]),
		    .fpm_sign(fpm_sign),
		    .fpm_inx(fpm_inx),
		    .frac_ovf(frac_ovf),
		    .rs1_s(fprf_dout1[63]),		// rs1_s
		    .rs1_m(fprf_dout1[54:0]),		// rs1_m[54:0]
		    .rs2_s(fprf_dout2[63]),		// rs2_s
		    .rs2_m(fprf_dout2[54:0]),		// rs2_m[54:0]
		    .fpm_inst(fpm_inst[1:0]),
		    .rnd_mode(rnd_mode[1:0]),
		    .fpm_start(fpm_start),
		    .fpm_clk(ss_clock)
		    );

				// multiplier exponent datapath
    fpm_exp fpmexp (
                   fp_fpm_scan_in,
                   fpm_exp_scan_out,
                   ss_scan_mode,
		   fpm_exp[10:0],
		   fpm_unfin,
		   frac_ovf,
		   fprf_dout1[62:52],		// rs1_e[10:0]
		   fprf_dout2[62:52],		// rs2_e[10:0]
		   fpm_inst[1:0],
		   fpm_start,
		   ss_clock
		   );


				// reg file Read Write datapath
    fp_rw fprw (
		.ld_fpu_w(ld_fpu_w), .FracResult(FracResult),
		.ExpResult(ExpResult), .SignResult(SignResult),
		.fpm_frac(fpm_frac), .fpm_exp(fpm_exp),
		.fpm_sign(fpm_sign),
		.res_select(res_select), .rfin_select(rfin_select),
		.fprf_din(fprf_din)
		);

endmodule