.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_46_po),
.PO (b_47_po
),
.SO (b_47_so
),
.IT (b_47_i),
.X (b_47)
) ;
// Bidirectional pad for b_48 (ad[29]), enabled by ADEnable
PCI_BI b_48_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_48_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_47_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_47_po),
.PO (b_48_po
),
.SO (b_48_so
),
.IT (b_48_i),
.X (b_48)
) ;
// Dummy pad vdd2_49 ()
// vdd
// Dummy pad vss2_50 ()
// vss
// Bidirectional pad for b_51 (ad[30]), enabled by ADEnable
PCI_BI b_51_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_51_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_48_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_48_po),
.PO (b_51_po
),
.SO (b_51_so
),
.IT (b_51_i),
.X (b_51)
) ;
// Bidirectional pad for b_52 (ad[31]), enabled by ADEnable
PCI_BI b_52_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_52_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_51_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_51_po),
.PO (b_52_po
),
.SO (b_52_so
),
.IT (b_52_i),
.X (b_52)
) ;
// Tristate enable cell for frameEn
ENABLE frameEn_cell(
.EN (frameEn),
.SHIFT (bscan_shift),
.SI (b_52_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (frameEn_enc_l
),
.SO (frameEn_so
)
) ;
// Bidirectional pad for b_53 (frame_l), enabled by frameEn
PCI_BI b_53_pad(
.ENC_ (frameEn_enc_l),
.OT (b_53_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (frameEn_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_52_po),
.PO (b_53_po
),
.SO (b_53_so
),
.IT (b_53_i),
.X (b_53)
) ;
// Dummy pad vdd_54 ()
// vdd
// Dummy pad vss_55 ()
// vss
// Tristate enable cell for trdyEn
ENABLE trdyEn_cell(
.EN (trdyEn),
.SHIFT (bscan_shift),
.SI (b_53_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (trdyEn_enc_l
),
.SO (trdyEn_so
)
) ;
// Bidirectional pad for b_56 (trdy_l), enabled by trdyEn
PCI_BI b_56_pad(
.ENC_ (trdyEn_enc_l),
.OT (b_56_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (trdyEn_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_53_po),
.PO (b_56_po
),
.SO (b_56_so
),
.IT (b_56_i),
.X (b_56)
) ;
// Tristate enable cell for irdyEn
ENABLE irdyEn_cell(
.EN (irdyEn),
.SHIFT (bscan_shift),
.SI (b_56_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (irdyEn_enc_l
),
.SO (irdyEn_so
)
) ;
// Bidirectional pad for b_57 (irdy_l), enabled by irdyEn
PCI_BI b_57_pad(
.ENC_ (irdyEn_enc_l),
.OT (b_57_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (irdyEn_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_56_po),
.PO (b_57_po
),
.SO (b_57_so
),
.IT (b_57_i),
.X (b_57)
) ;
// Tristate enable cell for stopEn
ENABLE stopEn_cell(
.EN (stopEn),
.SHIFT (bscan_shift),
.SI (b_57_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (stopEn_enc_l
),
.SO (stopEn_so
)
) ;
// Bidirectional pad for b_58 (stop_l), enabled by stopEn
PCI_BI b_58_pad(
.ENC_ (stopEn_enc_l),
.OT (b_58_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (stopEn_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_57_po),
.PO (b_58_po
),
.SO (b_58_so
),
.IT (b_58_i),
.X (b_58)
) ;
// Tristate enable cell for devselEn
ENABLE devselEn_cell(
.EN (devselEn),
.SHIFT (bscan_shift),
.SI (b_58_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (devselEn_enc_l
),
.SO (devselEn_so
)
) ;
// Bidirectional pad for b_59 (devsel_l), enabled by devselEn
PCI_BI b_59_pad(
.ENC_ (devselEn_enc_l),
.OT (b_59_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (devselEn_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_58_po),
.PO (b_59_po
),
.SO (b_59_so
),
.IT (b_59_i),
.X (b_59)
) ;
// Dummy pad vdd_60 ()
// vdd
// Dummy pad vss_61 ()
// vss
// Tristate enable cell for pci_gnt_oen
ENABLE pci_gnt_oen_cell(
.EN (pci_gnt_oen),
.SHIFT (bscan_shift),
.SI (b_59_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (pci_gnt_oen_enc_l
),
.SO (pci_gnt_oen_so
)
) ;
// Bidirectional pad for o_62 (pci_gnt_l[0]), enabled by pci_gnt_oen
PCI_BI o_62_pad(
.ENC_ (pci_gnt_oen_enc_l),
.OT (o_62_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (pci_gnt_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_59_po),
.PO (o_62_po
),
.SO (o_62_so
),
.IT (o_62_i),
.X (o_62)
) ;
// Bidirectional pad for o_63 (pci_gnt_l[1]), enabled by pci_gnt_oen
PCI_BI o_63_pad(
.ENC_ (pci_gnt_oen_enc_l),
.OT (o_63_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_62_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (o_62_po),
.PO (o_63_po
),
.SO (o_63_so
),
.IT (o_63_i),
.X (o_63)
) ;
// Bidirectional pad for o_64 (pci_gnt_l[2]), enabled by pci_gnt_oen
PCI_BI o_64_pad(
.ENC_ (pci_gnt_oen_enc_l),
.OT (o_64_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_63_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (o_63_po),
.PO (o_64_po
),
.SO (o_64_so
),
.IT (o_64_i),
.X (o_64)
) ;
// Dummy pad vdd2_65 ()
// vdd
// Dummy pad vss2_66 ()
// vss
// Bidirectional pad for o_67 (pci_gnt_l[3]), enabled by pci_gnt_oen
PCI_BI o_67_pad(
.ENC_ (pci_gnt_oen_enc_l),
.OT (o_67_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_64_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (o_64_po),
.PO (o_67_po
),
.SO (o_67_so
),
.IT (o_67_i),
.X (o_67)
) ;
// Tristate enable cell for pci_req_oen
ENABLE pci_req_oen_cell(
.EN (pci_req_oen),
.SHIFT (bscan_shift),
.SI (o_67_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (pci_req_oen_enc_l
),
.SO (pci_req_oen_so
)
) ;
// Bidirectional pad for i_68 (pci_req_l[0]), enabled by pci_req_oen
PCI_BI i_68_pad(
.ENC_ (pci_req_oen_enc_l),
.OT (i_68_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (pci_req_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (o_67_po),
.PO (i_68_po
),
.SO (i_68_so
),
.IT (i_68_i),
.X (i_68)
) ;
// Dummy pad vdd_69 ()
// vdd
// Bidirectional pad for i_70 (pci_req_l[2]), enabled by pci_req_oen
PCI_BI i_70_pad(
.ENC_ (pci_req_oen_enc_l),
.OT (i_70_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (i_68_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (i_68_po),
.PO (i_70_po
),
.SO (i_70_so
),
.IT (i_70_i),
.X (i_70)
) ;
// Bidirectional pad for i_71 (pci_req_l[1]), enabled by pci_req_oen
PCI_BI i_71_pad(
.ENC_ (pci_req_oen_enc_l),
.OT (i_71_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (i_70_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (i_70_po),
.PO (i_71_po
),
.SO (i_71_so
),
.IT (i_71_i),
.X (i_71)
) ;
// Dummy pad vss_72 ()
// vss
// Bidirectional pad for i_73 (pci_req_l[3]), enabled by pci_req_oen
PCI_BI i_73_pad(
.ENC_ (pci_req_oen_enc_l),
.OT (i_73_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (i_71_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (i_71_po),
.PO (i_73_po
),
.SO (i_73_so
),
.IT (i_73_i),
.X (i_73)
) ;
// Tristate enable cell for pci_clk0_oen
ENABLE pci_clk0_oen_cell(
.EN (pci_clk0_oen),
.SHIFT (bscan_shift),
.SI (i_73_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (pci_clk0_oen_enc_l
),
.SO (pci_clk0_oen_so
)
) ;
// Bidirectional pad for b_74 (pci_clk0), enabled by pci_clk0_oen
PCI_BI b_74_pad(
.ENC_ (pci_clk0_oen_enc_l),
.OT (b_74_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (pci_clk0_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (i_73_po),
.PO (b_74_po
),
.SO (b_74_so
),
.IT (b_74_i),
.X (b_74)
) ;
// Tristate enable cell for pci_clk1_oen
ENABLE pci_clk1_oen_cell(
.EN (pci_clk1_oen),
.SHIFT (bscan_shift),
.SI (b_74_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (pci_clk1_oen_enc_l
),
.SO (pci_clk1_oen_so
)
) ;
// Bidirectional pad for b_75 (pci_clk1), enabled by pci_clk1_oen
PCI_BI b_75_pad(
.ENC_ (pci_clk1_oen_enc_l),
.OT (b_75_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (pci_clk1_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_74_po),
.PO (b_75_po
),
.SO (b_75_so
),
.IT (b_75_i),
.X (b_75)
) ;
// Dummy pad vdd2_76 ()
// vdd
// Dummy pad vss2_77 ()
// vss
// Tristate enable cell for pci_clk2_oen
ENABLE pci_clk2_oen_cell(
.EN (pci_clk2_oen),
.SHIFT (bscan_shift),
.SI (b_75_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (pci_clk2_oen_enc_l
),
.SO (pci_clk2_oen_so
)
) ;
// Bidirectional pad for b_78 (pci_clk2), enabled by pci_clk2_oen
PCI_BI b_78_pad(
.ENC_ (pci_clk2_oen_enc_l),
.OT (b_78_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (pci_clk2_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_75_po),
.PO (b_78_po
),
.SO (b_78_so
),
.IT (b_78_i),
.X (b_78)
) ;
// Tristate enable cell for cbeEnable
ENABLE cbeEnable_cell(
.EN (cbeEnable),
.SHIFT (bscan_shift),
.SI (b_78_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (cbeEnable_enc_l
),
.SO (cbeEnable_so
)
) ;
// Bidirectional pad for b_79 (cbe[0]), enabled by cbeEnable
PCI_BI b_79_pad(
.ENC_ (cbeEnable_enc_l),
.OT (b_79_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (cbeEnable_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_78_po),
.PO (b_79_po
),
.SO (b_79_so
),
.IT (b_79_i),
.X (b_79)
) ;
// Dummy pad vdd_80 ()
// vdd
// Bidirectional pad for b_81 (cbe[1]), enabled by cbeEnable
PCI_BI b_81_pad(
.ENC_ (cbeEnable_enc_l),
.OT (b_81_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_79_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_79_po),
.PO (b_81_po
),
.SO (b_81_so
),
.IT (b_81_i),
.X (b_81)
) ;
// Bidirectional pad for b_82 (cbe[2]), enabled by cbeEnable
PCI_BI b_82_pad(
.ENC_ (cbeEnable_enc_l),
.OT (b_82_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_81_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_81_po),
.PO (po_out),
.SO (scan_out),
.IT (b_82_i),
.X (b_82)
) ;
// Dummy pad vss_83 ()
// vss
endmodule
This page: |
Created: | Thu Aug 19 12:02:15 1999 |
| From: |
../../../sparc_v8/ssparc/iopads/rtl/leftpads.v
|