/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)leftpads.v
***
****************************************************************************
****************************************************************************/
// @(#)leftpads.v 1.17 10/31/96
// Automatically generated from iopad_order rev 1.9 by mkiopads, rev 1.9
![[Up: iopads leftpads]](v2html-up.gif)
module leftpads
( // Pads listed in top-to-bottom order:
// vss_1, // vss
b_2, // ad[0]
b_2_o,
b_2_i,
// vdd_3, // vdd
// vdd_4, // vdd
// vss_5, // vss
b_6, // ad[1]
b_6_o,
b_6_i,
b_7, // ad[2]
b_7_o,
b_7_i,
ADEnable, // ADEnable
b_8, // ad[3]
b_8_o,
b_8_i,
b_9, // ad[4]
b_9_o,
b_9_i,
// vdd_10, // vdd
// vss_11, // vss
b_12, // ad[5]
b_12_o,
b_12_i,
b_13, // ad[6]
b_13_o,
b_13_i,
b_14, // ad[7]
b_14_o,
b_14_i,
// vdd2_15, // vdd
// vss2_16, // vss
b_17, // ad[8]
b_17_o,
b_17_i,
b_18, // ad[9]
b_18_o,
b_18_i,
b_19, // ad[10]
b_19_o,
b_19_i,
b_20, // ad[11]
b_20_o,
b_20_i,
// vdd_21, // vdd
// vss_22, // vss
b_23, // ad[12]
b_23_o,
b_23_i,
b_24, // ad[13]
b_24_o,
b_24_i,
b_25, // ad[14]
b_25_o,
b_25_i,
// vdd_26, // vdd
// vss_27, // vss
b_28, // ad[15]
b_28_o,
b_28_i,
b_29, // ad[16]
b_29_o,
b_29_i,
b_30, // ad[17]
b_30_o,
b_30_i,
b_31, // ad[18]
b_31_o,
b_31_i,
// vdd2_32, // vdd
// vss2_33, // vss
b_34, // ad[19]
b_34_o,
b_34_i,
b_35, // ad[20]
b_35_o,
b_35_i,
b_36, // ad[21]
b_36_o,
b_36_i,
// vdd_37, // vdd
// vss_38, // vss
b_39, // ad[22]
b_39_o,
b_39_i,
b_40, // ad[23]
b_40_o,
b_40_i,
b_41, // ad[24]
b_41_o,
b_41_i,
b_42, // ad[25]
b_42_o,
b_42_i,
// vdd_43, // vdd
// vss_44, // vss
b_45, // ad[26]
b_45_o,
b_45_i,
b_46, // ad[27]
b_46_o,
b_46_i,
b_47, // ad[28]
b_47_o,
b_47_i,
b_48, // ad[29]
b_48_o,
b_48_i,
// vdd2_49, // vdd
// vss2_50, // vss
b_51, // ad[30]
b_51_o,
b_51_i,
b_52, // ad[31]
b_52_o,
b_52_i,
frameEn, // frameEn
b_53, // frame_l
b_53_o,
b_53_i,
// vdd_54, // vdd
// vss_55, // vss
trdyEn, // trdyEn
b_56, // trdy_l
b_56_o,
b_56_i,
irdyEn, // irdyEn
b_57, // irdy_l
b_57_o,
b_57_i,
stopEn, // stopEn
b_58, // stop_l
b_58_o,
b_58_i,
devselEn, // devselEn
b_59, // devsel_l
b_59_o,
b_59_i,
// vdd_60, // vdd
// vss_61, // vss
pci_gnt_oen, // pci_gnt_oen
o_62, // pci_gnt_l[0]
o_62_o,
o_62_i,
o_63, // pci_gnt_l[1]
o_63_o,
o_63_i,
o_64, // pci_gnt_l[2]
o_64_o,
o_64_i,
// vdd2_65, // vdd
// vss2_66, // vss
o_67, // pci_gnt_l[3]
o_67_o,
o_67_i,
pci_req_oen, // pci_req_oen
i_68, // pci_req_l[0]
i_68_o,
i_68_i,
// vdd_69, // vdd
i_70, // pci_req_l[2]
i_70_o,
i_70_i,
i_71, // pci_req_l[1]
i_71_o,
i_71_i,
// vss_72, // vss
i_73, // pci_req_l[3]
i_73_o,
i_73_i,
pci_clk0_oen, // pci_clk0_oen
b_74, // pci_clk0
b_74_o,
b_74_i,
pci_clk1_oen, // pci_clk1_oen
b_75, // pci_clk1
b_75_o,
b_75_i,
// vdd2_76, // vdd
// vss2_77, // vss
pci_clk2_oen, // pci_clk2_oen
b_78, // pci_clk2
b_78_o,
b_78_i,
cbeEnable, // cbeEnable
b_79, // cbe[0]
b_79_o,
b_79_i,
// vdd_80, // vdd
b_81, // cbe[1]
b_81_o,
b_81_i,
b_82, // cbe[2]
b_82_o,
b_82_i,
// vss_83, // vss
bscan_clk_cap,
bscan_clk_upd,
w_input_tn,
bscan_shift,
bscan_sel_ff_out,
bscan_sel_ff_in,
pi_in,
scan_in,
po_out,
scan_out
) ;
inout b_2 ; // ad[0]
input b_2_o ;
output b_2_i ;
inout b_6 ; // ad[1]
input b_6_o ;
output b_6_i ;
inout b_7 ; // ad[2]
input b_7_o ;
output b_7_i ;
input ADEnable ; // ADEnable
inout b_8 ; // ad[3]
input b_8_o ;
output b_8_i ;
inout b_9 ; // ad[4]
input b_9_o ;
output b_9_i ;
inout b_12 ; // ad[5]
input b_12_o ;
output b_12_i ;
inout b_13 ; // ad[6]
input b_13_o ;
output b_13_i ;
inout b_14 ; // ad[7]
input b_14_o ;
output b_14_i ;
inout b_17 ; // ad[8]
input b_17_o ;
output b_17_i ;
inout b_18 ; // ad[9]
input b_18_o ;
output b_18_i ;
inout b_19 ; // ad[10]
input b_19_o ;
output b_19_i ;
inout b_20 ; // ad[11]
input b_20_o ;
output b_20_i ;
inout b_23 ; // ad[12]
input b_23_o ;
output b_23_i ;
inout b_24 ; // ad[13]
input b_24_o ;
output b_24_i ;
inout b_25 ; // ad[14]
input b_25_o ;
output b_25_i ;
inout b_28 ; // ad[15]
input b_28_o ;
output b_28_i ;
inout b_29 ; // ad[16]
input b_29_o ;
output b_29_i ;
inout b_30 ; // ad[17]
input b_30_o ;
output b_30_i ;
inout b_31 ; // ad[18]
input b_31_o ;
output b_31_i ;
inout b_34 ; // ad[19]
input b_34_o ;
output b_34_i ;
inout b_35 ; // ad[20]
input b_35_o ;
output b_35_i ;
inout b_36 ; // ad[21]
input b_36_o ;
output b_36_i ;
inout b_39 ; // ad[22]
input b_39_o ;
output b_39_i ;
inout b_40 ; // ad[23]
input b_40_o ;
output b_40_i ;
inout b_41 ; // ad[24]
input b_41_o ;
output b_41_i ;
inout b_42 ; // ad[25]
input b_42_o ;
output b_42_i ;
inout b_45 ; // ad[26]
input b_45_o ;
output b_45_i ;
inout b_46 ; // ad[27]
input b_46_o ;
output b_46_i ;
inout b_47 ; // ad[28]
input b_47_o ;
output b_47_i ;
inout b_48 ; // ad[29]
input b_48_o ;
output b_48_i ;
inout b_51 ; // ad[30]
input b_51_o ;
output b_51_i ;
inout b_52 ; // ad[31]
input b_52_o ;
output b_52_i ;
input frameEn ; // frameEn
inout b_53 ; // frame_l
input b_53_o ;
output b_53_i ;
input trdyEn ; // trdyEn
inout b_56 ; // trdy_l
input b_56_o ;
output b_56_i ;
input irdyEn ; // irdyEn
inout b_57 ; // irdy_l
input b_57_o ;
output b_57_i ;
input stopEn ; // stopEn
inout b_58 ; // stop_l
input b_58_o ;
output b_58_i ;
input devselEn ; // devselEn
inout b_59 ; // devsel_l
input b_59_o ;
output b_59_i ;
input pci_gnt_oen ; // pci_gnt_oen
inout o_62 ; // pci_gnt_l[0]
input o_62_o ;
output o_62_i ;
inout o_63 ; // pci_gnt_l[1]
input o_63_o ;
output o_63_i ;
inout o_64 ; // pci_gnt_l[2]
input o_64_o ;
output o_64_i ;
inout o_67 ; // pci_gnt_l[3]
input o_67_o ;
output o_67_i ;
input pci_req_oen ; // pci_req_oen
inout i_68 ; // pci_req_l[0]
input i_68_o ;
output i_68_i ;
inout i_70 ; // pci_req_l[2]
input i_70_o ;
output i_70_i ;
inout i_71 ; // pci_req_l[1]
input i_71_o ;
output i_71_i ;
inout i_73 ; // pci_req_l[3]
input i_73_o ;
output i_73_i ;
input pci_clk0_oen ; // pci_clk0_oen
inout b_74 ; // pci_clk0
input b_74_o ;
output b_74_i ;
input pci_clk1_oen ; // pci_clk1_oen
inout b_75 ; // pci_clk1
input b_75_o ;
output b_75_i ;
input pci_clk2_oen ; // pci_clk2_oen
inout b_78 ; // pci_clk2
input b_78_o ;
output b_78_i ;
input cbeEnable ; // cbeEnable
inout b_79 ; // cbe[0]
input b_79_o ;
output b_79_i ;
inout b_81 ; // cbe[1]
input b_81_o ;
output b_81_i ;
inout b_82 ; // cbe[2]
input b_82_o ;
output b_82_i ;
input bscan_clk_cap ;
input bscan_clk_upd ;
input w_input_tn ;
input bscan_shift ;
input bscan_sel_ff_out ;
input bscan_sel_ff_in ;
input pi_in ;
input scan_in ;
output po_out ;
output scan_out ;
// Dummy pad vss_1 ()
// vss
// Bidirectional pad for b_2 (ad[0]), enabled by ADEnable
PCI_BI b_2_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_2_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (scan_in),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (pi_in),
.PO (b_2_po),
.SO (b_2_so),
.IT (b_2_i),
.X (b_2)
) ;
// Dummy pad vdd_3 ()
// vdd
// Dummy pad vdd_4 ()
// vdd
// Dummy pad vss_5 ()
// vss
// Bidirectional pad for b_6 (ad[1]), enabled by ADEnable
PCI_BI b_6_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_6_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_2_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_2_po),
.PO (b_6_po),
.SO (b_6_so),
.IT (b_6_i),
.X (b_6)
) ;
// Bidirectional pad for b_7 (ad[2]), enabled by ADEnable
PCI_BI b_7_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_7_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_6_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_6_po),
.PO (b_7_po),
.SO (b_7_so),
.IT (b_7_i),
.X (b_7)
) ;
// Tristate enable cell for ADEnable
ENABLE ADEnable_cell(
.EN (ADEnable),
.SHIFT (bscan_shift),
.SI (b_7_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (ADEnable_enc_l),
.SO (ADEnable_so)
) ;
// Bidirectional pad for b_8 (ad[3]), enabled by ADEnable
PCI_BI b_8_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_8_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (ADEnable_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_7_po),
.PO (b_8_po),
.SO (b_8_so),
.IT (b_8_i),
.X (b_8)
) ;
// Bidirectional pad for b_9 (ad[4]), enabled by ADEnable
PCI_BI b_9_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_9_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_8_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_8_po),
.PO (b_9_po),
.SO (b_9_so),
.IT (b_9_i),
.X (b_9)
) ;
// Dummy pad vdd_10 ()
// vdd
// Dummy pad vss_11 ()
// vss
// Bidirectional pad for b_12 (ad[5]), enabled by ADEnable
PCI_BI b_12_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_12_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_9_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_9_po),
.PO (b_12_po),
.SO (b_12_so),
.IT (b_12_i),
.X (b_12)
) ;
// Bidirectional pad for b_13 (ad[6]), enabled by ADEnable
PCI_BI b_13_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_13_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_12_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_12_po),
.PO (b_13_po),
.SO (b_13_so),
.IT (b_13_i),
.X (b_13)
) ;
// Bidirectional pad for b_14 (ad[7]), enabled by ADEnable
PCI_BI b_14_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_14_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_13_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_13_po),
.PO (b_14_po),
.SO (b_14_so),
.IT (b_14_i),
.X (b_14)
) ;
// Dummy pad vdd2_15 ()
// vdd
// Dummy pad vss2_16 ()
// vss
// Bidirectional pad for b_17 (ad[8]), enabled by ADEnable
PCI_BI b_17_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_17_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_14_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_14_po),
.PO (b_17_po),
.SO (b_17_so),
.IT (b_17_i),
.X (b_17)
) ;
// Bidirectional pad for b_18 (ad[9]), enabled by ADEnable
PCI_BI b_18_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_18_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_17_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_17_po),
.PO (b_18_po),
.SO (b_18_so),
.IT (b_18_i),
.X (b_18)
) ;
// Bidirectional pad for b_19 (ad[10]), enabled by ADEnable
PCI_BI b_19_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_19_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_18_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_18_po),
.PO (b_19_po),
.SO (b_19_so),
.IT (b_19_i),
.X (b_19)
) ;
// Bidirectional pad for b_20 (ad[11]), enabled by ADEnable
PCI_BI b_20_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_20_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_19_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_19_po),
.PO (b_20_po),
.SO (b_20_so),
.IT (b_20_i),
.X (b_20)
) ;
// Dummy pad vdd_21 ()
// vdd
// Dummy pad vss_22 ()
// vss
// Bidirectional pad for b_23 (ad[12]), enabled by ADEnable
PCI_BI b_23_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_23_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_20_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_20_po),
.PO (b_23_po),
.SO (b_23_so),
.IT (b_23_i),
.X (b_23)
) ;
// Bidirectional pad for b_24 (ad[13]), enabled by ADEnable
PCI_BI b_24_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_24_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_23_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_23_po),
.PO (b_24_po),
.SO (b_24_so),
.IT (b_24_i),
.X (b_24)
) ;
// Bidirectional pad for b_25 (ad[14]), enabled by ADEnable
PCI_BI b_25_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_25_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_24_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_24_po),
.PO (b_25_po),
.SO (b_25_so),
.IT (b_25_i),
.X (b_25)
) ;
// Dummy pad vdd_26 ()
// vdd
// Dummy pad vss_27 ()
// vss
// Bidirectional pad for b_28 (ad[15]), enabled by ADEnable
PCI_BI b_28_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_28_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_25_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_25_po),
.PO (b_28_po),
.SO (b_28_so),
.IT (b_28_i),
.X (b_28)
) ;
// Bidirectional pad for b_29 (ad[16]), enabled by ADEnable
PCI_BI b_29_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_29_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_28_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_28_po),
.PO (b_29_po),
.SO (b_29_so),
.IT (b_29_i),
.X (b_29)
) ;
// Bidirectional pad for b_30 (ad[17]), enabled by ADEnable
PCI_BI b_30_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_30_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_29_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_29_po),
.PO (b_30_po),
.SO (b_30_so),
.IT (b_30_i),
.X (b_30)
) ;
// Bidirectional pad for b_31 (ad[18]), enabled by ADEnable
PCI_BI b_31_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_31_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_30_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_30_po),
.PO (b_31_po),
.SO (b_31_so),
.IT (b_31_i),
.X (b_31)
) ;
// Dummy pad vdd2_32 ()
// vdd
// Dummy pad vss2_33 ()
// vss
// Bidirectional pad for b_34 (ad[19]), enabled by ADEnable
PCI_BI b_34_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_34_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_31_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_31_po),
.PO (b_34_po),
.SO (b_34_so),
.IT (b_34_i),
.X (b_34)
) ;
// Bidirectional pad for b_35 (ad[20]), enabled by ADEnable
PCI_BI b_35_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_35_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_34_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_34_po),
.PO (b_35_po),
.SO (b_35_so),
.IT (b_35_i),
.X (b_35)
) ;
// Bidirectional pad for b_36 (ad[21]), enabled by ADEnable
PCI_BI b_36_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_36_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_35_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_35_po),
.PO (b_36_po),
.SO (b_36_so),
.IT (b_36_i),
.X (b_36)
) ;
// Dummy pad vdd_37 ()
// vdd
// Dummy pad vss_38 ()
// vss
// Bidirectional pad for b_39 (ad[22]), enabled by ADEnable
PCI_BI b_39_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_39_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_36_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_36_po),
.PO (b_39_po),
.SO (b_39_so),
.IT (b_39_i),
.X (b_39)
) ;
// Bidirectional pad for b_40 (ad[23]), enabled by ADEnable
PCI_BI b_40_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_40_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_39_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_39_po),
.PO (b_40_po),
.SO (b_40_so),
.IT (b_40_i),
.X (b_40)
) ;
// Bidirectional pad for b_41 (ad[24]), enabled by ADEnable
PCI_BI b_41_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_41_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_40_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_40_po),
.PO (b_41_po),
.SO (b_41_so),
.IT (b_41_i),
.X (b_41)
) ;
// Bidirectional pad for b_42 (ad[25]), enabled by ADEnable
PCI_BI b_42_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_42_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_41_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_41_po),
.PO (b_42_po),
.SO (b_42_so),
.IT (b_42_i),
.X (b_42)
) ;
// Dummy pad vdd_43 ()
// vdd
// Dummy pad vss_44 ()
// vss
// Bidirectional pad for b_45 (ad[26]), enabled by ADEnable
PCI_BI b_45_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_45_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_42_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_42_po),
.PO (b_45_po),
.SO (b_45_so),
.IT (b_45_i),
.X (b_45)
) ;
// Bidirectional pad for b_46 (ad[27]), enabled by ADEnable
PCI_BI b_46_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_46_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_45_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_45_po),
.PO (b_46_po),
.SO (b_46_so),
.IT (b_46_i),
.X (b_46)
) ;
// Bidirectional pad for b_47 (ad[28]), enabled by ADEnable
PCI_BI b_47_pad(
.ENC_ (ADEnable_enc_l),
.OT (b_47_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (b_46_so),
| This page: |
Created: | Thu Aug 19 12:02:14 1999 |
| From: |
../../../sparc_v8/ssparc/iopads/rtl/leftpads.v
|