/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// Instantiates the D cache RAM + D Tag RAM
module mc_d_tag_cache
(
dc_hld,
dc_do,
dc_ain,
dc_di,
dc_wle,
dc_be,
dc_power_down,
dc_iiddtn,
dt_scan_in,
dc_scan_out,
tg_strobe,
dt_do,
dt_di,
dt_val_in,
dt_val_out,
dt_be,
dt_be_vb,
dt_be_cntxt,
dt_at,
dt_acc_in,
dt_acc_out,
dt_cntx_in,
dt_cntx_out,
dt_index3,
dt_index2,
dt_index1,
dt_flush,
dt_flush_user,
dt_flush_user_cntx,
dt_hit,
scan_mode,
clkr,
clkl
);
input dc_power_down
; // Synchronous power down
input dc_iiddtn
;
//input [(`dc_msb-3):0] dc_ain ; // 2^10 cache lines
input [(12-3):0] dc_ain
;
input [63:0] dc_di
;
input dc_wle
;
input [7:0] dc_be
;
input dt_scan_in
;
input tg_strobe
;
output dc_scan_out
;
output [63:0] dc_do
;
//
output [18:0] dt_do
; // [31:13] actually
input [18:0] dt_di
; // [31:13] actually
input dt_val_in
;
output dt_val_out
;
input dt_be
;
input dt_be_vb
;
input dt_be_cntxt
;
input [4:0] dt_at
;
input [4:0] dt_acc_in
;
output [4:0] dt_acc_out
;
input [7:0] dt_cntx_in
;
output [7:0] dt_cntx_out
;
output dt_hit
;
input [1:0] dc_hld
;
input dt_index3
;
input dt_index2
;
input dt_index1
;
input dt_flush
;
input dt_flush_user
;
input dt_flush_user_cntx
;
input scan_mode
;
input clkr
, clkl
;
// Scan connected D$ -> DT
wire dt_scan_out
;
// Signals going between D$ and DT only
wire dt_power_down
; // Because only 1 powerdown f/f in D$
wire dt_wle
; // Because only 1 wle f/f in D$
//wire [`dc_msb:4] dt_ain ; // Address f/f's shared between D$ & DT
wire [12:4] dt_ain
;
mc_dcache dcache_data (
.dt_di (dt_di[18:0]),
.dt_val_in (dt_val_in),
.dt_cntx_in (dt_cntx_in[7:0]),
.dt_be (dt_be),
.dt_be_vb (dt_be_vb),
.dt_be_cb (dt_be_cntxt),
.dt_acc_in (dt_acc_in[4:0]),
.dc_hld (dc_hld[1:0]),
.dc_do (dc_do[63:0]),
.dc_ain (dc_ain[(12-3):0]),
.dc_di (dc_di[63:0]),
.dc_wle (dc_wle),
.dc_be (dc_be[7:0]),
.dc_power_down (dc_power_down),
.dt_power_down (dt_power_down),
.dc_iiddtn (dc_iiddtn),
.dt_wle (dt_wle),
.dt_ain (dt_ain[12:4]),
.dc_scan_mode (scan_mode),
.dc_scan_in (dt_scan_out),
.dc_scan_out (dc_scan_out),
.dc_tg_strobe (tg_strobe),
.dc_clk (clkl)
);
mc_dtag dcache_tag (
.mc_dtag_scan_in (dt_scan_in),
.mc_dtag_scan_out (dt_scan_out),
.ain_w (dt_ain[12:4]),
.t_do (dt_do[18:0]),
.t_di (dt_di[18:0]),
.t_val_in (dt_val_in),
.t_val_out (dt_val_out),
.t_be (dt_be),
.t_be_cb (dt_be_cntxt),
.t_be_vb (dt_be_vb),
.power_down_w (dt_power_down),
.dc_iiddtn (dc_iiddtn),
.wle_w (dt_wle),
.t_at (dt_at[4:0]),
.t_acc_in (dt_acc_in[4:0]),
.t_acc_out (dt_acc_out[4:0]),
.t_cntx_in (dt_cntx_in[7:0]),
.t_cntx_out (dt_cntx_out[7:0]),
.t_index3 (dt_index3),
.t_index2 (dt_index2),
.t_index1 (dt_index1),
.t_flush (dt_flush),
.t_flush_user (dt_flush_user),
.t_flush_user_cntx (dt_flush_user_cntx),
.t_hit (dt_hit),
.t_scan_mode (scan_mode),
// .t_scan_in (dt_scan_in),
// .t_scan_out (dc_scan_out),
.t_tg_strobe (tg_strobe),
.t_clk (clkl)
);
endmodule
This page: |
Created: | Thu Aug 19 12:02:32 1999 |
| From: |
../../../sparc_v8/ssparc/caches/mc_d_tag_cache/rtl/mc_d_tag_cache.v
|