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/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
// @(#)mr_caches.v	1.36 9/15/93
// Instantiates the cache RAM modules.


module mr_caches(
			// Timing critical address bits 
	ic_adr_in,	// ic_adr_in[13:2] go directly to $'s 
	ic_power_down,
	dc_power_down,
        iiddtn,
	ic_wle,
	ic_be,
	it_din,
	dt_din,
	it_val_in,
	ic_do,
	ic_di,
	it_dout_f,
	it_val_f,
        tg_strobe,
        ic_scan_in,
        scan_mode,

	dt_dout_w,
	dt_val_w,
 
        dc_scan_out,
	dc_dtv_din,
	dc_adr_in,
	dc_wle,
	dc_be,
	it_cntx_in,
	it_cntx_out,
	dc_hld,
	ic_hld,
	dc_do,
	dc_di,
	dt_at,
	dt_acc_in,
	dt_acc_out,
	it_acc_in,
	it_acc_out,
	it_lvl_in,
	it_lvl_out,
	dt_cntx_in,
	dt_cntx_out,
	it_be,
	it_be_vb,
	dt_be,
	dt_be_vb,
	dt_hit_w,
	it_hit_f,
    	dt_index3,
    	dt_index2,
    	dt_index1,
    	dt_flush,
    	dt_flush_user,
    	dt_flush_user_cntx,
        it_index3,
        it_index2,
        it_index1,
        it_flush,
        it_flush_user,
        it_flush_user_cntx,

	logic_0,

        clkl_i,
        clkr_i,
        clkl_d,
        clkr_d 
        ) ;

	input logic_0 ;

    	input dt_index3 ; 
    	input dt_index2 ;  
    	input dt_index1 ;   
    	input dt_flush ; 
    	input dt_flush_user ;  
    	input dt_flush_user_cntx ;

    	input it_index3 ; 
    	input it_index2 ;  
    	input it_index1 ;   
    	input it_flush ; 
    	input it_flush_user ;  
    	input it_flush_user_cntx ;

	output dt_hit_w ;
	output it_hit_f ;
	input it_be ;
	input it_be_vb ;
	input dt_be ;
	input dt_be_vb ;
	input [7:0] it_cntx_in ;
	output [7:0] it_cntx_out ;
	input it_acc_in ;
	input [1:0] it_lvl_in ;
	input [1:0] dc_hld ;
	input [1:0] ic_hld ;
	output it_acc_out ;
	output [1:0] it_lvl_out ;
	output [63:0] dc_do ;
	input [63:0] dc_di ;
	input [4:0] dt_at ;
	input [4:0] dt_acc_in ;
	output [4:0] dt_acc_out ;
	input [7:0] dt_cntx_in ;
	output [7:0] dt_cntx_out ;
 
	input tg_strobe;
	input scan_mode ;

	input [`dc_msb:3] dc_adr_in ;
	input dc_wle ;
	input [7:0] dc_be ;

        output dc_scan_out;
        // output dcctl_scan_out;

	output [`dt_msb:0] dt_dout_w ;

	output dt_val_w ;

        wire ic_scan_out;

	input dc_dtv_din ;

 
        input ic_scan_in;
        input ic_power_down;
        input dc_power_down;
        input iiddtn;
        input clkl_i ;
        input clkr_i ;
        input clkl_d ;
        input clkr_d ;
        output [63:0] ic_do ;
	output [`it_msb:0] it_dout_f ;
	output it_val_f ;
	input [`ic_msb:`log2_datasize] ic_adr_in ;
	input ic_wle ;
	input [1:0] ic_be ;
	input [31:`log2_icachesize] it_din ;
	input [31:`log2_dcachesize] dt_din ;
	input it_val_in ;
	input [63:0] ic_di ;

wire DUMY4;  // To satisfy verilog
wire DUMY2;  // To satisfy verilog

// To satisfy verilog

wire [`dt_msb:0] dt_di = {dt_din[31:`log2_dcachesize]} ; 

// For asi tag reads ..
// wire [`dt_msb:0] dt_do = {dt_dout_w[`dt_msb:0]} ; 

// The LSB of the ITag is not used.
// A ZERO is written into the [0] bit of the Itag megacell
// (which is really a replica of the mc_dtag cell). 
// Then the LOWER bit of the output is always neglected 
// while reading the contents of the mc_itag megacell.

// Write '0' into lsb
wire [`dt_msb:0] it_di = {it_din[31:`log2_icachesize],logic_0} ; 
wire [`dt_msb:0] it_do ;
// Disregard lsb during read.
wire [`it_msb:0] it_dout_f = it_do[`dt_msb:1] ;

// Merged I-cache + I-Tag module
mc_i_tag_cache i_tag_cache(
            .ic_hld (ic_hld[1:0]),
	    .ic_do (ic_do[63:0]),
	    .ic_di (ic_di[63:0]),
	    .ic_power_down (ic_power_down),
            .ic_iiddtn (iiddtn),
	    .ic_ain (ic_adr_in[`ic_msb:3]),
	    .ic_wle (ic_wle),
	    .ic_be (ic_be[1:0]),
	    .scan_mode (scan_mode),
	    .ic_scan_in (ic_scan_in),
	    .it_scan_out (ic_scan_out),
            .it_do (it_do),  		// Lowest bit is '0' 
            .it_di (it_di),		// Lowest bit is '0'
            .it_acc_in ({logic_0,it_acc_in,logic_0,it_lvl_in[1:0]}),
            .it_acc_out ({DUMY4,it_acc_out,DUMY2,it_lvl_out[1:0]}),
            .it_cntx_in (it_cntx_in[7:0]),
            .it_cntx_out (it_cntx_out[7:0]),
            .it_be (it_be),  
            .it_be_cntxt (it_be),  
            .it_be_vb (it_be_vb),
            .it_val_in (it_val_in),
            .it_val_out (it_val_f),
            .it_index3 (it_index3),
            .it_index2 (it_index2),
            .it_index1 (it_index1),
            .it_flush (it_flush),
            .it_flush_user (it_flush_user),
            .it_flush_user_cntx (it_flush_user_cntx),
            .it_hit (it_hit_f),
            .it_at ({5{logic_0}}),
            .tg_strobe (tg_strobe),
	    .clkr (clkr_i),
	    .clkl (clkl_i)
        );

// Merged D-cache + D-Tag module
mc_d_tag_cache d_tag_cache(
	    .dc_hld (dc_hld[1:0]),
	    .dc_do (dc_do[63:0]),
	    .dc_ain (dc_adr_in[`dc_msb:3]),
	    .dc_di (dc_di[63:0]),
	    .dc_wle (dc_wle),
	    .dc_be (dc_be[7:0]),
	    .dc_power_down (dc_power_down),
            .dc_iiddtn (iiddtn),
	    .dt_scan_in (ic_scan_out),
	    .dc_scan_out (dc_scan_out),
	    .tg_strobe (tg_strobe),
	    .dt_do (dt_dout_w),
	    .dt_di (dt_di),
	    .dt_val_in (dc_dtv_din),
	    .dt_val_out (dt_val_w),
	    .dt_be (dt_be),
	    .dt_be_cntxt (dt_be),
	    .dt_be_vb (dt_be_vb),
	    .dt_at (dt_at[4:0]),
	    .dt_acc_in (dt_acc_in[4:0]),
	    .dt_acc_out (dt_acc_out[4:0]),
	    .dt_cntx_in (dt_cntx_in[7:0]),
	    .dt_cntx_out (dt_cntx_out[7:0]),
	    .dt_index3 (dt_index3),
            .dt_index2 (dt_index2), 
            .dt_index1 (dt_index1), 
            .dt_flush (dt_flush),  
            .dt_flush_user (dt_flush_user),  
            .dt_flush_user_cntx (dt_flush_user_cntx),  
	    .dt_hit (dt_hit_w),
	    .scan_mode (scan_mode),
	    .clkr (clkr_d),
	    .clkl (clkl_d)
       );

// Added spare cells 
 
        spares  mr_caches_spares ();
endmodule