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//  @(#)mullsblog.v	1.1  4/7/92
//

module StickyPairNC (StkIn, notCin, X, Y, StkOut, notCout);
   input  StkIn, notCin ;
   input [1:0] X, Y ;
   output StkOut, notCout ; 
   
   ME_XNOR2_B  g10 ( X[0], Y[0], notZ0 );
   ME_XNOR2_B  g11 ( X[1], Y[1], notZ1 );
   ME_OR2_B    g13 ( notZ0, notZ1, notProp );

   // generate logic
   //ME_NMUX2B g12 ( Z1, x[1], x[0], notglo ) ; 
   ME_NAND3    g20 ( X[0], Y[0], X[1], g1 );
   ME_NAND3    g21 ( X[0], Y[0], Y[1], g2 );
   ME_NAND2    g22 ( X[1], Y[1], g3 );
   ME_NAND3    g23 ( g1, g2, g3, generate );

   // local sticky 
   ME_NAND2    g14 ( X[0], Y[0], notgenlo);
   ME_XOR3_B   g26 ( notgenlo, X[1], Y[1], bit1);
   ME_NAND3    g24 ( notZ0, bit1, notCin, StkGen);
   ME_NMUX2B   g28 ( notProp, notCin, StkGen, notStk ) ;

   // bypasses
   ME_INV_A    g31 ( StkIn, notStkIn );
   ME_NAND2    g32 ( notStkIn, notStk, StkOut );
 
   ME_INVA     g27 ( notCin, Cin );
   ME_NMUX2B_B g34 ( notProp, Cin, generate, notCout );
 
endmodule



module StickyPairNCI (StkIn, notCin, X, Y, StkOut, Cout);
   input  StkIn, notCin ;
   input [1:0] X, Y ;
   output StkOut, Cout ; 
   
   ME_XNOR2_B g10 ( X[0], Y[0], notZ0 );
   ME_XNOR2_B g11 ( X[1], Y[1], notZ1 );
   ME_OR2_B   g13 ( notZ0, notZ1, notProp );

   // generate logic
   //ME_NMUX2B g12 ( Z1, x[1], x[0], notglo ) ; 
   ME_NAND3 g20 ( X[0], Y[0], X[1], g1 );
   ME_NAND3 g21 ( X[0], Y[0], Y[1], g2 );
   ME_NAND2 g22 ( X[1], Y[1], g3 );
   ME_NAND3 g23 ( g1, g2, g3, generate );

   // local sticky 
   ME_NAND2   g14 (X[0], Y[0], notgenlo);
   ME_XOR3_B  g26 ( notgenlo, X[1], Y[1], bit1);
   ME_NAND3_B g25 ( notZ0, bit1, notCin, StkGen);
   ME_NMUX2B  g28 ( notProp, notCin, StkGen, notStk ) ;

   // bypasses
   ME_INVA    g31 ( StkIn, notStkIn );
   ME_NAND2_B g32 ( notStkIn, notStk, StkOut );
 
   ME_INVA    g27 ( notCin, Cin );
   ME_MUX2B   g34 ( notProp, Cin, generate, Cout );
 
endmodule



module MulLSBlog (SIn, CIn, SInA, CInA, LSBCarryIn, StickyIn,
                  LSBCarryOut, StickyOut);

   input [1:0] SIn, CIn;
   input [5:0] SInA, CInA;
   input LSBCarryIn, StickyIn;
   output LSBCarryOut, StickyOut;

   // wire [2:0] Sticky;
   // wire [7:0] SS;
   // wire [7:1] CO;

   ME_INVA    g27 ( LSBCarryIn, notLSBCarryIn );
   StickyPairNC  m0 (StickyIn, notLSBCarryIn, CIn, SIn, SS0, notC0);
   StickyPairNC  m1 (SS0,  notC0, CInA[1:0], SInA[1:0], SS1, notC1);
   StickyPairNC  m2 (SS1,  notC1, CInA[3:2], SInA[3:2], SS2, notC2);
   StickyPairNCI m3 (SS2,  notC2, CInA[5:4], SInA[5:4], StickyOut, LSBCarryOut);

   // ME_ADD3 a0 (CIn[0], SIn[0], LSBCarryIn, SS[0], CO[1]);
   // ME_ADD3 a1 (CIn[1], SIn[1], CO[1], SS[1], CO[2]);
   // ME_OR3  o1 (SS[0],  SS[1], StickyIn, Sticky[0]);
  
   // ME_ADD3 a2 (CInA[0], SInA[0], CO[2], SS[2], CO[3]);
   // ME_ADD3 a3 (CInA[1], SInA[1], CO[3], SS[3], CO[4]);
   // ME_OR3  o2 (SS[2],   SS[3], Sticky[0], Sticky[1]);

   // ME_ADD3 a4 (CInA[2], SInA[2], CO[4], SS[4], CO[5]);
   // ME_ADD3 a5 (CInA[3], SInA[3], CO[5], SS[5], CO[6]);
   // ME_OR3  o3 (SS[4],   SS[5], Sticky[1], Sticky[2]);

   // ME_ADD3 a6 (CInA[4], SInA[4], CO[6], SS[6], CO[7]);
   // ME_ADD3 a7 (CInA[5], SInA[5], CO[7], SS[7], LSBCarryOut);
   // ME_OR3  o4 (SS[6],   SS[7], Sticky[2], StickyOut);

endmodule