//
// Copyright Notice and Proprietary Information
//
// Copyright (C) 1992 - 1995 Synopsys, Inc. All rights reserved. This Software
// and manual are owned by Synopsys, Inc., and may be used only as authorized
// in the license agreement controlling such use. No part of this publication
// may be reproduced, transmitted, or translated, in any form or by any means,
// electronic, mechanical, manual, optical, or otherwise, without prior written
// permission of Synopsys, Inc., or as expressly provided by the license agreement.
//
// Destination Control Statement
//
// All technical data contained in this publication is subject to the export
// control laws of the United States of America. Disclosure to nationals of other
// countries contrary to United States law is prohibited. It is the reader's
// responsibility to determine the applicable regulations and to comply with them.
//
// Disclaimer
//
// Synopsys, Inc., makes no warranty of any kind, express or implied, with regard
// to this material, including, but not limited to, the implied warranties of
// merchantability and fitness for a particular purpose.
//
// Synopsys, Inc., reserves the right to make changes without further notice to
// the products described herein. Synopsys, Inc. does not assume any liability
// arising out of the application or use of any product or circuit described
// herein. The Synopsys products described herein are not authorized for use as
// components in life-support devices.
//
`lmv_timescale
//--- VER_GEN Version 7.0 ---
module pcimaster_times
;
integer trs_pad_pclk
; initial trs_pad_pclk
= 0;
integer trh_pad_pclk
; initial trh_pad_pclk
= 0;
integer twd_pad
[31:0];
initial begin
twd_pad[31] = 0;
twd_pad[30] = 0;
twd_pad[29] = 0;
twd_pad[28] = 0;
twd_pad[27] = 0;
twd_pad[26] = 0;
twd_pad[25] = 0;
twd_pad[24] = 0;
twd_pad[23] = 0;
twd_pad[22] = 0;
twd_pad[21] = 0;
twd_pad[20] = 0;
twd_pad[19] = 0;
twd_pad[18] = 0;
twd_pad[17] = 0;
twd_pad[16] = 0;
twd_pad[15] = 0;
twd_pad[14] = 0;
twd_pad[13] = 0;
twd_pad[12] = 0;
twd_pad[11] = 0;
twd_pad[10] = 0;
twd_pad[9] = 0;
twd_pad[8] = 0;
twd_pad[7] = 0;
twd_pad[6] = 0;
twd_pad[5] = 0;
twd_pad[4] = 0;
twd_pad[3] = 0;
twd_pad[2] = 0;
twd_pad[1] = 0;
twd_pad[0] = 0;
end
reg [127:0] tpr_pclk_pad
;
initial begin
tpr_pclk_pad = 128'b0;
end
integer thrx_pclk_pad
; initial thrx_pclk_pad
= 0;
integer tld_pad
[31:0];
initial begin
tld_pad[31] = 0;
tld_pad[30] = 0;
tld_pad[29] = 0;
tld_pad[28] = 0;
tld_pad[27] = 0;
tld_pad[26] = 0;
tld_pad[25] = 0;
tld_pad[24] = 0;
tld_pad[23] = 0;
tld_pad[22] = 0;
tld_pad[21] = 0;
tld_pad[20] = 0;
tld_pad[19] = 0;
tld_pad[18] = 0;
tld_pad[17] = 0;
tld_pad[16] = 0;
tld_pad[15] = 0;
tld_pad[14] = 0;
tld_pad[13] = 0;
tld_pad[12] = 0;
tld_pad[11] = 0;
tld_pad[10] = 0;
tld_pad[9] = 0;
tld_pad[8] = 0;
tld_pad[7] = 0;
tld_pad[6] = 0;
tld_pad[5] = 0;
tld_pad[4] = 0;
tld_pad[3] = 0;
tld_pad[2] = 0;
tld_pad[1] = 0;
tld_pad[0] = 0;
end
integer trs_pcxbenn_pclk
; initial trs_pcxbenn_pclk
= 0;
integer trh_pcxbenn_pclk
; initial trh_pcxbenn_pclk
= 0;
integer twd_pcxbenn
[3:0];
initial begin
twd_pcxbenn[3] = 0;
twd_pcxbenn[2] = 0;
twd_pcxbenn[1] = 0;
twd_pcxbenn[0] = 0;
end
reg [127:0] tpr_pclk_pcxbenn
;
initial begin
tpr_pclk_pcxbenn = 128'b0;
end
integer thrx_pclk_pcxbenn
; initial thrx_pclk_pcxbenn
= 0;
integer tld_pcxbenn
[3:0];
initial begin
tld_pcxbenn[3] = 0;
tld_pcxbenn[2] = 0;
tld_pcxbenn[1] = 0;
tld_pcxbenn[0] = 0;
end
integer trs_ppar_pclk
; initial trs_ppar_pclk
= 0;
integer trh_ppar_pclk
; initial trh_ppar_pclk
= 0;
integer twd_ppar
; initial twd_ppar
= 0;
reg [127:0] tpr_pclk_ppar
;
initial begin
tpr_pclk_ppar = 128'b0;
end
integer thrx_pclk_ppar
; initial thrx_pclk_ppar
= 0;
integer tld_ppar
; initial tld_ppar
= 0;
integer trs_pframenn_pclk
; initial trs_pframenn_pclk
= 0;
integer trh_pframenn_pclk
; initial trh_pframenn_pclk
= 0;
integer twd_pframenn
; initial twd_pframenn
= 0;
reg [127:0] tpr_pclk_pframenn
;
initial begin
tpr_pclk_pframenn = 128'b0;
end
integer thrx_pclk_pframenn
; initial thrx_pclk_pframenn
= 0;
integer tld_pframenn
; initial tld_pframenn
= 0;
integer trs_ptrdynn_pclk
; initial trs_ptrdynn_pclk
= 0;
integer trh_ptrdynn_pclk
; initial trh_ptrdynn_pclk
= 0;
integer twd_ptrdynn
; initial twd_ptrdynn
= 0;
reg [127:0] tpr_pclk_ptrdynn
;
initial begin
tpr_pclk_ptrdynn = 128'b0;
end
integer thrx_pclk_ptrdynn
; initial thrx_pclk_ptrdynn
= 0;
integer tld_ptrdynn
; initial tld_ptrdynn
= 0;
integer trs_pirdynn_pclk
; initial trs_pirdynn_pclk
= 0;
integer trh_pirdynn_pclk
; initial trh_pirdynn_pclk
= 0;
integer twd_pirdynn
; initial twd_pirdynn
= 0;
reg [127:0] tpr_pclk_pirdynn
;
initial begin
tpr_pclk_pirdynn = 128'b0;
end
integer thrx_pclk_pirdynn
; initial thrx_pclk_pirdynn
= 0;
integer tld_pirdynn
; initial tld_pirdynn
= 0;
integer trs_pstopnn_pclk
; initial trs_pstopnn_pclk
= 0;
integer trh_pstopnn_pclk
; initial trh_pstopnn_pclk
= 0;
integer twd_pstopnn
; initial twd_pstopnn
= 0;
integer trs_pdevselnn_pclk
; initial trs_pdevselnn_pclk
= 0;
integer trh_pdevselnn_pclk
; initial trh_pdevselnn_pclk
= 0;
integer twd_pdevselnn
; initial twd_pdevselnn
= 0;
reg [127:0] tpr_pclk_pdevselnn
;
initial begin
tpr_pclk_pdevselnn = 128'b0;
end
integer thrx_pclk_pdevselnn
; initial thrx_pclk_pdevselnn
= 0;
integer tld_pdevselnn
; initial tld_pdevselnn
= 0;
integer trs_pidsel_pclk
; initial trs_pidsel_pclk
= 0;
integer trh_pidsel_pclk
; initial trh_pidsel_pclk
= 0;
integer twd_pidsel
; initial twd_pidsel
= 0;
integer trs_preqnn_pclk
; initial trs_preqnn_pclk
= 0;
integer trh_preqnn_pclk
; initial trh_preqnn_pclk
= 0;
integer twd_preqnn
; initial twd_preqnn
= 0;
reg [127:0] tpr_pclk_preqnn
;
initial begin
tpr_pclk_preqnn = 128'b0;
end
integer thrx_pclk_preqnn
; initial thrx_pclk_preqnn
= 0;
integer tld_preqnn
; initial tld_preqnn
= 0;
integer trs_pgntnn_pclk
; initial trs_pgntnn_pclk
= 0;
integer trh_pgntnn_pclk
; initial trh_pgntnn_pclk
= 0;
integer twd_pgntnn
; initial twd_pgntnn
= 0;
integer tcy_min_pclk
; initial tcy_min_pclk
= 0;
integer tcy_max_pclk
; initial tcy_max_pclk
= 0;
integer tpwh_min_pclk
; initial tpwh_min_pclk
= 0;
integer tpwh_max_pclk
; initial tpwh_max_pclk
= 0;
integer tpwl_min_pclk
; initial tpwl_min_pclk
= 0;
integer tpwl_max_pclk
; initial tpwl_max_pclk
= 0;
integer twd_pclk
; initial twd_pclk
= 0;
integer trs_pclkrunnn_pclk
; initial trs_pclkrunnn_pclk
= 0;
integer trh_pclkrunnn_pclk
; initial trh_pclkrunnn_pclk
= 0;
integer twd_pclkrunnn
; initial twd_pclkrunnn
= 0;
reg [127:0] tpr_pclk_pclkrunnn
;
initial begin
tpr_pclk_pclkrunnn = 128'b0;
end
integer tld_pclkrunnn
; initial tld_pclkrunnn
= 0;
integer tcy_min_prstnn
; initial tcy_min_prstnn
= 0;
integer tcy_max_prstnn
; initial tcy_max_prstnn
= 0;
integer tpwh_min_prstnn
; initial tpwh_min_prstnn
= 0;
integer tpwh_max_prstnn
; initial tpwh_max_prstnn
= 0;
integer tpwl_min_prstnn
; initial tpwl_min_prstnn
= 0;
integer tpwl_max_prstnn
; initial tpwl_max_prstnn
= 0;
integer twd_prstnn
; initial twd_prstnn
= 0;
integer trs_pd_pclk
; initial trs_pd_pclk
= 0;
integer trh_pd_pclk
; initial trh_pd_pclk
= 0;
integer twd_pd
[63:32];
initial begin
twd_pd[63] = 0;
twd_pd[62] = 0;
twd_pd[61] = 0;
twd_pd[60] = 0;
twd_pd[59] = 0;
twd_pd[58] = 0;
twd_pd[57] = 0;
twd_pd[56] = 0;
twd_pd[55] = 0;
twd_pd[54] = 0;
twd_pd[53] = 0;
twd_pd[52] = 0;
twd_pd[51] = 0;
twd_pd[50] = 0;
twd_pd[49] = 0;
twd_pd[48] = 0;
twd_pd[47] = 0;
twd_pd[46] = 0;
twd_pd[45] = 0;
twd_pd[44] = 0;
twd_pd[43] = 0;
twd_pd[42] = 0;
twd_pd[41] = 0;
twd_pd[40] = 0;
twd_pd[39] = 0;
twd_pd[38] = 0;
twd_pd[37] = 0;
twd_pd[36] = 0;
twd_pd[35] = 0;
twd_pd[34] = 0;
twd_pd[33] = 0;
twd_pd[32] = 0;
end
reg [127:0] tpr_pclk_pd
;
initial begin
tpr_pclk_pd = 128'b0;
end
integer thrx_pclk_pd
; initial thrx_pclk_pd
= 0;
integer tld_pd
[63:32];
initial begin
tld_pd[63] = 0;
tld_pd[62] = 0;
tld_pd[61] = 0;
tld_pd[60] = 0;
tld_pd[59] = 0;
tld_pd[58] = 0;
tld_pd[57] = 0;
tld_pd[56] = 0;
tld_pd[55] = 0;
tld_pd[54] = 0;
tld_pd[53] = 0;
tld_pd[52] = 0;
tld_pd[51] = 0;
tld_pd[50] = 0;
tld_pd[49] = 0;
tld_pd[48] = 0;
tld_pd[47] = 0;
tld_pd[46] = 0;
tld_pd[45] = 0;
tld_pd[44] = 0;
tld_pd[43] = 0;
tld_pd[42] = 0;
tld_pd[41] = 0;
tld_pd[40] = 0;
tld_pd[39] = 0;
tld_pd[38] = 0;
tld_pd[37] = 0;
tld_pd[36] = 0;
tld_pd[35] = 0;
tld_pd[34] = 0;
tld_pd[33] = 0;
tld_pd[32] = 0;
end
integer trs_pbenn_pclk
; initial trs_pbenn_pclk
= 0;
integer trh_pbenn_pclk
; initial trh_pbenn_pclk
= 0;
integer twd_pbenn
[7:4];
initial begin
twd_pbenn[7] = 0;
twd_pbenn[6] = 0;
twd_pbenn[5] = 0;
twd_pbenn[4] = 0;
end
reg [127:0] tpr_pclk_pbenn
;
initial begin
tpr_pclk_pbenn = 128'b0;
end
integer thrx_pclk_pbenn
; initial thrx_pclk_pbenn
= 0;
integer tld_pbenn
[7:4];
initial begin
tld_pbenn[7] = 0;
tld_pbenn[6] = 0;
tld_pbenn[5] = 0;
tld_pbenn[4] = 0;
end
integer trs_ppar64_pclk
; initial trs_ppar64_pclk
= 0;
integer trh_ppar64_pclk
; initial trh_ppar64_pclk
= 0;
integer twd_ppar64
; initial twd_ppar64
= 0;
reg [127:0] tpr_pclk_ppar64
;
initial begin
tpr_pclk_ppar64 = 128'b0;
end
integer thrx_pclk_ppar64
; initial thrx_pclk_ppar64
= 0;
integer tld_ppar64
; initial tld_ppar64
= 0;
integer trs_preq64nn_pclk
; initial trs_preq64nn_pclk
= 0;
integer trh_preq64nn_pclk
; initial trh_preq64nn_pclk
= 0;
integer twd_preq64nn
; initial twd_preq64nn
= 0;
reg [127:0] tpr_pclk_preq64nn
;
initial begin
tpr_pclk_preq64nn = 128'b0;
end
integer thrx_pclk_preq64nn
; initial thrx_pclk_preq64nn
= 0;
integer tld_preq64nn
; initial tld_preq64nn
= 0;
integer trs_pack64nn_pclk
; initial trs_pack64nn_pclk
= 0;
integer trh_pack64nn_pclk
; initial trh_pack64nn_pclk
= 0;
integer twd_pack64nn
; initial twd_pack64nn
= 0;
integer trs_plocknn_pclk
; initial trs_plocknn_pclk
= 0;
integer trh_plocknn_pclk
; initial trh_plocknn_pclk
= 0;
integer twd_plocknn
; initial twd_plocknn
= 0;
reg [127:0] tpr_pclk_plocknn
;
initial begin
tpr_pclk_plocknn = 128'b0;
end
integer thrx_pclk_plocknn
; initial thrx_pclk_plocknn
= 0;
integer tld_plocknn
; initial tld_plocknn
= 0;
integer trs_pperrnn_pclk
; initial trs_pperrnn_pclk
= 0;
integer trh_pperrnn_pclk
; initial trh_pperrnn_pclk
= 0;
integer twd_pperrnn
; initial twd_pperrnn
= 0;
reg [127:0] tpr_pclk_pperrnn
;
initial begin
tpr_pclk_pperrnn = 128'b0;
end
integer thrx_pclk_pperrnn
; initial thrx_pclk_pperrnn
= 0;
integer tld_pperrnn
; initial tld_pperrnn
= 0;
integer trs_pserrnn_pclk
; initial trs_pserrnn_pclk
= 0;
integer trh_pserrnn_pclk
; initial trh_pserrnn_pclk
= 0;
integer twd_pserrnn
; initial twd_pserrnn
= 0;
integer trs_psbonn_pclk
; initial trs_psbonn_pclk
= 0;
integer trh_psbonn_pclk
; initial trh_psbonn_pclk
= 0;
integer twd_psbonn
; initial twd_psbonn
= 0;
integer trs_psdone_pclk
; initial trs_psdone_pclk
= 0;
integer trh_psdone_pclk
; initial trh_psdone_pclk
= 0;
integer twd_psdone
; initial twd_psdone
= 0;
reg [127:0] tpd_prstnn_pad
;
initial begin
tpd_prstnn_pad = 128'b0;
end
reg [127:0] tpd_prstnn_pd
;
initial begin
tpd_prstnn_pd = 128'b0;
end
reg [127:0] tpd_prstnn_pcxbenn
;
initial begin
tpd_prstnn_pcxbenn = 128'b0;
end
reg [127:0] tpd_prstnn_pbenn
;
initial begin
tpd_prstnn_pbenn = 128'b0;
end
reg [127:0] tpd_prstnn_preqnn
;
initial begin
tpd_prstnn_preqnn = 128'b0;
end
reg [127:0] tpd_prstnn_preq64nn
;
initial begin
tpd_prstnn_preq64nn = 128'b0;
end
reg [127:0] tpd_prstnn_ppar
;
initial begin
tpd_prstnn_ppar = 128'b0;
end
reg [127:0] tpd_prstnn_ppar64
;
initial begin
tpd_prstnn_ppar64 = 128'b0;
end
reg [127:0] tpd_prstnn_pperrnn
;
initial begin
tpd_prstnn_pperrnn = 128'b0;
end
reg [127:0] tpd_prstnn_pirdynn
;
initial begin
tpd_prstnn_pirdynn = 128'b0;
end
reg [127:0] tpd_prstnn_pframenn
;
initial begin
tpd_prstnn_pframenn = 128'b0;
end
reg [127:0] tpd_prstnn_plocknn
;
initial begin
tpd_prstnn_plocknn = 128'b0;
end
reg [127:0] tpd_prstnn_pdevselnn
;
initial begin
tpd_prstnn_pdevselnn = 128'b0;
end
reg [127:0] tpd_prstnn_ptrdynn
;
initial begin
tpd_prstnn_ptrdynn = 128'b0;
end
endmodule // pcimaster_times
module pcimaster_flags
;
integer option
;
reg time_check
, x_check
, annotated
;
integer debug_level
, vlt
, tmp
, DF
;
endmodule // pcimaster_flags
module pcimaster_fm_cntrl
;
reg pad
;
reg pad_in
;
reg r_pad_pclk
;
reg pcxbenn
;
reg pcxbenn_in
;
reg r_pcxbenn_pclk
;
reg ppar
;
reg ppar_in
;
reg r_ppar_pclk
;
reg pframenn
;
reg pframenn_in
;
reg r_pframenn_pclk
;
reg ptrdynn
;
reg ptrdynn_in
;
reg r_ptrdynn_pclk
;
reg pirdynn
;
reg pirdynn_in
;
reg r_pirdynn_pclk
;
reg pstopnn
;
reg r_pstopnn_pclk
;
reg pdevselnn
;
reg pdevselnn_in
;
reg r_pdevselnn_pclk
;
reg pidsel
;
reg r_pidsel_pclk
;
reg preqnn
;
reg preqnn_in
;
reg r_preqnn_pclk
;
reg pgntnn
;
reg r_pgntnn_pclk
;
reg pclk
;
reg ck_pclk
;
reg pclkrunnn
;
reg pclkrunnn_in
;
reg r_pclkrunnn_pclk
;
reg prstnn
;
reg ck_prstnn
;
reg pd
;
reg pd_in
;
reg r_pd_pclk
;
reg pbenn
;
reg pbenn_in
;
reg r_pbenn_pclk
;
reg ppar64
;
reg ppar64_in
;
reg r_ppar64_pclk
;
reg preq64nn
;
reg preq64nn_in
;
reg r_preq64nn_pclk
;
reg pack64nn
;
reg r_pack64nn_pclk
;
reg plocknn
;
reg plocknn_in
;
reg r_plocknn_pclk
;
reg pperrnn
;
reg pperrnn_in
;
reg r_pperrnn_pclk
;
reg pserrnn
;
reg r_pserrnn_pclk
;
reg psbonn
;
reg r_psbonn_pclk
;
reg psdone
;
reg r_psdone_pclk
;
integer tm_event
;
endmodule // pcimaster_fm_cntrl
module pcimaster_fm_data_out
;
reg strobe
;
reg ready
;
endmodule
module pcimaster_fm_input
;
reg [31:0] pad
, pad_old
;
reg pad_31
,pad_30
,pad_29
,pad_28
,pad_27
,pad_26
,pad_25
,pad_24
,pad_23
,pad_22
,pad_21
,pad_20
,pad_19
,pad_18
,pad_17
,pad_16
,pad_15
,pad_14
,pad_13
,pad_12
,pad_11
,pad_10
,pad_9
,pad_8
,pad_7
,pad_6
,pad_5
,pad_4
,pad_3
,pad_2
,pad_1
,pad_0
;
reg pad_event
;
integer pad_event_time
; initial pad_event_time
= -500*`time_scale_multiplier;
integer pad_last_event
;
always @(pad_31 or pad_30 or pad_29 or pad_28 or pad_27 or pad_26 or pad_25 or pad_24 or pad_23 or pad_22 or pad_21 or pad_20 or pad_19 or pad_18 or pad_17 or pad_16 or pad_15 or pad_14 or pad_13 or pad_12 or pad_11 or pad_10 or pad_9 or pad_8 or pad_7 or pad_6 or pad_5 or pad_4 or pad_3 or pad_2 or pad_1 or pad_0) begin
pad[31] = pad_31;
pad[30] = pad_30;
pad[29] = pad_29;
pad[28] = pad_28;
pad[27] = pad_27;
pad[26] = pad_26;
pad[25] = pad_25;
pad[24] = pad_24;
pad[23] = pad_23;
pad[22] = pad_22;
pad[21] = pad_21;
pad[20] = pad_20;
pad[19] = pad_19;
pad[18] = pad_18;
pad[17] = pad_17;
pad[16] = pad_16;
pad[15] = pad_15;
pad[14] = pad_14;
pad[13] = pad_13;
pad[12] = pad_12;
pad[11] = pad_11;
pad[10] = pad_10;
pad[9] = pad_9;
pad[8] = pad_8;
pad[7] = pad_7;
pad[6] = pad_6;
pad[5] = pad_5;
pad[4] = pad_4;
pad[3] = pad_3;
pad[2] = pad_2;
pad[1] = pad_1;
pad[0] = pad_0;
pad_event = `true;
pad_event <= #(0) `false;
pad_event_time = $time;
end
reg [3:0] pcxbenn
, pcxbenn_old
;
reg pcxbenn_3
,pcxbenn_2
,pcxbenn_1
,pcxbenn_0
;
reg pcxbenn_event
;
integer pcxbenn_event_time
; initial pcxbenn_event_time
= -500*`time_scale_multiplier;
integer pcxbenn_last_event
;
always @(pcxbenn_3 or pcxbenn_2 or pcxbenn_1 or pcxbenn_0) begin
pcxbenn[3] = pcxbenn_3;
pcxbenn[2] = pcxbenn_2;
pcxbenn[1] = pcxbenn_1;
pcxbenn[0] = pcxbenn_0;
pcxbenn_event = `true;
pcxbenn_event <= #(0) `false;
pcxbenn_event_time = $time;
end
reg ppar
, ppar_old
;
reg ppar_event
;
integer ppar_event_time
; initial ppar_event_time
= -500*`time_scale_multiplier;
integer ppar_last_event
;
always @(ppar) begin
ppar_event = `true;
ppar_event <= #(0) `false;
ppar_event_time = $time;
end
reg pframenn
, pframenn_old
;
reg pframenn_event
;
integer pframenn_event_time
; initial pframenn_event_time
= -500*`time_scale_multiplier;
integer pframenn_last_event
;
always @(pframenn) begin
pframenn_event = `true;
pframenn_event <= #(0) `false;
pframenn_event_time = $time;
end
reg ptrdynn
, ptrdynn_old
;
reg ptrdynn_event
;
integer ptrdynn_event_time
; initial ptrdynn_event_time
= -500*`time_scale_multiplier;
integer ptrdynn_last_event
;
always @(ptrdynn) begin
ptrdynn_event = `true;
ptrdynn_event <= #(0) `false;
ptrdynn_event_time = $time;
end
reg pirdynn
, pirdynn_old
;
reg pirdynn_event
;
integer pirdynn_event_time
; initial pirdynn_event_time
= -500*`time_scale_multiplier;
integer pirdynn_last_event
;
always @(pirdynn) begin
pirdynn_event = `true;
pirdynn_event <= #(0) `false;
pirdynn_event_time = $time;
end
reg pstopnn
, pstopnn_old
;
reg pstopnn_event
;
integer pstopnn_event_time
; initial pstopnn_event_time
= -500*`time_scale_multiplier;
integer pstopnn_last_event
;
always @(pstopnn) begin
pstopnn_event = `true;
pstopnn_event <= #(0) `false;
pstopnn_event_time = $time;
end
reg pdevselnn
, pdevselnn_old
;
reg pdevselnn_event
;
integer pdevselnn_event_time
; initial pdevselnn_event_time
= -500*`time_scale_multiplier;
integer pdevselnn_last_event
;
always @(pdevselnn) begin
pdevselnn_event = `true;
pdevselnn_event <= #(0) `false;
pdevselnn_event_time = $time;
end
reg pidsel
, pidsel_old
;
reg pidsel_event
;
integer pidsel_event_time
; initial pidsel_event_time
= -500*`time_scale_multiplier;
integer pidsel_last_event
;
always @(pidsel) begin
pidsel_event = `true;
pidsel_event <= #(0) `false;
pidsel_event_time = $time;
end
reg preqnn
, preqnn_old
;
reg preqnn_event
;
integer preqnn_event_time
; initial preqnn_event_time
= -500*`time_scale_multiplier;
integer preqnn_last_event
;
always @(preqnn) begin
preqnn_event = `true;
preqnn_event <= #(0) `false;
preqnn_event_time = $time;
end
reg pgntnn
, pgntnn_old
;
reg pgntnn_event
;
integer pgntnn_event_time
; initial pgntnn_event_time
= -500*`time_scale_multiplier;
integer pgntnn_last_event
;
always @(pgntnn) begin
pgntnn_event = `true;
pgntnn_event <= #(0) `false;
pgntnn_event_time = $time;
end
reg pclk
, pclk_old
;
reg pclk_event
;
integer pclk_event_time
; initial pclk_event_time
= -500*`time_scale_multiplier;
integer pclk_last_event
;
always @(pclk) begin
pclk_event = `true;
pclk_event <= #(0) `false;
pclk_event_time = $time;
end
reg pclkrunnn
, pclkrunnn_old
;
reg pclkrunnn_event
;
integer pclkrunnn_event_time
; initial pclkrunnn_event_time
= -500*`time_scale_multiplier;
integer pclkrunnn_last_event
;
always @(pclkrunnn) begin
pclkrunnn_event = `true;
pclkrunnn_event <= #(0) `false;
pclkrunnn_event_time = $time;
end
reg prstnn
, prstnn_old
;
reg prstnn_event
;
integer prstnn_event_time
; initial prstnn_event_time
= -500*`time_scale_multiplier;
integer prstnn_last_event
;
always @(prstnn) begin
prstnn_event = `true;
prstnn_event <= #(0) `false;
prstnn_event_time = $time;
end
reg [63:32] pd
, pd_old
;
reg pd_63
,pd_62
,pd_61
,pd_60
,pd_59
,pd_58
,pd_57
,pd_56
,pd_55
,pd_54
,pd_53
,pd_52
,pd_51
,pd_50
,pd_49
,pd_48
,pd_47
,pd_46
,pd_45
,pd_44
,pd_43
,pd_42
,pd_41
,pd_40
,pd_39
,pd_38
,pd_37
,pd_36
,pd_35
,pd_34
,pd_33
,pd_32
;
reg pd_event
;
integer pd_event_time
; initial pd_event_time
= -500*`time_scale_multiplier;
integer pd_last_event
;
always @(pd_63 or pd_62 or pd_61 or pd_60 or pd_59 or pd_58 or pd_57 or pd_56 or pd_55 or pd_54 or pd_53 or pd_52 or pd_51 or pd_50 or pd_49 or pd_48 or pd_47 or pd_46 or pd_45 or pd_44 or pd_43 or pd_42 or pd_41 or pd_40 or pd_39 or pd_38 or pd_37 or pd_36 or pd_35 or pd_34 or pd_33 or pd_32) begin
pd[63] = pd_63;
pd[62] = pd_62;
pd[61] = pd_61;
pd[60] = pd_60;
pd[59] = pd_59;
pd[58] = pd_58;
pd[57] = pd_57;
pd[56] = pd_56;
pd[55] = pd_55;
pd[54] = pd_54;
pd[53] = pd_53;
pd[52] = pd_52;
pd[51] = pd_51;
pd[50] = pd_50;
pd[49] = pd_49;
pd[48] = pd_48;
pd[47] = pd_47;
pd[46] = pd_46;
pd[45] = pd_45;
pd[44] = pd_44;
pd[43] = pd_43;
pd[42] = pd_42;
pd[41] = pd_41;
pd[40] = pd_40;
pd[39] = pd_39;
pd[38] = pd_38;
pd[37] = pd_37;
pd[36] = pd_36;
pd[35] = pd_35;
pd[34] = pd_34;
pd[33] = pd_33;
pd[32] = pd_32;
pd_event = `true;
pd_event <= #(0) `false;
pd_event_time = $time;
end
reg [7:4] pbenn
, pbenn_old
;
reg pbenn_7
,pbenn_6
,pbenn_5
,pbenn_4
;
reg pbenn_event
;
integer pbenn_event_time
; initial pbenn_event_time
= -500*`time_scale_multiplier;
integer pbenn_last_event
;
always @(pbenn_7 or pbenn_6 or pbenn_5 or pbenn_4) begin
pbenn[7] = pbenn_7;
pbenn[6] = pbenn_6;
pbenn[5] = pbenn_5;
pbenn[4] = pbenn_4;
pbenn_event = `true;
pbenn_event <= #(0) `false;
pbenn_event_time = $time;
end
reg ppar64
, ppar64_old
;
reg ppar64_event
;
integer ppar64_event_time
; initial ppar64_event_time
= -500*`time_scale_multiplier;
integer ppar64_last_event
;
always @(ppar64) begin
ppar64_event = `true;
ppar64_event <= #(0) `false;
ppar64_event_time = $time;
end
reg preq64nn
, preq64nn_old
;
reg preq64nn_event
;
integer preq64nn_event_time
; initial preq64nn_event_time
= -500*`time_scale_multiplier;
integer preq64nn_last_event
;
always @(preq64nn) begin
preq64nn_event = `true;
preq64nn_event <= #(0) `false;
preq64nn_event_time = $time;
end
reg pack64nn
, pack64nn_old
;
reg pack64nn_event
;
integer pack64nn_event_time
; initial pack64nn_event_time
= -500*`time_scale_multiplier;
integer pack64nn_last_event
;
always @(pack64nn) begin
pack64nn_event = `true;
pack64nn_event <= #(0) `false;
pack64nn_event_time = $time;
end
reg plocknn
, plocknn_old
;
reg plocknn_event
;
integer plocknn_event_time
; initial plocknn_event_time
= -500*`time_scale_multiplier;
integer plocknn_last_event
;
always @(plocknn) begin
plocknn_event = `true;
plocknn_event <= #(0) `false;
plocknn_event_time = $time;
end
reg pperrnn
, pperrnn_old
;
reg pperrnn_event
;
integer pperrnn_event_time
; initial pperrnn_event_time
= -500*`time_scale_multiplier;
integer pperrnn_last_event
;
always @(pperrnn) begin
pperrnn_event = `true;
pperrnn_event <= #(0) `false;
pperrnn_event_time = $time;
end
reg pserrnn
, pserrnn_old
;
reg pserrnn_event
;
integer pserrnn_event_time
; initial pserrnn_event_time
= -500*`time_scale_multiplier;
integer pserrnn_last_event
;
always @(pserrnn) begin
pserrnn_event = `true;
pserrnn_event <= #(0) `false;
pserrnn_event_time = $time;
end
reg psbonn
, psbonn_old
;
reg psbonn_event
;
integer psbonn_event_time
; initial psbonn_event_time
= -500*`time_scale_multiplier;
integer psbonn_last_event
;
always @(psbonn) begin
psbonn_event = `true;
psbonn_event <= #(0) `false;
psbonn_event_time = $time;
end
reg psdone
, psdone_old
;
reg psdone_event
;
integer psdone_event_time
; initial psdone_event_time
= -500*`time_scale_multiplier;
integer psdone_last_event
;
always @(psdone) begin
psdone_event = `true;
psdone_event <= #(0) `false;
psdone_event_time = $time;
end
integer fm_event
;
endmodule // pcimaster_fm_input
//--**--**--**--**--**--**--**--**-- TEMP: MODELER DECLARATION BEGIN
//--**--**--**--**--**--**--**--**-- TEMP: MODELER DECLARATION END
module pcimaster_timing
;
//--**--**--**--**--**--**--**--**-- USER CODE BEGIN
parameter fm_data_in1 = 1;
parameter fm_data_in2 = 5190;
parameter incode1 = 1;
parameter incode2 = 32;
parameter instrobe = 33;
parameter inrtype1 = 34;
parameter inrtype2 = 65;
parameter inbyten1 = 66;
parameter inbyten2 = 129;
parameter inexpected_data1 = 130;
parameter inexpected_data2 = 193;
parameter indelay1 = 194;
parameter indelay2 = 225;
parameter inaddr1 = 226;
parameter inaddr2 = 257;
parameter intc1 = 258;
parameter intc2 = 289;
parameter inlock1 = 290;
parameter inlock2 = 290;
parameter inwtype1 = 291;
parameter inwtype2 = 322;
parameter indata1 = 323;
parameter indata2 = 386;
parameter inctype1 = 387;
parameter inctype2 = 418;
parameter invalue_vector1 = 419;
parameter invalue_vector2 = 482;
parameter invalue_int1 = 483;
parameter invalue_int2 = 514;
parameter invalue_bol = 515;
parameter inmode1 = 516;
parameter inmode2 = 547;
parameter invalue_time1 = 548;
parameter invalue_time2 = 579;
parameter inwait_num1 = 580;
parameter inwait_num2 = 611;
parameter inwakeup_num1 = 612;
parameter inwakeup_num2 = 643;
parameter incycles1 = 644;
parameter incycles2 = 675;
parameter insleep_num1 = 676;
parameter insleep_num2 = 707;
parameter intvalue1 = 708;
parameter intvalue2 = 739;
parameter inmessage1 = 740;
parameter inmessage2 = 1763;
parameter inmlevel1 = 1764;
parameter inmlevel2 = 1795;
parameter infunction_name1 = 1796;
parameter infunction_name2 = 2819;
parameter instype1 = 2820;
parameter instype2 = 2851;
parameter inobject_name1 = 2852;
parameter inobject_name2 = 2883;
parameter inobject_value1 = 2884;
parameter inobject_value2 = 2947;
parameter indelay_val1 = 2948;
parameter indelay_val2 = 2979;
parameter intarget_id1 = 2980;
parameter intarget_id2 = 3011;
parameter inmsg1 = 3012;
parameter inmsg2 = 4035;
parameter inbuffer_f = 4036;
parameter innotify_f = 4037;
parameter inreturn_data_f = 4038;
parameter innode_name1 = 4039;
parameter innode_name2 = 5062;
parameter innode_value1 = 5063;
parameter innode_value2 = 5126;
parameter innode_mask1 = 5127;
parameter innode_mask2 = 5190;
//type object_name_types is :
parameter pad_bus = 0;
parameter pad_0 = 1;
parameter pad_1 = 2;
parameter pad_2 = 3;
parameter pad_3 = 4;
parameter pad_4 = 5;
parameter pad_5 = 6;
parameter pad_6 = 7;
parameter pad_7 = 8;
parameter pad_8 = 9;
parameter pad_9 = 10;
parameter pad_10 = 11;
parameter pad_11 = 12;
parameter pad_12 = 13;
parameter pad_13 = 14;
parameter pad_14 = 15;
parameter pad_15 = 16;
parameter pad_16 = 17;
parameter pad_17 = 18;
parameter pad_18 = 19;
parameter pad_19 = 20;
parameter pad_20 = 21;
parameter pad_21 = 22;
parameter pad_22 = 23;
parameter pad_23 = 24;
parameter pad_24 = 25;
parameter pad_25 = 26;
parameter pad_26 = 27;
parameter pad_27 = 28;
parameter pad_28 = 29;
parameter pad_29 = 30;
parameter pad_30 = 31;
parameter pad_31 = 32;
parameter pcxbenn_bus = 33;
parameter pcxbenn_0 = 34;
parameter pcxbenn_1 = 35;
parameter pcxbenn_2 = 36;
parameter pcxbenn_3 = 37;
parameter ppar_pin = 38;
parameter pframenn_pin = 39;
parameter ptrdynn_pin = 40;
parameter pirdynn_pin = 41;
parameter pstopnn_pin = 42;
parameter pdevselnn_pin = 43;
parameter pidsel_pin = 44;
parameter preqnn_pin = 45;
parameter pgntnn_pin = 46;
parameter pclk_pin = 47;
parameter pclkrunnn_pin = 48;
parameter prstnn_pin = 49;
parameter pd_bus = 50;
parameter pd_32 = 51;
parameter pd_33 = 52;
parameter pd_34 = 53;
parameter pd_35 = 54;
parameter pd_36 = 55;
parameter pd_37 = 56;
parameter pd_38 = 57;
parameter pd_39 = 58;
parameter pd_40 = 59;
parameter pd_41 = 60;
parameter pd_42 = 61;
parameter pd_43 = 62;
parameter pd_44 = 63;
parameter pd_45 = 64;
parameter pd_46 = 65;
parameter pd_47 = 66;
parameter pd_48 = 67;
parameter pd_49 = 68;
parameter pd_50 = 69;
parameter pd_51 = 70;
parameter pd_52 = 71;
parameter pd_53 = 72;
parameter pd_54 = 73;
parameter pd_55 = 74;
parameter pd_56 = 75;
parameter pd_57 = 76;
parameter pd_58 = 77;
parameter pd_59 = 78;
parameter pd_60 = 79;
parameter pd_61 = 80;
parameter pd_62 = 81;
parameter pd_63 = 82;
parameter pbenn_bus = 83;
parameter pbenn_4 = 84;
parameter pbenn_5 = 85;
This page: |
Created: | Thu Aug 19 12:03:02 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcimaster_timing.v
|