endtask // lock_enable;

task bus_state;
begin 
  case ( bstate )
    sidle , sturn_ar : begin  
        no_trdy = `true;
        no_irdy = `true;
        if ( b(INP.pframenn) ) begin
           bstate_nx = sidle;
        end else if ( ! b(INP.pframenn) && ! b(hit) ) begin
           bstate_nx = sb_busy;
        end else if ( ! b(INP.pframenn) && b(hit) &&
              (! b(term) || (b(term) && b(ready))) &&
              (lstate===free || (lstate===locked && b(INP.plocknn))) ) begin
           bstate_nx = ss_data;
        end else if ( ! b(INP.pframenn) && b(hit) && ((b(term) && ! b(ready)) ||
              (lstate===locked && ! b(INP.plocknn))) ) begin
           bstate_nx = sbackoff;
        end else begin
           if (!(`false)) begin
             $display("WARNING at %0t from %m",$time);
             $write("     \"pci_slave:  no path out of idle or turn_ar state; reseting bus to idle state");
             $display("\"");
           end
           bstate_nx = sidle;

        end // if
   end
    sb_busy : begin
        if ( (! b(INP.pframenn) || ! b(INP.pirdynn)) && ! b(hit) ) begin
           bstate_nx = sb_busy;
        end else if ( (! b(INP.pframenn) || ! b(INP.pirdynn)) && b(hit) &&
              (! b(term) || (b(term) && b(ready))) &&
              (lstate===free || (lstate===locked && b(lock_int))) ) begin
           bstate_nx = ss_data;
        end else if ( (! b(INP.pframenn) || ! b(INP.pirdynn)) && b(hit) &&
              ((b(term) && ! b(ready)) ||
              (lstate===locked && ! b(lock_int))) ) begin
           bstate_nx = sbackoff;
        end else if ( b(INP.pframenn) && (hit_resolved || b(INP.pirdynn)) ) begin 
           bstate_nx = sidle;
        end else begin
           if (!(`false)) begin
             $display("WARNING at %0t from %m",$time);
             $write("     \"pci_slave:  no path out of b_busy state; reseting bus to idle state");
             $display("\"");
           end
           bstate_nx = sidle;

        end // if
   end
    ss_data : begin
        if ( ! b(INP.pirdynn) ) begin
           no_irdy = `false;
        end // if
        if ( ! b(INP.ptrdynn) ) begin
           no_trdy = `false;
        end // if
        if ( (! b(INP.pframenn) && ! b(INP.pstopnn) && ! b(INP.ptrdynn)) ||
           (! b(INP.pframenn) && b(INP.pstopnn)) ||
           (b(INP.pframenn) && b(INP.ptrdynn) && b(INP.pstopnn)) ) begin
           if ( ((req_space === spc_space) || (no_trdy && ! no_irdy)) && b(INP.pirdynn) && b(INP.pframenn) ) begin
              bstate_nx = sturn_ar;
           end else begin
              bstate_nx = ss_data;
           end // if
        end else if ( ! b(INP.pframenn) && ! b(INP.pstopnn) && b(INP.ptrdynn) ) begin
           bstate_nx = sbackoff;
        end else if ( b(INP.pframenn) && (! b(INP.ptrdynn) || ! b(INP.pstopnn)) ) begin
           bstate_nx = sturn_ar;
        end else begin
           if (!(`false)) begin
             $display("WARNING at %0t from %m",$time);
             $write("     \"pci_slave:  no path out of s_data state; reseting bus to idle state");
             $display("\"");
           end
           bstate_nx = sidle;

        end // if
   end
    sbackoff : begin
        if ( ! b(INP.pframenn) ) begin
           bstate_nx = sbackoff;
        end else if ( b(INP.pframenn) ) begin
           bstate_nx = sturn_ar;
        end else begin
           if (!(`false)) begin
             $display("WARNING at %0t from %m",$time);
             $write("     \"pci_slave:  no path out of backoff state; reseting bus to idle state");
             $display("\"");
           end
           bstate_nx = sidle;

        end // if
    end
    endcase  
   bstate = bstate_nx;

end
endtask // bus_state;

function [31:0] get_ddelay; 
input [31:0] index;
integer tom;
begin
  if ( index <= `max_delay_index ) begin
     tom = ddelay[index];
  end else begin
     tom = ddelay[`max_delay_index];
  end // if
  get_ddelay = tom;
end
endfunction // get_ddelay;

task request;
begin
  if (!((msg_level<debug_3))) begin
    $display("NOTE at %0t from %m",$time);
    $write("     \"PROCEDURE REQUEST");
    $display("\"");
  end

  if (( request_cnt >= request_limit ) || is_first) begin
    if ( (is_first) ) begin
      is_first = `false;
    end else begin
      get_nxt_cmd;      
    end // if
    request_cnt = 0;
    if ( curr_cmd[incode1:incode2] === `request_cmd ) begin
      request_limit  = curr_cmd[inrequest_limit1:inrequest_limit2];
      addr_decode_cycles = curr_cmd[indecode1:indecode2];
      ddelay[1] = curr_cmd[indelay1:indelay2];
      request_limit_last  = curr_cmd[inrequest_limit1:inrequest_limit2];
      addr_decode_cycles_last = curr_cmd[indecode1:indecode2];
      ddelay1_last = curr_cmd[indelay1:indelay2];
    end else if(curr_cmd[incode1:incode2] === `idle_cmd) begin
//      request_limit = request_limit_last;
//      addr_decode_cycles = addr_decode_cycles_last;
//      ddelay[1] = ddelay1_last;
    end // if
 end // if
 if (( curr_cmd[incode1:incode2] === `request_cmd ) || 
     ( curr_cmd[incode1:incode2] === `idle_cmd)) begin
   transfer_cnt = 1;
   request_cnt = request_cnt + 1;
   if ( get_ddelay(1) !== 0 ) begin
     delay_cnt = get_ddelay(1);
     cstate = ddelay_first;
     ready = 1'b0;
     term  = 1'b0;
   end else begin
     if ( tabort_limit === 0 ) begin
       ready = 1'b0;
       term  = 1'b0;
       cstate = abort_first;
     end else if ( fm_transfer_limit === 0 ) begin
       term = 1'b1;
       ready = 1'b0;
       cstate = terminate_first;
     end else if ( (transfer_cnt === fm_transfer_limit) && (term_style === with_data) ) begin
       term = 1'b1;
       ready = 1'b1;
       cstate = ready_first;
     end else begin
       term = 1'b0;
       ready = 1'b1;
       cstate = ready_first;
     end // if
   end // if
 end // if
 snoop_enable = `true;
 sstate = snp_standby;
end
endtask // request;

task configure;
input [fm_data_in1:fm_data_in2] cmd;
reg [61 : 0]  addr  ; 
reg [31 : 0]  data     ; 
begin
  addr = 62'h0;
  data = 32'hxxxxxxxx;
  case ( cmd[inctype1:inctype2] )
     transfer_limit : begin
      fm_transfer_limit = cmd[invalue1:invalue2];
    end
     abort_limit : begin
      tabort_limit   = cmd[invalue1:invalue2]; 
    end
     termination_style : begin
      ts = cmd[invalue1:invalue2];
      if ( cmd[invalue1:invalue2] === 1 ) begin
        term_style = with_data;
      end else begin 
        term_style = without_data;
      end // if
    end
     pci_error : begin
      npe = cmd[invalue1:invalue2];
    end
     decode : begin
      addr_decode_cycles = cmd[invalue1:invalue2];    
      addr_decode_cycles_last = cmd[invalue1:invalue2];    
    end
     delays : begin
      if ( cmd[indelay_index1:indelay_index2] === -1 ) begin
	for (i = 1; i <= `max_delay_index; i = i + 1) begin 
	  ddelay[i] = cmd[indelay1:indelay2];
	end // loop
      end else begin
        ddelay[cmd[indelay_index1:indelay_index2]] = cmd[indelay1:indelay2];
        ddelay1_last = ddelay[1];
      end // if
    end
     dev_id : begin
      $lmv_memory_read("cfg_head",addr,data);
      data[31 : 16] = cmd[invalue_vector1:invalue_vector2];
      $lmv_memory_write("cfg_head",addr,data);
    end
     ven_id : begin
      $lmv_memory_read("cfg_head",addr,data);
      data[15 : 0] = cmd[invalue_vector1:invalue_vector2];
      $lmv_memory_write("cfg_head",addr,data);
    end
     cls_code : begin
      addr = addr + 2;
      $lmv_memory_read("cfg_head",addr,data);
      data[31 : 8] = cmd[invalue_vector1:invalue_vector2];
      $lmv_memory_write("cfg_head",addr,data);
    end
     rev_id : begin
      addr = addr + 2;
      $lmv_memory_read("cfg_head",addr,data);
      data[7 : 0] = cmd[invalue_vector1:invalue_vector2];
      $lmv_memory_write("cfg_head",addr,data);
    end
     h_type : begin
      addr = addr + 3;
      $lmv_memory_read("cfg_head",addr,data);
      data[23 : 16] = cmd[invalue_vector1:invalue_vector2];
      $lmv_memory_write("cfg_head",addr,data);
    end
     c_line_size : begin
      addr = addr + 3;
      $lmv_memory_read("cfg_head",addr,data);
      data[7 : 0] = cmd[invalue_vector1:invalue_vector2];
      $lmv_memory_write("cfg_head",addr,data);
      line_size = (cmd[invalue_vector1:invalue_vector2]);
    end
     mem_l_0 : begin
      mem_lower_0 = (cmd[invalue_vector1:invalue_vector2]);
    end
     mem_u_0 : begin
      mem_upper_0 = (cmd[invalue_vector1:invalue_vector2]);
    end
     mem_l_1 : begin
      mem_lower_1 = (cmd[invalue_vector1:invalue_vector2]);
    end
     mem_u_1 : begin
      mem_upper_1 = (cmd[invalue_vector1:invalue_vector2]);
    end
     mem_l_2 : begin
      mem_lower_2 = (cmd[invalue_vector1:invalue_vector2]);
    end
     mem_u_2 : begin
      mem_upper_2 = (cmd[invalue_vector1:invalue_vector2]);
    end
     io_l_0 : begin
      io_lower_0  = (cmd[invalue_vector1:invalue_vector2]);
    end
     io_u_0 : begin
      io_upper_0  = (cmd[invalue_vector1:invalue_vector2]);
    end
     io_l_1 : begin
      io_lower_1  = (cmd[invalue_vector1:invalue_vector2]);
    end
     io_u_1 : begin
      io_upper_1  = (cmd[invalue_vector1:invalue_vector2]);
    end
     io_l_2 : begin
      io_lower_2  = (cmd[invalue_vector1:invalue_vector2]);
    end
     io_u_2 : begin
      io_upper_2  = (cmd[invalue_vector1:invalue_vector2]);
    end
     addr_64 : begin
      addr64_local = cmd[invalue_boolean];
    end
     data_64 : begin
      data64_local = cmd[invalue_boolean];
    end
     int_ack : begin
      iack_local = cmd[invalue_boolean];
    end
     int_ack_vector : begin
      iack_vector_local = (cmd[invalue_vector1:invalue_vector2]);
    end
     type1_access : begin
      type1_access_l = cmd[invalue_boolean];
    end
     default begin 
      /* null */
  end
  endcase
	
 if (!((msg_level<debug_2))) begin
   $display("NOTE at %0t from %m",$time);
   $display(" TRANSFER LIMIT     = %0d",fm_transfer_limit);
   $display(" ABORT LIMIT        = %0d",tabort_limit);
   $display(" TERM STYLE         = %0d",ts);
   $display(" REQUEST LIMIT      = %0d",request_limit);
   $display(" DECODE DELAY       = %0d",addr_decode_cycles);
   $display(" PCI ERROR          = %0d",npe);
   $display(" TRDY DELAYS[1:3]   = %0d,%0d,%0d",ddelay[1],ddelay[2],ddelay[3]);
 end

end
endtask // configure;


task ready_maker;
begin
  if ( (bstate === sidle) ) begin
     snoop_enable = `true;
     sstate = snp_standby;
  end // if 

  if ( cacheable ) begin                // x's are ignored, state stays same. 
     if ( snoop_enable ) begin 
        if ( INP.psdone === 1'b0 ) begin 
           if ( INP.psbonn === 1'b1 || INP.psbonn === 1'b0 ) begin
              sstate = snp_standby;
              cstate = ddelay_first; 
              ready = 1'b0;
              if ( delay_cnt === 0 ) begin
                 delay_cnt = 1; 
              end // if
           end // if
        end else if ( INP.psdone === 1'b1 ) begin 
           if ( INP.psbonn === 1'b0 ) begin
              sstate = snp_hit_mod;
              term_style = without_data;
              snoop_enable = `false;
              delay_cnt = 1;
           end else if ( INP.psbonn === 1'b1 ) begin
              sstate = snp_clean; 
              snoop_enable = `false;
           end // if
        end // if
        if ( INP.psdone === 1'bx ) begin
           sstate = snp_clean;
           if (!(`false)) begin
             $display("WARNING at %0t from %m",$time);
             $write("     \"Snoop state cannot be determined : PSDONE Unknown");
             $display("\"");
           end

        end // if
        if ( INP.psbonn === 1'bx ) begin
           sstate = snp_clean;
           if (!(`false)) begin
             $display("WARNING at %0t from %m",$time);
             $write("     \"Snoop state cannot be determined : PSBONN Unknown");
             $display("\"");
           end

        end // if    
     end // if
  end else begin
     sstate = snp_clean;
  end // if

// Only report error on first transfer 

 if ( (req_space === io_space && bstate === ss_data && transfer_cnt === 1) ) begin
    if (  (INP.pcxbenn[3 : 0] !== 4'hf) && ((ad10 === 0 && cxbe_int[0] !== 1'b0) ||
       (ad10 === 1 && (cxbe_int[1] !== 1'b0 || cxbe_int[0] !== 1'b1)) ||
       (ad10 === 2 && (cxbe_int[2] !== 1'b0 || cxbe_int[1] !== 1'b1 || cxbe_int[0] !== 1'b1)) ||
       (ad10 === 3 && (cxbe_int[3] !== 1'b0 || cxbe_int[2] !== 1'b1 || cxbe_int[1] !== 1'b1 || cxbe_int[0] !== 1'b1)) )) begin
       if (!((tabort_limit===0))) begin
         $display("NOTE at %0t from %m",$time);
         $write("     \"Illegal CBE & AD1,AD0 during IO cycle");
         $display("\"");
       end
         if (cstate !== abort && cstate !== abort_first) begin
           target_abort = `true;
         end
     end // if
 end // if


  if ( (hit_nx === 1'b1 && b(INP.pframenn) && b(INP.pirdynn) && bstate === sb_busy) ) begin
     request;
  end // if

  case ( cstate )

  //  the ready_first state is when we are waiting for a transfer to begin.
  //  we know that we want to transfer data at the first available moment
  //  so the 'ready' line is already asserted.  the only time we leave this
  //  state is when the bus machine is in the s_data or backoff state.
  //  we return here (or to ddelay_first) with a new set of params when the
  //  bus machine goes to any other state besides s_data or backoff.

   ready_first : begin                      // ready to do a data transfer
       if ( bstate === ss_data ) begin
          if ( INP.pirdynn === 1'b0 && INP.ptrdynn === 1'b0 ) begin              // a data transfer happened.
             transfer_cnt = transfer_cnt + 1;
             if ( direction === write ) begin
                write_slave_data;
             end // if
             update_address;
             if ( direction === read ) begin
                read_slave_data;
             end // if
             if ( get_ddelay(transfer_cnt) !== 0 ) begin
                delay_cnt = get_ddelay(transfer_cnt);
                ready = 1'b0;
                cstate = d_delay;
             end else if ( transfer_cnt > tabort_limit || target_abort ) begin
                ready = 1'b0;
                term = 1'b0;
                t_abort = 1'b1;
                cstate = abort;
                target_abort = `false;
             end else if ( (transfer_cnt > fm_transfer_limit) || (disc) || 
                   (cacheable && command == 15 &&
                   ((! transfer64 && (transfer_cnt > line_size)) ||
                   (transfer64 && (transfer_cnt > line_size/2)))) ) begin
                term = 1'b1;
                ready = 1'b0;
                cstate = terminate;
                disc = `false;
             end else if ( (transfer_cnt === fm_transfer_limit) && (term_style === with_data) ) begin
                term = 1'b1;
                ready = 1'b1;
                cstate = sready;
             end else begin
                term = 1'b0;
                ready = 1'b1;
                cstate = sready;
             end // if
          end else begin
             cstate = sready;
          end // if
       end else if ( bstate === sbackoff || sstate === snp_busy || sstate === snp_hit_mod ) begin // 3/14/94 MF
          term = 1'b0;
          cstate = terminate;
       end // if
  end
   sready : begin
       if ( bstate === ss_data ) begin
          if ( INP.pirdynn === 1'b0 ) begin              // a data transfer happened.
             transfer_cnt = transfer_cnt + 1;
             if ( direction === write ) begin
                write_slave_data;
             end // if
             update_address;
             if ( direction === read ) begin
                read_slave_data;
             end // if
             if ( get_ddelay(transfer_cnt) !== 0 ) begin
                delay_cnt = get_ddelay(transfer_cnt);
                ready = 1'b0;
                cstate = d_delay;
             end else if ( transfer_cnt > tabort_limit || target_abort ) begin
                ready = 1'b0;
                term = 1'b0;
                t_abort = 1'b1;
                cstate = abort;
                target_abort = `false;
             end else if ( (transfer_cnt > fm_transfer_limit) || (disc) ||
                   (cacheable && command == 15 && 
                   ((! transfer64 && (transfer_cnt > line_size)) ||
                   (transfer64 && (transfer_cnt > line_size/2)))) ) begin
                term = 1'b1;
                ready = 1'b0;
                cstate = terminate;
                disc = `false;
             end else if ( (transfer_cnt === fm_transfer_limit) && (term_style === with_data) ) begin
                term = 1'b1;
                 ready = 1'b1;
                 cstate = sready;
             end else begin
                term = 1'b0;
                ready = 1'b1;
                cstate = sready;
             end // if
          end else begin
             cstate = sready;
          end // if
       end else if ( bstate === sbackoff ) begin
          term = 1'b0;
          ready = 1'b0;
          cstate = terminate;
       end else begin
          term = 1'b0;
          request;
       end // if
  end
   ddelay_first : begin
       if ( bstate === ss_data ) begin
          if ( (sstate !== snp_standby) ) begin
             if ( (delay_cnt > 0) ) begin
                delay_cnt = delay_cnt - 1;
             end else begin
                delay_cnt = 0;
             end // if
          end // if
          if ( delay_cnt === 0 ) begin
             if ( transfer_cnt > tabort_limit || target_abort ) begin
                ready = 1'b0;
                term = 1'b0;
                t_abort = 1'b1;
                cstate = abort;
                target_abort = `false;
             end else if ( transfer_cnt > fm_transfer_limit || disc || 
                   sstate === snp_busy || sstate === snp_hit_mod ) begin
                term = 1'b1;
                ready = 1'b0;
                cstate = terminate;
                disc = `false;
             end else if ( (transfer_cnt === fm_transfer_limit) && (term_style === with_data) ) begin
                term = 1'b1;
                ready = 1'b1;
                cstate = sready;
             end else begin
                term = 1'b0;
                ready = 1'b1;
                cstate = sready;
             end // if
          end else if ( sstate === snp_clean ) begin
             cstate = d_delay;
          end // if
       end else if ( bstate === sbackoff || sstate === snp_busy || sstate === snp_hit_mod ) begin
          term = 1'b0;
          ready = 1'b0;
          cstate = terminate;
       end // if
  end
   d_delay : begin
       if ( bstate === ss_data ) begin
          delay_cnt = delay_cnt - 1;  
          if ( delay_cnt === 0 ) begin
             if ( transfer_cnt > tabort_limit || target_abort ) begin
                ready = 1'b0;
                term = 1'b0;
                t_abort = 1'b1;
                cstate = abort;
                target_abort = `false;
             end else if ( (transfer_cnt > fm_transfer_limit) || (disc) ||
                   (cacheable && command == 15 && 
                   ((! transfer64 && (transfer_cnt > line_size)) ||
                   (transfer64 && (transfer_cnt > line_size/2)))) ) begin
                term = 1'b1;
                ready = 1'b0;
                cstate = terminate;
                disc = `false;
             end else if ( (transfer_cnt === fm_transfer_limit) && (term_style === with_data) ) begin
                term = 1'b1;
                ready = 1'b1;
                cstate = sready;
             end else begin
                term = 1'b0;
                ready = 1'b1;
                cstate = sready;
             end // if
          end else begin
             cstate = d_delay;
          end // if
       end else begin
          term = 1'b0;
          request;
       end // if
  end
   terminate : begin
       if ( (bstate === ss_data) || (bstate === sbackoff) ) begin
           cstate = terminate;
           term = 1'b1;
        end else begin
           request;
        end // if
   end
    terminate_first : begin
        if ( (bstate === ss_data) || (bstate === sbackoff) ) begin
            cstate = terminate;
            term = 1'b1;
         end else begin
            cstate = terminate_first;
         end // if
    end
     abort_first : begin
         if ( (bstate === ss_data) ) begin
             cstate = abort;
             t_abort = 1'b1;
          end else begin
             cstate = abort_first;
          end // if
     end
      abort : begin
          if ( (bstate === ss_data) || (bstate === sbackoff) ) begin
             t_abort = 1'b1;
          end else begin
             t_abort = 1'b0;
             request;
          end // if
     end
     endcase

end
endtask // ready_maker;

task latcher;
reg [3 : 0]  bit4  ;   
reg [61:0]   ctmp   ;
reg [61:0]   tmp1   ;
reg [61:0]   tmp2   ;
integer i; 
begin
  bit4 = 4'h0;
  ctmp = 62'h0;
  tmp1 = 62'h0;
  tmp2 = 62'h0;
  idsel_int             = INP.pidsel;
  lock_int              = INP.plocknn;

  if ( INP.pcxbenn[0] === 1'b0 ) begin 
     direction = read;
  end else begin 
     direction = write;
  end // if
  bit4 = INP.pcxbenn; 

  cacheable = `false;
  command = (bit4);
  case ( bit4 )
    (4'b0010) , (4'b0011) : begin
        req_space = io_space;
   end
    (4'b1010) , (4'b1011) : begin
        req_space = cfg_space; 
   end
    (4'b0110) , (4'b0111) , (4'b1100) ,  (4'b1110) , (4'b1111) : begin
        req_space = mem_space;
        if ( line_size !== 0 ) begin
           cacheable = `true;
        end // if
        if ( INP.preq64nn === 1'b0 && data64_local ) begin
           transfer64 = `true;
        end // if
   end
    (4'b0000) : begin
        if ( iack_local ) begin
           req_space = iack_space;
        end else begin
           req_space = no_space;
        end // if
   end
    (4'b0001) : begin
        if ( (special_enable) ) begin
           req_space = spc_space;
        end else begin
           req_space = no_space;
        end // if
   end
    (4'b1101) : begin
        req_space = no_space;
   end
    default begin 
        req_space = no_space;
        command = -1;
   end
   endcase

  addr_good = `true;
  begin: loop1
  for (i = 0; i <= 31; i = i + 1) begin 
   if ( INP.pad[i] === 1'bx ) begin
      addr_good = `false;
      disable loop1;
   end // if
   if ( relatch ) begin
      if ( ad_int[i] === 1'bx ) begin
         addr_good = `false;
         disable loop1;
      end // if
   end // if
  end // loop
  end // loop1

  relatch = `false;

  if ( addr64_local ) begin 
     case ( bit4 )
       (4'b1101) : begin
           address[29 : 0]  = INP.pad[31 : 2];
           address[31 : 30] = 2'b00;
           address_valid = `false;
           ad10 = (INP.pad[1 : 0]);
           dual = `true;
           dturn = `true;
           relatch = `true;
      end
       (4'b0010) , (4'b0011) , (4'b1010) , (4'b1011) , (4'b0110) ,
           (4'b0111) , (4'b1100) , (4'b1110) , (4'b1111) : begin
           if ( address_valid ) begin
              address[29 : 0]  = (INP.pad[31 : 2]);
              address[61 : 30] = 32'h0;
              dturn = `false;
              ad10 = (INP.pad[1 : 0]);
              dual = `false; 
           end else begin
              address[61 : 30]  = (INP.pad);
              address_valid = `true; 
           end // if
      end
       default begin 
           /* null */
      end
      endcase
  end else begin  // not addr64
     address[29 : 0] = INP.pad[31 : 2];
     address[61 : 30] = 32'h0; 
     address_valid = `true;
     ad10 = (INP.pad[1 : 0]);
  end // if // addr64
  io_address = {address[61 : 0],INP.pad[1 : 0]};

  if ( transfer64 ) begin
     if ( address[0] !== 1'b0 ) begin
        address[0] = 1'b0;
        if (!(`false)) begin
          $display("WARNING at %0t from %m",$time);
          $write("     \"AD2 must be 0 for 64-bit transfer : Assuming AD2 = 0");
          $display("\"");
        end

     end // if
  end // if

// changed pad to INP.pad from here to end of task

  maddress[61 : 0] = address;
  laddress = (INP.pad[31 : 2]);
  saddress = maddress;
  transfer_count = 0;
  if ( cacheable ) begin
     ctmp        = line_size;     
     tmp1        = saddress / ctmp;
     cache_start = tmp1[30 : 0] * ctmp[30 : 0];
     cache_end   = cache_start + ctmp;
  end // if
  
  if ( relatch || ! dual ) begin // MF 9/23/94
     if ( INP.pad[1] === 1'b0 && INP.pad[0] === 1'b0 ) begin
        b_order = inc;
     end else if ( INP.pad[1] === 1'b1 && INP.pad[0] === 1'b0 ) begin
        if ( supports_wrap ) begin
           b_order = wrap;
        end else begin
           b_order = rsvd;
        end // if
     end else begin
        b_order = rsvd;
     end // if
  end // if

  if ( direction === read ) begin
     read_slave_data;
  end // if

end
endtask // latcher;


task hit_maker;
begin
  if ( hit_nx === 1'b1 ) begin
     if ( (hit_delayer_cycles > 0) ) begin
        hit_delayer_cycles = hit_delayer_cycles - 1;
     end // if
     if ( (hit_delayer_cycles === 0) ) begin
         hit = hit_nx; 
         hit_resolved = `true;
         hit_nx = 1'b0;
         pe = npe;
     end // if
  end // if

  ad_int[31 : 0]   = INP.pad;
  ad_int[63 : 32]  = INP.pd;
  cxbe_int[3 : 0]  = INP.pcxbenn;
  cxbe_int[7 : 4]  = INP.pbenn;

  if ( INP.pframenn === 1'b0 && (last_frame !== 1'b0 || relatch) ) begin
     transfer64 = `false;
     hit = 1'b0;
     hit_nx = 1'b0;
     hit_resolved = `false;
     latcher;

     if ( address_valid && ! relatch ) begin
        if ( addr_good ) begin
           case ( req_space )
             mem_space : begin   // the access is to memory space
                 if ( mem_enable && (((address >= mem_lower_0[63 : 2]) && (address <= mem_upper_0[63 : 2])) ||
                    ((address >= mem_lower_1[63 : 2]) && (address <= mem_upper_1[63 : 2])) ||
                    ((address >= mem_lower_2[63 : 2]) && (address <= mem_upper_2[63 : 2]))) ) begin
                    hit = 1'b0;
                    if ( addr_decode_cycles === 0 ) begin
                       hit_resolved = `true;
                       hit = 1'b1; 
                       pe = npe;
                    end else begin
                       hit_nx = 1'b1;
                       hit_delayer_cycles = addr_decode_cycles;
                    end // if
                 end else begin
                    hit_resolved = `true;
                    hit = 1'b0;
                 end // if
            end
             io_space : begin
                 // the access is to io space
                 if ( io_enable && (((io_address >= io_lower_0[63 : 0]) && (io_address <= io_upper_0[63 : 0])) ||
                    ((io_address >= io_lower_1[63 : 0]) && (io_address <= io_upper_1[63 : 0])) ||
                    ((io_address >= io_lower_2[63 : 0]) && (io_address <= io_upper_2[63 : 0]))) ) begin
                    hit = 1'b0;
                    if ( addr_decode_cycles === 0 ) begin
                       hit_resolved = `true;
                       hit = 1'b1;
                       pe = npe;
                    end else begin
                       hit_nx = 1'b1;
                       hit_delayer_cycles = addr_decode_cycles;
                    end // if
                 end else begin
                     hit = 1'b0;
                     hit_resolved = `true;
                 end // if
            end
             cfg_space : begin
                 if (( INP.pidsel === 1'b1 ) && ((INP.pad[1 : 0] === 2'b00) 
                    || ((INP.pad[1 : 0] === 2'b01) &&
                    type1_access_l))) begin
                    hit = 1'b0;
                    if ( addr_decode_cycles === 0 ) begin
                       hit_resolved = `true;
                       hit = 1'b1;
                       pe = npe;
                     end else begin
                        hit_nx = 1'b1;
                        hit_delayer_cycles = addr_decode_cycles;
                     end // if
                  end else begin
                     hit = 1'b0;
                     hit_resolved = `true;
                  end // if
             end
              iack_space : begin
                  if ( iack_local ) begin
                     hit = 1'b0;
                     if ( addr_decode_cycles === 0 ) begin             
                        hit_resolved = `true;
                        hit = 1'b1;
                        pe = npe;
                     end else begin
                        hit_nx = 1'b1;
                        hit_delayer_cycles = addr_decode_cycles;
                     end // if
                  end else begin
                     hit = 1'b0;
                     hit_resolved = `true;
                  end // if 

             end
              spc_space : begin
                  hit = 1'b1;
                  hit_resolved = `true;
                  pe = npe;
             end
              no_space : begin
                  hit = 1'b0;
                  hit_resolved = `false;
             end
             endcase 
         end // if // address good

      end // if // address valid

     turn_around_delay = 1'b0;

   end // if // frame

   if ( last_frame === 1'b0 && direction === read ) begin
      if ( dturn ) begin
         dturn = `false;
      end else begin
         turn_around_delay = 1'b1;
      end // if
   end // if

// Check for Fast Back-to-Back  MF 8/30/94

   if ( addr_decode_cycles === 0 ) begin // 
      if ( (INP.pframenn === 1'b0 && last_frame === 1'b1 && INP.pirdynn === 1'b1 && last_irdy === 1'b0 && last_trdy === 1'b0) ) begin // Fast Back-to-Back
         if ( ! hit_last && hit === 1'b1 ) begin // Not back to back to us
            if ( supports_fbb_chg ) begin
               hit_nx = 1'b1;
               hit_delayer_cycles = 1;
               if (!(`false)) begin
                 $display("WARNING at %0t from %m",$time);
                 $write("     \"Illegal Decode value during Fast Back-to-Back transaction: Assumming 1");
                 $display("\"");
               end

            end else begin
               if (!(`false)) begin
                 $display("WARNING at %0t from %m",$time);
                 $write("     \"Illegal Decode value during Fast Back-to-Back transaction: Decode should be set to greater than 0");
                 $display("\"");
               end

            end // if
         end // if
      end // if
   end // if

   if ( hit_resolved ) begin
      if ( hit === 1'b1 ) begin
         hit_last = `true;
      end else begin
         hit_last = `false;
      end // if
   end // if

   last_frame  = INP.pframenn;
   last_irdy   = INP.pirdynn;
   last_trdy   = INP.ptrdynn;

end
endtask // hit_maker;

task parity_maker;
 integer pcnt ; 
 integer pcnt64 ; 
begin

  pcnt = 0;
  pcnt64 = 0;
  if ( (bstate === ss_data && direction === read && // t_abort = '0' and 
      ! (last_dly === 1'b0 && turn_around_delay === 1'b1)) ) begin
      for (i = 32; i >= 0; i = i - 1) begin 
       if ( INP.pad[i] === 1'b1 ) begin 
          pcnt = pcnt + 1;
       end // if
     end // loop
     for (i = 3; i >= 0; i = i - 1) begin 
       if ( INP.pcxbenn[i] === 1'b1 ) begin 
          pcnt = pcnt + 1;
       end // if
     end // loop 
     if ( pe === 1 ) begin
        pcnt = pcnt + 1;
     end // if
     if ( lmcver.rem(pcnt,2) === 1 ) begin 
         if ( last_par === 1'bz ) begin                                   // PAR Floating
            ppar_out(1'bx,model_times.tpr_pclk_ppar,0 *`time_scale_multiplier);         // TON
         end else if ( last_par !== 1'b1 ) begin
            ppar_out(1'bx,model_times.tpr_pclk_ppar,-2 *`time_scale_multiplier);        // TH
         end // if
         ppar_out(1'b1,model_times.tpr_pclk_ppar,0 *`time_scale_multiplier);            // TVAL
         last_par = 1'b1;
      end else begin 
         if ( last_par === 1'bz ) begin                                   // PAR Floating
            ppar_out(1'bx,model_times.tpr_pclk_ppar,0 *`time_scale_multiplier);         // TON
         end else if ( last_par !== 1'b0 ) begin                               // PAR Changing
            ppar_out(1'bx,model_times.tpr_pclk_ppar,-2 *`time_scale_multiplier);        // TH
         end // if
         ppar_out(1'b0,model_times.tpr_pclk_ppar,0 *`time_scale_multiplier);            // TVAL
         last_par = 1'b0;
      end // if
   
      if ( (transfer64) ) begin
         for (i = 63; i >= 32; i = i - 1) begin 
           if ( INP.pd[i] === 1'b1 ) begin 
              pcnt64 = pcnt64 + 1;
           end // if
          end // loop
          for (i = 7; i >= 4; i = i - 1) begin 
            if ( INP.pbenn[i] === 1'b1 ) begin 
               pcnt64 = pcnt64 + 1;
            end // if
          end // loop
          if ( pe === 1 ) begin
             pcnt64 = pcnt64 + 1;
          end // if
          if ( lmcver.rem(pcnt64,2) === 1 ) begin