parameter sb_busy = 1;
parameter ss_data = 2;
parameter sturn_ar = 3;
parameter sbackoff = 4;
// type lock_state
parameter free = 0;
parameter locked = 1;
// type burst_order
parameter inc = 0;
parameter wrap = 2;
parameter rsvd = 3;
integer cstate
/*: cmd_states */ ; initial cstate = sready;
integer cstate_nx /*: cmd_states */ ; initial cstate_nx = sready;
integer astate /*: abort_state_type */ ; initial astate = waiting;
integer sstate /*: snoop_states */ ; initial sstate = snp_clean;
integer req_space /*: req_space_type */ ; initial req_space = no_space;
integer direction /*: dir_type */ ; initial direction = read;
integer term_style /*: termination_style */ ; initial term_style = without_data;
integer cmd_dlyd1 /*: dir_type */ ; initial cmd_dlyd1 = read;
integer cmd_dlyd2 /*: dir_type */ ; initial cmd_dlyd2 = read;
integer b_order /*: burst_order */ ; initial b_order = inc;
integer bstate /*: slave_states */ ; initial bstate = sidle;
integer bstate_nx /*: slave_states */ ; initial bstate_nx = sidle;
integer lstate /*: lock_state */ ; initial lstate = free;
integer ddelay[`max_delay_index:0] /*: delay_cnt_type */ ;
reg [63:0] mem_lower_0 ; initial mem_lower_0 = 64'h0;
reg [63:0] mem_upper_0 ; initial mem_upper_0 = 64'h0;
reg [63:0] mem_lower_1 ; initial mem_lower_1 = 64'h0;
reg [63:0] mem_upper_1 ; initial mem_upper_1 = 64'h0;
reg [63:0] mem_lower_2 ; initial mem_lower_2 = 64'h0;
reg [63:0] mem_upper_2 ; initial mem_upper_2 = 64'h0;
reg [63:0] io_lower_0 ; initial io_lower_0 = 64'h0;
reg [63:0] io_upper_0 ; initial io_upper_0 = 64'h0;
reg [63:0] io_lower_1 ; initial io_lower_1 = 64'h0;
reg [63:0] io_upper_1 ; initial io_upper_1 = 64'h0;
reg [63:0] io_lower_2 ; initial io_lower_2 = 64'h0;
reg [63:0] io_upper_2 ; initial io_upper_2 = 64'h0;
reg [61:0] address ; initial address = 62'h0;
reg [63:0] io_address ; initial io_address = 64'h0;
reg [61:0] saddress ; initial saddress = 62'h0;
reg [61:0] maddress ; initial maddress = 62'h0;
reg [61:0] cache_start ; initial cache_start = 62'h0;
reg [61:0] cache_end ; initial cache_end = 62'h0;
reg [63 : 0] data ; initial data = 64'h0;
reg [63 : 0] data_int ; initial data_int = 64'h0;
reg [63 : 0] ad_int ; initial ad_int = 64'h0;
reg [7 : 0] cxbe_int ; initial cxbe_int = 8'h0;
reg [31 : 0] pad_last ; initial pad_last = 32'hxxxxxxxx;
reg [63 : 32] pd_last ; initial pd_last = 32'hxxxxxxxx;
reg [15 : 0] preload_cmd ; initial preload_cmd = 16'h0;
reg [15 : 0] preload_status ; initial preload_status = 16'h0;
reg trdy_next ; initial trdy_next = 1'b1;
reg trdy_last ; initial trdy_last = 1'bz;
reg stop_next ; initial stop_next = 1'b1;
reg stop_last ; initial stop_last = 1'bz;
reg devsel_next ; initial devsel_next = 1'b1;
reg devsel_last ; initial devsel_last = 1'bz;
reg lock_int ; initial lock_int = 1'b0;
reg idsel_int ; initial idsel_int = 1'b0;
reg strobe ; initial strobe = 1'b0;
reg last_frame ; initial last_frame = 1'b1;
reg last_irdy ; initial last_irdy = 1'b1;
reg last_trdy ; initial last_trdy = 1'b1;
reg last_perr ; initial last_perr = 1'bz;
reg last_serr ; initial last_serr = 1'bz;
reg last_par ; initial last_par = 1'bz;
reg last_par64 ; initial last_par64 = 1'bz;
reg hit ; initial hit = 1'b0;
reg hit_nx ; initial hit_nx = 1'b0;
reg trdy_oe_dlyd1 ; initial trdy_oe_dlyd1 = 1'b0;
reg ready ; initial ready = 1'b0;
reg term ; initial term = 1'b0;
reg t_abort ; initial t_abort = 1'b0;
reg trdy_oe ; initial trdy_oe = 1'b1;
reg r_derr ; initial r_derr = 1'b0;
reg r_aerr ; initial r_aerr = 1'b0;
reg perr_oe ; initial perr_oe = 1'b0;
reg turn_around_delay ; initial turn_around_delay = 1'b0;
reg last_dly ; initial last_dly = 1'b0;
reg initialize ; initial initialize = `true;
reg hit_resolved ; initial hit_resolved = `false;
reg addr_good ; initial addr_good = `true;
reg address_valid ; initial address_valid = `true;
reg snoop_enable ; initial snoop_enable = `true;
reg cacheable ; initial cacheable = `false;
reg dual ; initial dual = `false;
reg dturn ; initial dturn = `false;
reg relatch ; initial relatch = `false;
reg transfer64 ; initial transfer64 = `false;
reg io_enable ; initial io_enable = `true;
reg mem_enable ; initial mem_enable = `true;
reg parity_enable ; initial parity_enable = `false;
reg serr_enable ; initial serr_enable = `false;
reg special_enable ; initial special_enable = `false;
reg bad_parity ; initial bad_parity = `false;
reg no_trdy ; initial no_trdy = `true;
reg no_irdy ; initial no_irdy = `true;
reg hit_last ; initial hit_last = `false;
reg check_dparity ; initial check_dparity = `false;
reg enable_check ; initial enable_check = `false;
reg supports_wrap ; initial supports_wrap = `true;
reg supports_rsvd_disc ; initial supports_rsvd_disc = `true;
reg supports_fbb_chg ; initial supports_fbb_chg = `true;
reg disc ; initial disc = `false;
reg target_abort ; initial target_abort = `false;
reg first_reset ; initial first_reset = `false;
reg [1 : 256*8] mem_fname [0:9]; // memory file names
reg [1 : 256*8] io_fname [0:9];
reg [1 : 256*8] cfg_fname [0:9];
integer request_limit ; initial request_limit = 1;
integer request_cnt ; initial request_cnt = 0;
integer fm_transfer_limit ; initial fm_transfer_limit = 16;
integer transfer_cnt ; initial transfer_cnt = 1;
integer transfer_count ; initial transfer_count = 0;
integer tabort_limit ; initial tabort_limit = 16;
integer delay_cnt ; initial delay_cnt = 0;
integer cdelay ; initial cdelay = 0;
integer sdelay ; initial sdelay = 0;
integer ulba ; initial ulba = 0;
integer usba ; initial usba = 0;
integer addr_decode_cycles ; initial addr_decode_cycles = 0;
integer hit_delayer_cycles ; initial hit_delayer_cycles = 0;
integer pe ; initial pe = 0;
integer npe ; initial npe = 0;
integer laddress ; initial laddress = 0;
integer ad10 ; initial ad10 = 0;
integer command ; initial command = -1;
reg is_first ; initial is_first = `true;
integer last_bstate /*: slave_states*/ ; initial last_bstate = sidle;
reg [63 : 0] last_ad ; initial last_ad = 64'hffffffffffffffff;
reg [ 7 : 0] last_cbe ; initial last_cbe = 8'hff;
integer tc ; initial tc = 0;
integer ts ; initial ts = 0;
reg iack_local ; initial iack_local = `false;
reg [31 : 0] iack_vector_local ; initial iack_vector_local = 32'hFFFFFFFF;
reg addr64_local ; initial addr64_local = `false;
reg data64_local ; initial data64_local = `false;
reg type1_access_l ; initial type1_access_l = `true;
integer request_limit_last ; initial request_limit_last = 1;
integer addr_decode_cycles_last ; initial addr_decode_cycles_last = 0;
integer ddelay1_last; initial ddelay1_last = 0;
// define some functions here that convert signals into
// boolean values. this makes it easier to code the state
// machines so that they appear exactly the same as in the
// text. for a given signal x, the function that returns its
// boolean value is x_b.
function b;
input s;
reg result;
begin
result = 0;
case (s)
1'b1 : result = 1;
default result = 0;
endcase
b = result;
end
endfunction
`ifdef no_pli
// No hex file
`else
// read intel hex file into memory
task read_hex_file;
input [1:64] list;
input [1:800] data_file;
reg elar;
reg [0 : 1023] binary_data;
reg [63 : 0] usba, addr;
reg [31 : 0] eaddress, address, tmp_addr;
reg [31 : 0] data, tdata;
reg [71 : 0] temp_data;
reg [127 : 0] an_temp;
integer linen, ulba, fh, offset;
integer record_type, count;
integer check_sum, temp, status;
integer endfile;
integer temp1, temp2, notimes, no_units, byte_offset, info_width, final;
integer i,j,k;
integer remain, max_index;
begin
temp1 = 0; temp2 = 0; notimes = 0; no_units = 0; byte_offset = 0;
info_width = 0; final = 0;
record_type = 0; addr = 0; count = 0; check_sum = 0;
temp = 0; status = 0; linen = 0;
ulba = 0; usba = 0;
elar = `true;
address = 32'b0; eaddress = 32'b0;
$lmv_openr(data_file,fh);
if (fh == 0) begin
if ((!(msg_level < `warnings))) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cannot open HEX file %0s. No data is preloaded!\"",data_file);
end
end
$lmv_endfile(fh,endfile);
if (!endfile) begin
while (!endfile && record_type != 1) begin
linen = linen + 1;
$lmv_read_hex(fh,record_type,status,count,offset,check_sum,binary_data);
case (record_type)
0 : begin // data record (8,16 or 32-bit formats)
an_temp = ulba * 65536;
if (elar) begin
addr = an_temp[63: 0] + offset; // Extended Linear address
end else begin
an_temp = usba* 16;
addr = usba[63 : 0] + offset; // Extended Segment address
end // if
temp1 = 0;
temp2 = 31;
no_units = 4;
notimes = count/no_units;
if ((addr % no_units) != 0 ) begin
byte_offset = addr % no_units;
notimes = notimes + 1;
end //if;
addr = addr/no_units;
info_width = 32;
for (i=0; i <= notimes-1 ; i= i+ 1) begin
if ( i != 0 ) begin
max_index = 8;
end else if (i === 0 && byte_offset === 0 ) begin
max_index = 8;
end else if (i === 0 && byte_offset != 0 ) begin
max_index = 8 + 8*byte_offset;
`ifdef paged
if (list == "mem_head")
$lmv_mempage_read("mem_head",addr[61:9],addr[8:0],temp_data[31:0]);
else if (list == "io_head")
$lmv_mempage_read("io_head",addr[61:9],addr[8:0],temp_data[31:0]);
else if (list == "cfg_head")
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],temp_data[31:0]);
`else
if (list == "mem_head")
$lmv_memory_read("mem_head",addr[61 : 0],temp_data[31:0]);
else if (list == "io_head")
$lmv_memory_read("io_head",addr[61:0],temp_data[31:0]);
else if (list == "cfg_head")
$lmv_memory_read("cfg_head",addr[61:0],temp_data[31:0]);
`endif
end //if;
if ( byte_offset != 0 && i === 0) begin
final = info_width-1-8*byte_offset;
end else begin
final = info_width-1;
end //if;
for (k =0; k <= final; k = k + 1) begin
max_index = max_index - 1;
temp_data[max_index] = binary_data[temp1+k];
if(max_index===56) begin
max_index = 72;
end else if(max_index==48) begin
max_index = 64;
end else if(max_index==40) begin
max_index = 56;
end else if(max_index==32) begin
max_index = 48;
end else if(max_index==24) begin
max_index = 40;
end else if(max_index==16) begin
max_index = 32;
end else if(max_index==8) begin
max_index = 24;
end else if(max_index==0) begin
max_index = 16;
end //if;
end //loop;
`ifdef paged
if (list == "mem_head") begin
$lmv_mempage_write("mem_head",addr[61:9],addr[8:0],temp_data[31:0]);
end else if (list == "io_head")begin
$lmv_mempage_write("io_head",addr[61:9],addr[8:0],temp_data[31:0]);
end else if (list == "cfg_head")
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],temp_data[31:0]);
`else
if (list == "mem_head") begin
$lmv_memory_write("mem_head",addr[61:0],temp_data[31:0]);
end else if (list == "io_head") begin
$lmv_memory_write("io_head",addr[61:0],temp_data[31:0]);
end else if (list == "cfg_head") begin
$lmv_memory_write("cfg_head",addr[61:0],temp_data[31:0]);
end
`endif
addr = addr + 1;
if ( i === 0 ) begin
temp1 = temp1 + info_width - 8*byte_offset;
temp2 = temp2 + info_width - 8*byte_offset;
end else begin
temp1 = temp1 + info_width;
temp2 = temp2 + info_width;
end// if;
end //for ;
end
2 : begin // Extended Segment Address Record (16 or 32-bit formats)
elar = `false;
usba = offset;
end
4 : begin // Extended Linear Address Record (16 or 32-bit formats)
elar = `true;
ulba = offset;
end
endcase
if (status != 0) begin
if (status == 1) begin
$display("warning at time %0t ps from %m",$time);
$display(" \"hex file %s checksum error at line %0d - expected = %h\"",data_file,linen,check_sum);
end else begin
$display("warning at time %0t ps from %m",$time);
$display(" \"hex file %s illegal syntax at line %0d - line ignored\"",data_file,linen);
end
end
$lmv_endfile(fh,endfile);
end
end
$lmv_close(fh);
end
endtask // read_hex_file
task preload_mem;
input [1:100*8] data_file;
integer fh,endfile,dat_format;
integer d_width;
begin
fh = 0;
endfile = 0;
dat_format = 0;
d_width = 32;
$lmv_openr(data_file,fh);
$lmv_endfile(fh,endfile);
if (fh == 0) begin
// $display("WARNING at time %0t from %m",$time);
$display(" \"Cannot open data file %0s. No data is preloaded!\"",data_file);
end else begin
$lmv_initialize_mem("mem_head",data_file,d_width);
$lmv_close(fh);
if ( dat_format == 1 )
read_hex_file("mem_head",data_file);
end
end
endtask
task preload_io;
input [1:100*8] data_file;
integer fh,endfile,dat_format;
integer d_width;
begin
fh = 0;
endfile = 0;
dat_format = 0;
d_width = 32;
$lmv_openr(data_file,fh);
$lmv_endfile(fh,endfile);
if (fh == 0) begin
// $display("WARNING at time %0t from %m",$time);
$display(" \"Cannot open data file %0s. No data is preloaded!\"",data_file);
end else begin
$lmv_initialize_mem("io_head",data_file,d_width);
$lmv_close(fh);
if ( dat_format == 1 )
read_hex_file("io_head",data_file);
end
end
endtask
task preload_cfg;
input [1:100*8] data_file;
integer fh,endfile,dat_format;
integer d_width;
begin
fh = 0;
endfile = 0;
dat_format = 0;
d_width = 32;
$lmv_openr(data_file,fh);
$lmv_endfile(fh,endfile);
if (fh == 0) begin
// $display("WARNING at time %0t from %m",$time);
$display(" \"Cannot open data file %0s. No data is preloaded!\"",data_file);
end else begin
$lmv_initialize_mem("cfg_head",data_file,d_width);
$lmv_close(fh);
if ( dat_format == 1 )
read_hex_file("cfg_head", data_file);
end
end
endtask
`endif
task update_status;
reg [61:0] addr ;
reg [31 : 0] data ;
begin
addr = 62'h0;
if ( t_abort === 1'b1 || r_derr === 1'b1 || r_aerr === 1'b1 ) begin
addr[0] = 1'b1; //- configuration address 1
`ifdef no_pli
data = cfg_head[addr[max_addr_width-1:0]];
`else
`ifdef paged
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_read("cfg_head",addr,data);
`endif
`endif
if ( t_abort === 1'b1 ) begin
data[27] = 1'b1; // target abort bit
end // if
if ( r_derr === 1'b1 ) begin
data[31] = 1'b1; // parity error bit
end // if
if ( r_aerr === 1'b1 ) begin
data[30] = 1'b1; // serr bit
data[31] = 1'b1; // parity error bit
end // if
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data;
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_write("cfg_head",addr,data);
`endif
`endif
end // if
end
endtask // update_status;
task update_address;
reg [63:0] foo ;
reg [63:0] tfoo ;
reg [63:0] cfoo ;
begin
foo = 64'h0;
tfoo = 64'h0;
cfoo = 64'h0;
disc = `false;
transfer_count = transfer_count + 1;
if ( req_space === mem_space ) begin
case ( b_order )
inc : begin
address = address + 1;
if ( transfer64 ) begin
address = address + 1;
end // if
end
wrap : begin
address = address + 1;
if ( transfer64 ) begin
address = address + 1;
end // if
if ( address === cache_end ) begin
address = cache_start;
end // if
end
rsvd : begin
address = address + 1;
if ( transfer64 ) begin
address = address + 1;
end // if
if (supports_rsvd_disc)
begin
disc = `true; // Force slave to disconnect
$display("WARNING at %0t from %m",$time);
$write(" \"Reserved encoding on ad1:ad0 -- disconnecting ");
$display("\"");
end
else
begin
$display("WARNING at %0t from %m",$time);
$write(" \"Reserved encoding on ad1:ad0. using increment ");
$display("\"");
end
end
endcase
end else begin
address = address + 1;
end // if
// Check for address out of bounds
if ( mem_enable && req_space === mem_space ) begin
if ( ! (((address >= mem_lower_0[63 : 2]) && (address <= mem_upper_0[63 : 2])) ||
((address >= mem_lower_1[63 : 2]) && (address <= mem_upper_1[63 : 2])) ||
((address >= mem_lower_2[63 : 2]) && (address <= mem_upper_2[63 : 2]))) ) begin
if (!(`false)) begin
$display("WARNING at %0t from %m",$time);
if (INP.pframenn === 1'b0) begin
$write(" \"Generated burst memory address out of boundary of defined memory address space -- disconnecting next access");
end
$display("\"");
end
disc = `true; // Force slave to disconnect
end // if
end // if
if ( io_enable && req_space === io_space ) begin
if ( ! (((address >= io_lower_0[63 : 2]) && (address <= io_upper_0[63 : 2])) ||
((address >= io_lower_1[63 : 2]) && (address <= io_upper_1[63 : 2])) ||
((address >= io_lower_2[63 : 2]) && (address <= io_upper_2[63 : 2]))) ) begin
if (!(`false)) begin
$display("WARNING at %0t from %m",$time);
if (INP.pframenn === 1'b0) begin
$write(" \"Generated burst IO address out of boundary of defined IO address space -- disconnecting next access");
end
$display("\"");
end
disc = `true; // Force slave to disconnect
end // if
end // if
end
endtask // update_address;
task write_slave_data;
integer i,j,k;
integer iaddr ;
reg [63 : 0] data ;
reg [61:0] addr ;
begin
iaddr = 0;
addr = address;
data = 64'h0;
case ( req_space )
mem_space : begin
`ifdef no_pli
data[31:0] = mem_head[addr[max_addr_width-1:0]];
if (transfer64)
data[63:32] = mem_head[addr[max_addr_width-1:0]+1];
`else
`ifdef paged
$lmv_mempage_read("mem_head",addr[61:9],addr[8:0],data[31:0]);
if (transfer64)
$lmv_mempage_read("mem_head",(addr+1)/page_size,(addr+1) % page_size,data[63:32]);
`else
$lmv_memory_read("mem_head",addr,data[31:0]);
if (transfer64)
$lmv_memory_read("mem_head",addr+1,data[63:32]);
`endif
`endif
for (j = 0; j <= 3; j = j + 1) begin
if ( cxbe_int[j] === 1'b0 ) begin
for (i = j*8+7; i >= j*8; i = i - 1) begin
data[i] = ad_int[i];
end
end // if
if ( (transfer64) ) begin
k = j + 4;
if ( cxbe_int[k] === 1'b0 ) begin
for (i = k*8+7; i >= k*8; i = i - 1) begin
data[i] = ad_int[i];
end
end // if
end // if
end // loop
`ifdef no_pli
mem_head[addr[max_addr_width-1:0]] = data[31:0];
if (transfer64)
mem_head[addr[max_addr_width-1:0]+1] = data[63:32];
`else
`ifdef paged
$lmv_mempage_write("mem_head",addr[61:9],addr[8:0],data[31:0]);
if (transfer64)
$lmv_mempage_write("mem_head",(addr+1)/page_size,(addr+1) % page_size,data[63:32]);
`else
$lmv_memory_write("mem_head",addr,data[31:0]);
if (transfer64)
$lmv_memory_write("mem_head",addr+1,data[63:32]);
`endif
`endif
if (transfer64) begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE MEMORY SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data);
end
end else begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE MEMORY SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data[31:0]);
end
end // if
end
io_space : begin
`ifdef no_pli
data[31:0] = io_head[addr[max_addr_width-1:0]];
`else
`ifdef paged
$lmv_mempage_read("io_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_read("io_head",addr,data[31:0]);
`endif
`endif
for (j = 0; j <= 3; j = j + 1) begin
if ( cxbe_int[j] === 1'b0 ) begin
for (i = j*8+7; i >= j*8; i = i - 1) begin
data[i] = ad_int[i];
end
end // if
end // loop
`ifdef no_pli
io_head[addr[max_addr_width-1:0]] = data[31:0];
`else
`ifdef paged
$lmv_mempage_write("io_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_write("io_head",addr,data[31:0]);
`endif
`endif
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE IO SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data[31:0]);
end
end
cfg_space : begin
addr[61 : 8] = 'h0;
`ifdef no_pli
data[31:0] = cfg_head[addr[max_addr_width-1:0]];
`else
`ifdef paged
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_read("cfg_head",addr,data[31:0]);
`endif
`endif
iaddr = addr[7 : 0];
case ( iaddr )
0 , 2 : begin // read only
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = NO DATA WRITTEN (Read Only)");
end
end
4 , 5 , 6 , 7 , 8 , 9 : begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = NO DATA WRITTEN (BASE ADDRESS NOT IMPLEMENTED)");
end
end
10 , 11 , 13 , 14 : begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = NO DATA WRITTEN (RESERVED)");
end
end
12 , 15 : begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = NO DATA WRITTEN (REGISTER NOT IMPLEMENTED)");
end
end
1 : begin
if ( (cxbe_int[0] === 1'b0) ) begin
data[1 : 0] = ad_int[1 : 0]; // i/o and mem space enable
if ( data[0] === 1'b1 ) begin
io_enable = `true;
end else begin
io_enable = `false;
end // if
if ( data[1] === 1'b1 ) begin
mem_enable = `true;
end else begin
mem_enable = `false;
end // if
data[3] = ad_int[3];
if ( data[3] === 1'b1 ) begin // special cycle monitoring
special_enable = `true;
end else begin
special_enable = `false;
end // if
data[6] = ad_int[6]; // parity reporting
if ( data[6] === 1'b1 ) begin
parity_enable = `true;
end else begin
parity_enable = `false;
end // if
end // if
if ( (cxbe_int[1] === 1'b0) ) begin
data[8] = ad_int[8]; // serr enable
if ( data[8] === 1'b1 ) begin
serr_enable = `true;
end else begin
serr_enable = `false;
end // if
end // if
if ( (cxbe_int[3] === 1'b0) ) begin
if ( ad_int[27] === 1'b1 ) begin
data[27] = 1'b0;
end // if
if ( ad_int[30] === 1'b1 ) begin
data[30] = 1'b0;
end // if
if ( ad_int[31] === 1'b1 ) begin
data[31] = 1'b0;
end // if
end // if
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data[31:0];
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_write("cfg_head",addr,data[31:0]);
`endif
`endif
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$write("ADDRESS = %h",addr);
else
$write("ADDRESS = %h",addr[31:0]);
$display(" (STATUS | COMMAND)");
$display("DATA = %h",data[31:0]);
end
end
3 : begin
if ( (cxbe_int[0] === 1'b0) ) begin
data[7 : 0] = ad_int[7 : 0]; // only cache line size writeable
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data[31:0];
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_write("cfg_head",addr,data[31:0]);
`endif
`endif
line_size = data[7 : 0];
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$write("ADDRESS = %h",addr);
else
$write("ADDRESS = %h",addr[31:0]);
$display(" (CACHE LINE SIZE)");
$display("DATA = %h",data[7:0]);
end
end else begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = NO DATA WRITTEN (REGISTER NOT IMPLEMENTED)");
end
end // if
end
default begin
for (j = 0; j <= 3; j = j + 1) begin
if ( cxbe_int[j] === 1'b0 ) begin
for (i = j*8+7; i >= j*8; i = i - 1) begin
data[i] = ad_int[i];
end
end // if
end // loop
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data[31:0];
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_write("cfg_head",addr,data[31:0]);
`endif
`endif
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("WRITE CONFIGURATION SPACE");
if (dual)
$display("ADDRESS = %h",addr);
else
$display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data[31:0]);
end
end
endcase
end
no_space : begin
/* null */
end
default begin
/* null */
end
endcase
end
endtask // write_slave_data;
task read_slave_data;
reg [63 : 0] data ;
reg [61:0] addr ;
begin
addr = address;
case ( req_space )
mem_space : begin
`ifdef no_pli
data[63:32] = mem_head[addr[max_addr_width-1:0]+1];
`else
`ifdef paged
$lmv_mempage_read("mem_head",addr[61:9],addr[8:0],data[31:0]);
if (transfer64)
$lmv_mempage_read("mem_head",(addr+1)/page_size,(addr+1) % page_size,data[63:32]);
`else
$lmv_memory_read("mem_head",addr,data[31:0]);
if (transfer64)
$lmv_memory_read("mem_head",addr+1,data[63:32]);
`endif
`endif
if (transfer64)
begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("READ MEMORY SPACE");
if (dual) $display("ADDRESS = %h",addr);
else $display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data);
end
end else begin
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("READ MEMORY SPACE");
if (dual) $display("ADDRESS = %h",addr);
else $display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data[31:0]);
end
end // if
end
io_space : begin
`ifdef no_pli
data[31:0] = io_head[addr[max_addr_width-1:0]];
`else
`ifdef paged
$lmv_mempage_read("io_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_read("io_head",addr,data[31:0]);
`endif
`endif
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("READ IO SPACE");
if (dual) $display("ADDRESS = %h",addr);
else $display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data[31:0]);
end
end
cfg_space : begin
addr[61 : 8] = 'h0;
`ifdef no_pli
data[31:0] = cfg_head[addr[max_addr_width-1:0]];
`else
`ifdef paged
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data[31:0]);
`else
$lmv_memory_read("cfg_head",addr,data[31:0]);
`endif
`endif
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("READ CONFIGURATION SPACE");
if (dual) $display("ADDRESS = %h",addr);
else $display("ADDRESS = %h",addr[31:0]);
$display("DATA = %h",data[31:0]);
end
end
iack_space : begin
data[31 : 0] = iack_vector;
if (model_flags.debug_level > 0) begin
$display("NOTE at %0t from %m",$time);
$display("READ IACK DATA");
$display("DATA = %h",data[31:0]);
end
end
no_space : begin
/* null */
end
default begin
/* null */
end
endcase
data_int = data;
end
endtask // read_slave_data;
task lock_enable;
begin
case ( lstate )
free : begin
if ( (! b(INP.pframenn) && b(INP.plocknn) && b(hit) &&
(bstate===sidle || bstate===sturn_ar)) ||
(b(lock_int) && b(hit) && bstate===sb_busy) ) begin
lstate = locked;
end else begin
lstate = free;
end // if
end
locked : begin
if ( b(INP.pframenn) && b(INP.plocknn) ) begin
lstate = free;
end else begin
lstate = locked;
end // if
end
endcase
end
| This page: |
Created: | Thu Aug 19 12:02:03 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcislave_fm.v
|