//
// Copyright Notice and Proprietary Information
//
// Copyright (C) 1992 - 1995 Synopsys, Inc. All rights reserved. This Software
// and manual are owned by Synopsys, Inc., and may be used only as authorized
// in the license agreement controlling such use. No part of this publication
// may be reproduced, transmitted, or translated, in any form or by any means,
// electronic, mechanical, manual, optical, or otherwise, without prior written
// permission of Synopsys, Inc., or as expressly provided by the license agreement.
//
// Destination Control Statement
//
// All technical data contained in this publication is subject to the export
// control laws of the United States of America. Disclosure to nationals of other
// countries contrary to United States law is prohibited. It is the reader's
// responsibility to determine the applicable regulations and to comply with them.
//
// Disclaimer
//
// Synopsys, Inc., makes no warranty of any kind, express or implied, with regard
// to this material, including, but not limited to, the implied warranties of
// merchantability and fitness for a particular purpose.
//
// Synopsys, Inc., reserves the right to make changes without further notice to
// the products described herein. Synopsys, Inc. does not assume any liability
// arising out of the application or use of any product or circuit described
// herein. The Synopsys products described herein are not authorized for use as
// components in life-support devices.
//
// $Version 5.3.06
// 44084 fm 05.30.96 sequential command causes endless loop
// 43984 fm 05.22.96 parameter x_transition does not work in slave, works in master
// 43840 fm 05.09.96 index out of range on integers in read_hex_file
// 43691 fm 05.09.96 target disconnects mem_write/mem_read on cacheline boundary
// 43683 fm 05.09.96 index out of range warning when compiling on vcs/veribest
// 43603 fm 05.09.96 severity error message in bus state machine
//
// $Version 5.2.15
// 43505 all 04.03.96 Verilog R8.0
// 220 fm 03.20.96 reports that memory address is outside defined memory space
// 43054 fm 03.20.96 slave unable to establish lock for dual address cycle
// 43176 fm 03.20.96 slave responds to type1 config cycles
// 42301 fm 03.13.96 hex file load malfunctions for non-dword boundaries
// 295 fm 01.05.96 workaround for cmd_mem memory consumption
// 270 fm 12.09.95 dump command does not seem to work
// 42440 fm 12.09.95 dump command not working in external mode (timing.vhd)
// 141 fm 12.08.95 pcislave not configurable to reside at single I/O
// 42366 fm 11.03.95 idle cycles while wait_on_node (vlog)
// 42349 fm 11.01.95 sequential command and esr's execution in the file mode (vlog)
// 42390 fm 11.03.95 Corrected PAR setup flag enable/disable (update_timing_flags)
// 42391 tst 11.03.95 Removed pullup on PAR pin
// 42360 fm 11.01.95 Modified latcher code to only latch INP signals (PAD)
// 402 fm 09.19.95 Trigger_fix, wait value different cause loop
//
// $End_Version
//
//
//
//
//
//
//
//
//
//
//
//
//
`lmv_timescale
![[Up: pcislave fm]](v2html-up.gif)
module pcislave_fm
(pad,pcxbenn,ppar,pframenn,ptrdynn,pirdynn,pstopnn,pdevselnn,pidsel,psbonn
,psdone,pclk,prstnn,pd,pbenn,ppar64,preq64nn,pack64nn,plocknn,pperrnn,pserrnn);
inout [31:0] pad;
reg pad_reg_31; assign pad[31] = pad_reg_31;
reg pad_reg_30; assign pad[30] = pad_reg_30;
reg pad_reg_29; assign pad[29] = pad_reg_29;
reg pad_reg_28; assign pad[28] = pad_reg_28;
reg pad_reg_27; assign pad[27] = pad_reg_27;
reg pad_reg_26; assign pad[26] = pad_reg_26;
reg pad_reg_25; assign pad[25] = pad_reg_25;
reg pad_reg_24; assign pad[24] = pad_reg_24;
reg pad_reg_23; assign pad[23] = pad_reg_23;
reg pad_reg_22; assign pad[22] = pad_reg_22;
reg pad_reg_21; assign pad[21] = pad_reg_21;
reg pad_reg_20; assign pad[20] = pad_reg_20;
reg pad_reg_19; assign pad[19] = pad_reg_19;
reg pad_reg_18; assign pad[18] = pad_reg_18;
reg pad_reg_17; assign pad[17] = pad_reg_17;
reg pad_reg_16; assign pad[16] = pad_reg_16;
reg pad_reg_15; assign pad[15] = pad_reg_15;
reg pad_reg_14; assign pad[14] = pad_reg_14;
reg pad_reg_13; assign pad[13] = pad_reg_13;
reg pad_reg_12; assign pad[12] = pad_reg_12;
reg pad_reg_11; assign pad[11] = pad_reg_11;
reg pad_reg_10; assign pad[10] = pad_reg_10;
reg pad_reg_9; assign pad[9] = pad_reg_9;
reg pad_reg_8; assign pad[8] = pad_reg_8;
reg pad_reg_7; assign pad[7] = pad_reg_7;
reg pad_reg_6; assign pad[6] = pad_reg_6;
reg pad_reg_5; assign pad[5] = pad_reg_5;
reg pad_reg_4; assign pad[4] = pad_reg_4;
reg pad_reg_3; assign pad[3] = pad_reg_3;
reg pad_reg_2; assign pad[2] = pad_reg_2;
reg pad_reg_1; assign pad[1] = pad_reg_1;
reg pad_reg_0; assign pad[0] = pad_reg_0;
input [3:0] pcxbenn;
inout ppar; reg ppar_reg; assign ppar = ppar_reg;
input pframenn;
inout ptrdynn; reg ptrdynn_reg; assign ptrdynn = ptrdynn_reg;
input pirdynn;
inout pstopnn; reg pstopnn_reg; assign pstopnn = pstopnn_reg;
output pdevselnn; reg pdevselnn;
input pidsel;
input psbonn;
input psdone;
input pclk;
input prstnn;
inout [63:32] pd;
reg pd_reg_63; assign pd[63] = pd_reg_63;
reg pd_reg_62; assign pd[62] = pd_reg_62;
reg pd_reg_61; assign pd[61] = pd_reg_61;
reg pd_reg_60; assign pd[60] = pd_reg_60;
reg pd_reg_59; assign pd[59] = pd_reg_59;
reg pd_reg_58; assign pd[58] = pd_reg_58;
reg pd_reg_57; assign pd[57] = pd_reg_57;
reg pd_reg_56; assign pd[56] = pd_reg_56;
reg pd_reg_55; assign pd[55] = pd_reg_55;
reg pd_reg_54; assign pd[54] = pd_reg_54;
reg pd_reg_53; assign pd[53] = pd_reg_53;
reg pd_reg_52; assign pd[52] = pd_reg_52;
reg pd_reg_51; assign pd[51] = pd_reg_51;
reg pd_reg_50; assign pd[50] = pd_reg_50;
reg pd_reg_49; assign pd[49] = pd_reg_49;
reg pd_reg_48; assign pd[48] = pd_reg_48;
reg pd_reg_47; assign pd[47] = pd_reg_47;
reg pd_reg_46; assign pd[46] = pd_reg_46;
reg pd_reg_45; assign pd[45] = pd_reg_45;
reg pd_reg_44; assign pd[44] = pd_reg_44;
reg pd_reg_43; assign pd[43] = pd_reg_43;
reg pd_reg_42; assign pd[42] = pd_reg_42;
reg pd_reg_41; assign pd[41] = pd_reg_41;
reg pd_reg_40; assign pd[40] = pd_reg_40;
reg pd_reg_39; assign pd[39] = pd_reg_39;
reg pd_reg_38; assign pd[38] = pd_reg_38;
reg pd_reg_37; assign pd[37] = pd_reg_37;
reg pd_reg_36; assign pd[36] = pd_reg_36;
reg pd_reg_35; assign pd[35] = pd_reg_35;
reg pd_reg_34; assign pd[34] = pd_reg_34;
reg pd_reg_33; assign pd[33] = pd_reg_33;
reg pd_reg_32; assign pd[32] = pd_reg_32;
input [7:4] pbenn;
inout ppar64; reg ppar64_reg; assign ppar64 = ppar64_reg;
input preq64nn;
output pack64nn; reg pack64nn;
input plocknn;
output pperrnn; reg pperrnn;
output pserrnn; reg pserrnn;
pcislave_fm_data_out fm_rsp();
reg [127:0] ret_val; // OUT ret_data_ary_type
parameter version = "pci33",
cfg_file = "pcislave_tst.cfg",
mem_file = "pcislave_tst.dat",
io_file = "pcislave_tst.io",
x_transition = `true,
gen_global = `true,
gen_option = `lmv_maximum,
gen_time_check = `true,
gen_x_check = `true,
gen_annotated = `false,
gen_debug_level = 0,
gen_vlt = 5000,
gen_tmp = 300,
gen_DF = 100,
device_id = 16'h0000,
vendor_id = 16'h0000,
revision_id = 8'h00,
header_type = 8'h00,
class_code = 24'h000000,
mem_lower_0_init= 64'h0000000000000000,
mem_upper_0_init= 64'h00000000000000ff,
mem_lower_1_init= 64'h0000000000000000,
mem_upper_1_init= 64'h0000000000000000,
mem_lower_2_init= 64'h0000000000000000,
mem_upper_2_init= 64'h0000000000000000,
io_lower_0_init = 64'h0000000000000100,
io_upper_0_init = 64'h00000000000001ff,
io_lower_1_init = 64'h0000000000000000,
io_upper_1_init = 64'h0000000000000000,
io_lower_2_init = 64'h0000000000000000,
io_upper_2_init = 64'h0000000000000000,
cache_line_size = 8'h00,
addr64 = `false,
data64 = `false,
iack = `false,
iack_vector = 32'h00000000;
parameter id_number = 0,
cmd_file = "pcislave_tst.cmd";
pcislave_timing timing(); // instantiation of timing package
pcislave_fm_input INP();
pcislave_fm_cntrl CNTRL();
pcislave_flags model_flags();
pcislave_times model_times();
reg init_finished; initial init_finished = `false;
integer msg_level; initial msg_level = gen_debug_level + 1;
// Tools defined directional signals for bidirectional pins,
// used in pattern generator
reg pad_d; initial pad_d = 1'b0; // 0 = input, 1 = output
reg ppar_d; initial ppar_d = 1'b0; // 0 = input, 1 = output
reg ptrdynn_d; initial ptrdynn_d = 1'b0; // 0 = input, 1 = output
reg pstopnn_d; initial pstopnn_d = 1'b0; // 0 = input, 1 = output
reg pd_d; initial pd_d = 1'b0; // 0 = input, 1 = output
reg ppar64_d; initial ppar64_d = 1'b0; // 0 = input, 1 = output
// TIMING INITIALIZATION PROCESS
initial
begin : init_process
CNTRL.pad = `true;
CNTRL.pad_in = `true;
CNTRL.r_pad_pclk = `true;
CNTRL.pcxbenn = `true;
CNTRL.r_pcxbenn_pclk = `true;
CNTRL.ppar = `true;
CNTRL.ppar_in = `true;
CNTRL.r_ppar_pclk = `true;
CNTRL.pframenn = `true;
CNTRL.r_pframenn_pclk = `true;
CNTRL.ptrdynn = `true;
CNTRL.ptrdynn_in = `true;
CNTRL.r_ptrdynn_pclk = `true;
CNTRL.pirdynn = `true;
CNTRL.r_pirdynn_pclk = `true;
CNTRL.pstopnn = `true;
CNTRL.pstopnn_in = `true;
CNTRL.r_pstopnn_pclk = `true;
CNTRL.pdevselnn = `true;
CNTRL.pidsel = `true;
CNTRL.r_pidsel_pclk = `true;
CNTRL.psbonn = `true;
CNTRL.r_psbonn_pclk = `true;
CNTRL.psdone = `true;
CNTRL.r_psdone_pclk = `true;
CNTRL.pclk = `true;
CNTRL.ck_pclk = `true;
CNTRL.prstnn = `true;
CNTRL.ck_prstnn = `true;
CNTRL.pd = `true;
CNTRL.pd_in = `true;
CNTRL.r_pd_pclk = `true;
CNTRL.pbenn = `true;
CNTRL.r_pbenn_pclk = `true;
CNTRL.ppar64 = `true;
CNTRL.ppar64_in = `true;
CNTRL.r_ppar64_pclk = `true;
CNTRL.preq64nn = `true;
CNTRL.r_preq64nn_pclk = `true;
CNTRL.pack64nn = `true;
CNTRL.plocknn = `true;
CNTRL.r_plocknn_pclk = `true;
CNTRL.pperrnn = `true;
CNTRL.pserrnn = `true;
if (gen_global === `true) begin
lmcver.get_flags(model_flags.option,model_flags.time_check,model_flags.x_check,
model_flags.annotated,model_flags.debug_level,
model_flags.vlt,model_flags.tmp,model_flags.DF);
end else begin
model_flags.option = gen_option;
model_flags.time_check = gen_time_check;
model_flags.x_check = gen_x_check;
model_flags.annotated = gen_annotated;
model_flags.vlt = gen_vlt;
model_flags.tmp = gen_tmp;
model_flags.DF = gen_DF;
end
model_flags.debug_level = gen_debug_level;
timing.get_timing(
model_times.trs_pad_pclk,
model_times.trh_pad_pclk,
model_times.twd_pad[31],
model_times.twd_pad[30],
model_times.twd_pad[29],
model_times.twd_pad[28],
model_times.twd_pad[27],
model_times.twd_pad[26],
model_times.twd_pad[25],
model_times.twd_pad[24],
model_times.twd_pad[23],
model_times.twd_pad[22],
model_times.twd_pad[21],
model_times.twd_pad[20],
model_times.twd_pad[19],
model_times.twd_pad[18],
model_times.twd_pad[17],
model_times.twd_pad[16],
model_times.twd_pad[15],
model_times.twd_pad[14],
model_times.twd_pad[13],
model_times.twd_pad[12],
model_times.twd_pad[11],
model_times.twd_pad[10],
model_times.twd_pad[9],
model_times.twd_pad[8],
model_times.twd_pad[7],
model_times.twd_pad[6],
model_times.twd_pad[5],
model_times.twd_pad[4],
model_times.twd_pad[3],
model_times.twd_pad[2],
model_times.twd_pad[1],
model_times.twd_pad[0],
model_times.tpr_pclk_pad[31:0],
model_times.tpr_pclk_pad[63:32],
model_times.tpr_pclk_pad[95:64],
model_times.tpr_pclk_pad[127:96],
model_times.tld_pad[31],
model_times.tld_pad[30],
model_times.tld_pad[29],
model_times.tld_pad[28],
model_times.tld_pad[27],
model_times.tld_pad[26],
model_times.tld_pad[25],
model_times.tld_pad[24],
model_times.tld_pad[23],
model_times.tld_pad[22],
model_times.tld_pad[21],
model_times.tld_pad[20],
model_times.tld_pad[19],
model_times.tld_pad[18],
model_times.tld_pad[17],
model_times.tld_pad[16],
model_times.tld_pad[15],
model_times.tld_pad[14],
model_times.tld_pad[13],
model_times.tld_pad[12],
model_times.tld_pad[11],
model_times.tld_pad[10],
model_times.tld_pad[9],
model_times.tld_pad[8],
model_times.tld_pad[7],
model_times.tld_pad[6],
model_times.tld_pad[5],
model_times.tld_pad[4],
model_times.tld_pad[3],
model_times.tld_pad[2],
model_times.tld_pad[1],
model_times.tld_pad[0],
model_times.trs_pcxbenn_pclk,
model_times.trh_pcxbenn_pclk,
model_times.twd_pcxbenn[3],
model_times.twd_pcxbenn[2],
model_times.twd_pcxbenn[1],
model_times.twd_pcxbenn[0],
model_times.trs_ppar_pclk,
model_times.trh_ppar_pclk,
model_times.twd_ppar,
model_times.tpr_pclk_ppar[31:0],
model_times.tpr_pclk_ppar[63:32],
model_times.tpr_pclk_ppar[95:64],
model_times.tpr_pclk_ppar[127:96],
model_times.tld_ppar,
model_times.trs_pframenn_pclk,
model_times.trh_pframenn_pclk,
model_times.twd_pframenn,
model_times.trs_ptrdynn_pclk,
model_times.trh_ptrdynn_pclk,
model_times.twd_ptrdynn,
model_times.tpr_pclk_ptrdynn[31:0],
model_times.tpr_pclk_ptrdynn[63:32],
model_times.tpr_pclk_ptrdynn[95:64],
model_times.tpr_pclk_ptrdynn[127:96],
model_times.tld_ptrdynn,
model_times.trs_pirdynn_pclk,
model_times.trh_pirdynn_pclk,
model_times.twd_pirdynn,
model_times.trs_pstopnn_pclk,
model_times.trh_pstopnn_pclk,
model_times.twd_pstopnn,
model_times.tpr_pclk_pstopnn[31:0],
model_times.tpr_pclk_pstopnn[63:32],
model_times.tpr_pclk_pstopnn[95:64],
model_times.tpr_pclk_pstopnn[127:96],
model_times.tld_pstopnn,
model_times.tpr_pclk_pdevselnn[31:0],
model_times.tpr_pclk_pdevselnn[63:32],
model_times.tpr_pclk_pdevselnn[95:64],
model_times.tpr_pclk_pdevselnn[127:96],
model_times.tld_pdevselnn,
model_times.trs_pidsel_pclk,
model_times.trh_pidsel_pclk,
model_times.twd_pidsel,
model_times.trs_psbonn_pclk,
model_times.trh_psbonn_pclk,
model_times.twd_psbonn,
model_times.trs_psdone_pclk,
model_times.trh_psdone_pclk,
model_times.twd_psdone,
model_times.tcy_min_pclk,
model_times.tcy_max_pclk,
model_times.tpwh_min_pclk,
model_times.tpwh_max_pclk,
model_times.tpwl_min_pclk,
model_times.tpwl_max_pclk,
model_times.twd_pclk,
model_times.tcy_min_prstnn,
model_times.tcy_max_prstnn,
model_times.tpwh_min_prstnn,
model_times.tpwh_max_prstnn,
model_times.tpwl_min_prstnn,
model_times.tpwl_max_prstnn,
model_times.twd_prstnn,
model_times.trs_pd_pclk,
model_times.trh_pd_pclk,
model_times.twd_pd[63],
model_times.twd_pd[62],
model_times.twd_pd[61],
model_times.twd_pd[60],
model_times.twd_pd[59],
model_times.twd_pd[58],
model_times.twd_pd[57],
model_times.twd_pd[56],
model_times.twd_pd[55],
model_times.twd_pd[54],
model_times.twd_pd[53],
model_times.twd_pd[52],
model_times.twd_pd[51],
model_times.twd_pd[50],
model_times.twd_pd[49],
model_times.twd_pd[48],
model_times.twd_pd[47],
model_times.twd_pd[46],
model_times.twd_pd[45],
model_times.twd_pd[44],
model_times.twd_pd[43],
model_times.twd_pd[42],
model_times.twd_pd[41],
model_times.twd_pd[40],
model_times.twd_pd[39],
model_times.twd_pd[38],
model_times.twd_pd[37],
model_times.twd_pd[36],
model_times.twd_pd[35],
model_times.twd_pd[34],
model_times.twd_pd[33],
model_times.twd_pd[32],
model_times.tpr_pclk_pd[31:0],
model_times.tpr_pclk_pd[63:32],
model_times.tpr_pclk_pd[95:64],
model_times.tpr_pclk_pd[127:96],
model_times.tld_pd[63],
model_times.tld_pd[62],
model_times.tld_pd[61],
model_times.tld_pd[60],
model_times.tld_pd[59],
model_times.tld_pd[58],
model_times.tld_pd[57],
model_times.tld_pd[56],
model_times.tld_pd[55],
model_times.tld_pd[54],
model_times.tld_pd[53],
model_times.tld_pd[52],
model_times.tld_pd[51],
model_times.tld_pd[50],
model_times.tld_pd[49],
model_times.tld_pd[48],
model_times.tld_pd[47],
model_times.tld_pd[46],
model_times.tld_pd[45],
model_times.tld_pd[44],
model_times.tld_pd[43],
model_times.tld_pd[42],
model_times.tld_pd[41],
model_times.tld_pd[40],
model_times.tld_pd[39],
model_times.tld_pd[38],
model_times.tld_pd[37],
model_times.tld_pd[36],
model_times.tld_pd[35],
model_times.tld_pd[34],
model_times.tld_pd[33],
model_times.tld_pd[32],
model_times.trs_pbenn_pclk,
model_times.trh_pbenn_pclk,
model_times.twd_pbenn[7],
model_times.twd_pbenn[6],
model_times.twd_pbenn[5],
model_times.twd_pbenn[4],
model_times.trs_ppar64_pclk,
model_times.trh_ppar64_pclk,
model_times.twd_ppar64,
model_times.tpr_pclk_ppar64[31:0],
model_times.tpr_pclk_ppar64[63:32],
model_times.tpr_pclk_ppar64[95:64],
model_times.tpr_pclk_ppar64[127:96],
model_times.tld_ppar64,
model_times.trs_preq64nn_pclk,
model_times.trh_preq64nn_pclk,
model_times.twd_preq64nn,
model_times.tpr_pclk_pack64nn[31:0],
model_times.tpr_pclk_pack64nn[63:32],
model_times.tpr_pclk_pack64nn[95:64],
model_times.tpr_pclk_pack64nn[127:96],
model_times.tld_pack64nn,
model_times.trs_plocknn_pclk,
model_times.trh_plocknn_pclk,
model_times.twd_plocknn,
model_times.tpr_pclk_pperrnn[31:0],
model_times.tpr_pclk_pperrnn[63:32],
model_times.tpr_pclk_pperrnn[95:64],
model_times.tpr_pclk_pperrnn[127:96],
model_times.tld_pperrnn,
model_times.tpr_pclk_pserrnn[31:0],
model_times.tpr_pclk_pserrnn[63:32],
model_times.tpr_pclk_pserrnn[95:64],
model_times.tpr_pclk_pserrnn[127:96],
model_times.tld_pserrnn,
model_times.tpd_prstnn_pad[31:0],
model_times.tpd_prstnn_pad[63:32],
model_times.tpd_prstnn_pad[95:64],
model_times.tpd_prstnn_pad[127:96],
model_times.tpd_prstnn_ppar[31:0],
model_times.tpd_prstnn_ppar[63:32],
model_times.tpd_prstnn_ppar[95:64],
model_times.tpd_prstnn_ppar[127:96],
model_times.tpd_prstnn_ptrdynn[31:0],
model_times.tpd_prstnn_ptrdynn[63:32],
model_times.tpd_prstnn_ptrdynn[95:64],
model_times.tpd_prstnn_ptrdynn[127:96],
model_times.tpd_prstnn_pstopnn[31:0],
model_times.tpd_prstnn_pstopnn[63:32],
model_times.tpd_prstnn_pstopnn[95:64],
model_times.tpd_prstnn_pstopnn[127:96],
model_times.tpd_prstnn_pdevselnn[31:0],
model_times.tpd_prstnn_pdevselnn[63:32],
model_times.tpd_prstnn_pdevselnn[95:64],
model_times.tpd_prstnn_pdevselnn[127:96],
model_times.tpd_prstnn_pd[31:0],
model_times.tpd_prstnn_pd[63:32],
model_times.tpd_prstnn_pd[95:64],
model_times.tpd_prstnn_pd[127:96],
model_times.tpd_prstnn_ppar64[31:0],
model_times.tpd_prstnn_ppar64[63:32],
model_times.tpd_prstnn_ppar64[95:64],
model_times.tpd_prstnn_ppar64[127:96],
model_times.tpd_prstnn_pack64nn[31:0],
model_times.tpd_prstnn_pack64nn[63:32],
model_times.tpd_prstnn_pack64nn[95:64],
model_times.tpd_prstnn_pack64nn[127:96],
model_times.tpd_prstnn_pperrnn[31:0],
model_times.tpd_prstnn_pperrnn[63:32],
model_times.tpd_prstnn_pperrnn[95:64],
model_times.tpd_prstnn_pperrnn[127:96],
model_times.tpd_prstnn_pserrnn[31:0],
model_times.tpd_prstnn_pserrnn[63:32],
model_times.tpd_prstnn_pserrnn[95:64],
model_times.tpd_prstnn_pserrnn[127:96],
model_flags.option,
model_flags.annotated,
model_flags.vlt,
model_flags.tmp,
model_flags.DF,
version);
pclk_check.last_rising = -50*`time_scale_multiplier;
pclk_check.last_falling = -50*`time_scale_multiplier;
prstnn_check.last_rising = -50*`time_scale_multiplier;
prstnn_check.last_falling = -50*`time_scale_multiplier;
init_finished = `true;
end // init_process
// Performs all TIMING CHECKS and X-CHECKs for signal PCLK
always begin : pclk_check
reg wait_for_0;
integer last_rising, last_falling;
if (init_finished !== `true) begin
wait (init_finished === `true);
end
if (model_flags.time_check !== `true && model_flags.x_check !== `true) begin
// Kill process if NOT USED in simulation
wait(`false);
end else begin
@(INP.pclk or CNTRL.pclk);
wait_for_0 = `true;
wait_for_0 <= #(0) `false;
@(negedge wait_for_0);
INP.pclk_last_event = $time - INP.pclk_event_time;
INP.pad_last_event = $time - INP.pad_event_time;
INP.pcxbenn_last_event = $time - INP.pcxbenn_event_time;
INP.ppar_last_event = $time - INP.ppar_event_time;
INP.pframenn_last_event = $time - INP.pframenn_event_time;
INP.ptrdynn_last_event = $time - INP.ptrdynn_event_time;
INP.pirdynn_last_event = $time - INP.pirdynn_event_time;
INP.pstopnn_last_event = $time - INP.pstopnn_event_time;
INP.pidsel_last_event = $time - INP.pidsel_event_time;
INP.psbonn_last_event = $time - INP.psbonn_event_time;
INP.psdone_last_event = $time - INP.psdone_event_time;
INP.pclk_last_event = $time - INP.pclk_event_time;
INP.prstnn_last_event = $time - INP.prstnn_event_time;
INP.pd_last_event = $time - INP.pd_event_time;
INP.pbenn_last_event = $time - INP.pbenn_event_time;
INP.ppar64_last_event = $time - INP.ppar64_event_time;
INP.preq64nn_last_event = $time - INP.preq64nn_event_time;
INP.plocknn_last_event = $time - INP.plocknn_event_time;
if ($time > 1 && CNTRL.pclk && INP.pclk_last_event <= (2*`time_unit)) begin
if (model_flags.time_check) begin
if (INP.pclk === 1'b1) begin
// Check cycle, pulse width low, and rising edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tcy_min_pclk && CNTRL.ck_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too short on pin pclk\"");
end
if (last_rising > 0 && model_times.tcy_max_pclk != 0 &&
$time - last_rising > model_times.tcy_max_pclk && CNTRL.ck_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too long on pin pclk\"");
end
if (last_falling > 0 && $time - last_falling < model_times.tpwl_min_pclk && CNTRL.ck_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too short on pin pclk\"");
end
if (last_falling > 0 && model_times.tpwl_max_pclk != 0 &&
$time - last_falling > model_times.tpwl_max_pclk && CNTRL.ck_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too long on pin pclk\"");
end
last_rising = $time;
if ((INP.pad_last_event < model_times.trs_pad_pclk) &&
CNTRL.pad_in && CNTRL.r_pad_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pad and pclk\"");
end
if ((INP.pcxbenn_last_event < model_times.trs_pcxbenn_pclk) &&
CNTRL.pcxbenn && CNTRL.r_pcxbenn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pcxbenn and pclk\"");
end
if ((INP.ppar_last_event < model_times.trs_ppar_pclk) &&
CNTRL.ppar_in && CNTRL.r_ppar_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins ppar and pclk\"");
end
if ((INP.pframenn_last_event < model_times.trs_pframenn_pclk) &&
CNTRL.pframenn && CNTRL.r_pframenn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pframenn and pclk\"");
end
if ((INP.ptrdynn_last_event < model_times.trs_ptrdynn_pclk) &&
CNTRL.ptrdynn_in && CNTRL.r_ptrdynn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins ptrdynn and pclk\"");
end
if ((INP.pirdynn_last_event < model_times.trs_pirdynn_pclk) &&
CNTRL.pirdynn && CNTRL.r_pirdynn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pirdynn and pclk\"");
end
if ((INP.pstopnn_last_event < model_times.trs_pstopnn_pclk) &&
CNTRL.pstopnn_in && CNTRL.r_pstopnn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pstopnn and pclk\"");
end
if ((INP.pidsel_last_event < model_times.trs_pidsel_pclk) &&
CNTRL.pidsel && CNTRL.r_pidsel_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pidsel and pclk\"");
end
if ((INP.psbonn_last_event < model_times.trs_psbonn_pclk) &&
CNTRL.psbonn && CNTRL.r_psbonn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins psbonn and pclk\"");
end
if ((INP.psdone_last_event < model_times.trs_psdone_pclk) &&
CNTRL.psdone && CNTRL.r_psdone_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins psdone and pclk\"");
end
if ((INP.pd_last_event < model_times.trs_pd_pclk) &&
CNTRL.pd_in && CNTRL.r_pd_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pd and pclk\"");
end
if ((INP.pbenn_last_event < model_times.trs_pbenn_pclk) &&
CNTRL.pbenn && CNTRL.r_pbenn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins pbenn and pclk\"");
end
if ((INP.ppar64_last_event < model_times.trs_ppar64_pclk) &&
CNTRL.ppar64_in && CNTRL.r_ppar64_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins ppar64 and pclk\"");
end
if ((INP.preq64nn_last_event < model_times.trs_preq64nn_pclk) &&
CNTRL.preq64nn && CNTRL.r_preq64nn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins preq64nn and pclk\"");
end
if ((INP.plocknn_last_event < model_times.trs_plocknn_pclk) &&
CNTRL.plocknn && CNTRL.r_plocknn_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Setup timing violation between pins plocknn and pclk\"");
end
end else if (INP.pclk === 1'b0) begin
// Check pulse width high, and falling edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tpwh_min_pclk && CNTRL.ck_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too short on pin pclk\"");
end
if (last_rising > 0 && model_times.tpwh_max_pclk != 0 &&
$time - last_rising > model_times.tpwh_max_pclk && CNTRL.ck_pclk) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too long on pin pclk\"");
end
last_falling = $time;
end
end
if (model_flags.x_check) begin
if (INP.pclk === 1'bx) begin
// Check for UNKNOWN value on control/clock pin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on pin pclk will be ignored\"");
end
end
end else if ($time > 1 && INP.pclk_event) begin
if (INP.pclk === 1'b1) begin
last_rising = $time;
end else if (INP.pclk === 1'b0) begin
last_falling = $time;
end
end
if ($time > 1 && model_flags.x_check) begin
if (INP.pclk === 1'b1) begin
// Disabled until next version
// if (INP.pframenn === 1'bx && CNTRL.pframenn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on pframenn input\"");
// end
// if (INP.pframenn === 1'bz && CNTRL.pframenn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on pframenn input\"");
// end
// if (INP.ptrdynn === 1'bx && CNTRL.ptrdynn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on ptrdynn input\"");
// end
// if (INP.ptrdynn === 1'bz && CNTRL.ptrdynn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on ptrdynn input\"");
// end
// if (INP.pirdynn === 1'bx && CNTRL.pirdynn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on pirdynn input\"");
// end
// if (INP.pirdynn === 1'bz && CNTRL.pirdynn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on pirdynn input\"");
// end
// if (INP.pstopnn === 1'bx && CNTRL.pstopnn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on pstopnn input\"");
// end
// if (INP.pstopnn === 1'bz && CNTRL.pstopnn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on pstopnn input\"");
// end
// if (INP.pidsel === 1'bx && CNTRL.pidsel) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on pidsel input\"");
// end
// if (INP.pidsel === 1'bz && CNTRL.pidsel) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on pidsel input\"");
// end
// if (INP.psbonn === 1'bx && CNTRL.psbonn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on psbonn input\"");
// end
// if (INP.psbonn === 1'bz && CNTRL.psbonn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on psbonn input\"");
// end
// if (INP.psdone === 1'bx && CNTRL.psdone) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on psdone input\"");
// end
// if (INP.psdone === 1'bz && CNTRL.psdone) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on psdone input\"");
// end
// if (INP.preq64nn === 1'bx && CNTRL.preq64nn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on preq64nn input\"");
// end
// if (INP.preq64nn === 1'bz && CNTRL.preq64nn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on preq64nn input\"");
// end
// if (INP.plocknn === 1'bx && CNTRL.plocknn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Unknown value on plocknn input\"");
// end
// if (INP.plocknn === 1'bz && CNTRL.plocknn) begin
// $display("WARNING at time %0t from %m",$time);
// $display(" \"Hi-Z value on plocknn input\"");
// end
end
end
end
end // pclk_check;
// Performs all TIMING CHECKS and X-CHECKs for signal PRSTNN
always begin : prstnn_check
reg wait_for_0;
integer last_rising, last_falling;
if (init_finished !== `true) begin
wait (init_finished === `true);
end
if (model_flags.time_check !== `true && model_flags.x_check !== `true) begin
// Kill process if NOT USED in simulation
wait(`false);
end else begin
@(INP.prstnn or CNTRL.prstnn);
wait_for_0 = `true;
wait_for_0 <= #(0) `false;
@(negedge wait_for_0);
INP.prstnn_last_event = $time - INP.prstnn_event_time;
INP.pad_last_event = $time - INP.pad_event_time;
INP.pcxbenn_last_event = $time - INP.pcxbenn_event_time;
INP.ppar_last_event = $time - INP.ppar_event_time;
INP.pframenn_last_event = $time - INP.pframenn_event_time;
INP.ptrdynn_last_event = $time - INP.ptrdynn_event_time;
INP.pirdynn_last_event = $time - INP.pirdynn_event_time;
INP.pstopnn_last_event = $time - INP.pstopnn_event_time;
INP.pidsel_last_event = $time - INP.pidsel_event_time;
INP.psbonn_last_event = $time - INP.psbonn_event_time;
INP.psdone_last_event = $time - INP.psdone_event_time;
INP.pclk_last_event = $time - INP.pclk_event_time;
INP.prstnn_last_event = $time - INP.prstnn_event_time;
INP.pd_last_event = $time - INP.pd_event_time;
INP.pbenn_last_event = $time - INP.pbenn_event_time;
INP.ppar64_last_event = $time - INP.ppar64_event_time;
INP.preq64nn_last_event = $time - INP.preq64nn_event_time;
INP.plocknn_last_event = $time - INP.plocknn_event_time;
if ($time > 1 && CNTRL.prstnn && INP.prstnn_last_event <= (2*`time_unit)) begin
if (model_flags.time_check) begin
if (INP.prstnn === 1'b1) begin
// Check cycle, pulse width low, and rising edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tcy_min_prstnn && CNTRL.ck_prstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too short on pin prstnn\"");
end
if (last_rising > 0 && model_times.tcy_max_prstnn != 0 &&
$time - last_rising > model_times.tcy_max_prstnn && CNTRL.ck_prstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Cycle period is too long on pin prstnn\"");
end
if (last_falling > 0 && $time - last_falling < model_times.tpwl_min_prstnn && CNTRL.ck_prstnn) begin
// $display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too short on pin prstnn\"");
end
if (last_falling > 0 && model_times.tpwl_max_prstnn != 0 &&
$time - last_falling > model_times.tpwl_max_prstnn && CNTRL.ck_prstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width low period is too long on pin prstnn\"");
end
last_rising = $time;
end else if (INP.prstnn === 1'b0) begin
// Check pulse width high, and falling edge setup times
if (last_rising > 0 && $time - last_rising < model_times.tpwh_min_prstnn && CNTRL.ck_prstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too short on pin prstnn\"");
end
if (last_rising > 0 && model_times.tpwh_max_prstnn != 0 &&
$time - last_rising > model_times.tpwh_max_prstnn && CNTRL.ck_prstnn) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Pulse width high period is too long on pin prstnn\"");
end
last_falling = $time;
end
end
if (model_flags.x_check) begin
if (INP.prstnn === 1'bx) begin
// Check for UNKNOWN value on control/clock pin
$display("WARNING at time %0t from %m",$time);
$display(" \"Unknown value on pin prstnn will be ignored\"");
end
end
end else if ($time > 1 && INP.prstnn_event) begin
if (INP.prstnn === 1'b1) begin
last_rising = $time;
end else if (INP.prstnn === 1'b0) begin
last_falling = $time;
end
end
end
end // prstnn_check;
// ----- HOLD CHECK PROCESS -----
always begin : hold_check
reg wait_for_0;
if (init_finished !== `true) begin
wait (init_finished === `true);
end
if (model_flags.time_check !== `true) begin
// Kill process if NOT USED in simulation
wait(`false);
end else begin
if ($time < 1) begin
#(`time_unit);
end
@(INP.pad or INP.pcxbenn or INP.ppar or INP.pframenn or INP.ptrdynn or INP.pirdynn or INP.pstopnn or INP.pidsel or INP.psbonn or INP.psdone or INP.pclk or INP.prstnn or INP.pd or INP.pbenn or INP.ppar64 or INP.preq64nn or INP.plocknn);
wait_for_0 = `true;
wait_for_0 <= #(0) `false;
@(negedge wait_for_0);
INP.pad_last_event = $time - INP.pad_event_time;
INP.pcxbenn_last_event = $time - INP.pcxbenn_event_time;
INP.ppar_last_event = $time - INP.ppar_event_time;
INP.pframenn_last_event = $time - INP.pframenn_event_time;
INP.ptrdynn_last_event = $time - INP.ptrdynn_event_time;
INP.pirdynn_last_event = $time - INP.pirdynn_event_time;
INP.pstopnn_last_event = $time - INP.pstopnn_event_time;
INP.pidsel_last_event = $time - INP.pidsel_event_time;
INP.psbonn_last_event = $time - INP.psbonn_event_time;
INP.psdone_last_event = $time - INP.psdone_event_time;
INP.pclk_last_event = $time - INP.pclk_event_time;
INP.prstnn_last_event = $time - INP.prstnn_event_time;
INP.pd_last_event = $time - INP.pd_event_time;
INP.pbenn_last_event = $time - INP.pbenn_event_time;
INP.ppar64_last_event = $time - INP.ppar64_event_time;
INP.preq64nn_last_event = $time - INP.preq64nn_event_time;
INP.plocknn_last_event = $time - INP.plocknn_event_time;
if (INP.pclk === 1'b1 && CNTRL.pclk) begin
if (INP.pcxbenn_last_event <= `time_unit && CNTRL.pcxbenn) begin
if (CNTRL.r_pcxbenn_pclk && INP.pclk_last_event < model_times.trh_pcxbenn_pclk &&
(INP.pclk_last_event > - model_times.trs_pcxbenn_pclk ||
(INP.pclk_last_event == 0 && model_times.trs_pcxbenn_pclk == 0))) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hold violation between pins pcxbenn and pclk\"");
end
end
if (INP.pframenn_last_event <= `time_unit && CNTRL.pframenn) begin
if (CNTRL.r_pframenn_pclk && INP.pclk_last_event < model_times.trh_pframenn_pclk &&
(INP.pclk_last_event > - model_times.trs_pframenn_pclk ||
(INP.pclk_last_event == 0 && model_times.trs_pframenn_pclk == 0))) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hold violation between pins pframenn and pclk\"");
end
end
if (INP.pirdynn_last_event <= `time_unit && CNTRL.pirdynn) begin
if (CNTRL.r_pirdynn_pclk && INP.pclk_last_event < model_times.trh_pirdynn_pclk &&
(INP.pclk_last_event > - model_times.trs_pirdynn_pclk ||
(INP.pclk_last_event == 0 && model_times.trs_pirdynn_pclk == 0))) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hold violation between pins pirdynn and pclk\"");
end
end
if (INP.pidsel_last_event <= `time_unit && CNTRL.pidsel) begin
if (CNTRL.r_pidsel_pclk && INP.pclk_last_event < model_times.trh_pidsel_pclk &&
(INP.pclk_last_event > - model_times.trs_pidsel_pclk ||
(INP.pclk_last_event == 0 && model_times.trs_pidsel_pclk == 0))) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hold violation between pins pidsel and pclk\"");
end
end
if (INP.psbonn_last_event <= `time_unit && CNTRL.psbonn) begin
if (CNTRL.r_psbonn_pclk && INP.pclk_last_event < model_times.trh_psbonn_pclk &&
(INP.pclk_last_event > - model_times.trs_psbonn_pclk ||
(INP.pclk_last_event == 0 && model_times.trs_psbonn_pclk == 0))) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hold violation between pins psbonn and pclk\"");
end
end
if (INP.psdone_last_event <= `time_unit && CNTRL.psdone) begin
if (CNTRL.r_psdone_pclk && INP.pclk_last_event < model_times.trh_psdone_pclk &&
(INP.pclk_last_event > - model_times.trs_psdone_pclk ||
(INP.pclk_last_event == 0 && model_times.trs_psdone_pclk == 0))) begin
$display("WARNING at time %0t from %m",$time);
$display(" \"Hold violation between pins psdone and pclk\"");
end
end
if (INP.pbenn_last_event <= `time_unit && CNTRL.pbenn) begin
| This page: |
Created: | Thu Aug 19 12:01:47 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcislave_fm.v
|