if ( last_par64 === 1'bz ) begin // PAR Floating
ppar64_out(1'bx,model_times.tpr_pclk_ppar64,0 *`time_scale_multiplier); // TON
end else if ( last_par !== 1'b1 ) begin // PAR64 Changing
ppar64_out(1'bx,model_times.tpr_pclk_ppar64,-2 *`time_scale_multiplier); // TH
end // if
ppar64_out(1'b1,model_times.tpr_pclk_ppar64,0 *`time_scale_multiplier);
last_par64 = 1'b1;
end else begin
if ( last_par64 === 1'bz ) begin // PAR Floating
ppar64_out(1'bx,model_times.tpr_pclk_ppar64,0 *`time_scale_multiplier); // TON
end else if ( last_par !== 1'b0 ) begin // PAR64 Changing
ppar64_out(1'bx,model_times.tpr_pclk_ppar64,-2 *`time_scale_multiplier); // TH
end // if
ppar64_out(1'b0,model_times.tpr_pclk_ppar64,0 *`time_scale_multiplier);
last_par64 = 1'b0;
end // if
end // if
end else begin
CNTRL.r_pirdynn_pclk <= #(0) `false;
if ( last_par !== 1'bz ) begin // PAR not floating
ppar_out(1'bx,model_times.tpr_pclk_ppar,-2 *`time_scale_multiplier); // TH
ppar_out(1'bz,model_times.tpr_pclk_ppar,0 *`time_scale_multiplier); // TOFF
last_par = 1'bz;
end // if
if ( transfer64 || INP.prstnn === 1'b0 ) begin
if ( last_par64 !== 1'bz ) begin // PAR64 not floating
ppar64_out(1'bx,model_times.tpr_pclk_ppar64,-2 *`time_scale_multiplier); // TH
ppar64_out(1'bz,model_times.tpr_pclk_ppar64,0 *`time_scale_multiplier); // TOFF
last_par64 = 1'bz;
end // if
end // if
end // if
last_dly = turn_around_delay;
end
endtask // parity_maker;
task parity_checker;
integer pcnt ;
integer pcnt64 ;
integer i;
reg check_aparity ;
begin
pcnt = 0;
pcnt64 = 0;
check_aparity = `false;
if ( (((last_bstate === sidle) && (bstate === ss_data || bstate === sb_busy || bstate === sturn_ar)) ||
((last_bstate === sturn_ar) && (bstate === ss_data || bstate === sb_busy))) ) begin
check_aparity = `true;
end else begin
check_aparity = `false;
end // if
if ( (check_aparity || (direction === write && ((bstate === ss_data && req_space === spc_space) ||
(last_bstate === ss_data && req_space !== spc_space && check_dparity)))) ) begin // SPR 100.091
for (i = 0; i <= 31; i = i + 1) begin
if ( last_ad[i] === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
end // loop
for (i = 0; i <= 3; i = i + 1) begin
if ( last_cbe[i] === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
end // loop
if ( INP.ppar === 1'b1 ) begin
pcnt = pcnt + 1;
end // if
if ( transfer64 ) begin
for (i = 32; i <= 63; i = i + 1) begin
if ( last_ad[i] === 1'b1 ) begin
pcnt64 = pcnt64 + 1;
end // if
end // loop
for (i = 4; i <= 7; i = i + 1) begin
if ( last_cbe[i] === 1'b1 ) begin
pcnt64 = pcnt64 + 1;
end // if
end // loop
if ( INP.ppar64 === 1'b1 ) begin
pcnt64 = pcnt64 + 1;
end // if
end // if
if ( (lmcver.rem(pcnt,2) === 1) || (lmcver.rem(pcnt64,2) === 1) ) begin
if ( check_aparity ) begin
if ( lmcver.rem(pcnt,2) === 1) begin // Address parity only on lower 32 bits (block serr)
r_derr = 1'b0;
if ( serr_enable && parity_enable ) begin
if ( last_serr === 1'bz ) begin // SERR Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TON
end else if ( last_serr !== 1'b0 ) begin // SERR Driven
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
end // if
pserrnn_out(1'b0,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TVAL
last_serr = 1'b0;
r_aerr = 1'b1;
end // if
end // if
end else begin
r_aerr = 1'b0;
r_derr = 1'b1;
if ( req_space === spc_space && serr_enable && parity_enable ) begin
if ( last_serr === 1'bz ) begin // SERR Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TON
end else if ( last_serr !== 1'b0 ) begin // SERR Driven
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
end // if
pserrnn_out(1'b0,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TVAL
last_serr = 1'b0;
end else begin
if ( last_serr !== 1'bz ) begin // SERR not Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
pserrnn_out(1'bz,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TOFF
last_serr = 1'bz;
end // if
end // if
end // if
end else if ( pe > 1 && pe < 6 ) begin
if ( check_aparity ) begin
if ( pe === 2 ) begin
r_derr = 1'b0;
if ( serr_enable && parity_enable ) begin
if ( last_serr === 1'bz ) begin // SERR Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TON
end else if ( last_serr !== 1'b0 ) begin // SERR Driven
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
end // if
pserrnn_out(1'b0,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TVAL
last_serr = 1'b0;
r_aerr = 1'b1;
end // if
end // if
end else if ( (check_dparity) ) begin
r_aerr = 1'b0;
if ( pe - 2 === tc ) begin
r_derr = 1'b1;
if ( req_space === spc_space && serr_enable && parity_enable ) begin
if ( last_serr === 1'bz ) begin // SERR Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TON
end else if ( last_serr !== 1'b0 ) begin // SERR Driven
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
end // if
pserrnn_out(1'b0,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TVAL
last_serr = 1'b0;
end else begin
if ( last_serr !== 1'bz ) begin // SERR not Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
pserrnn_out(1'bz,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TOFF
last_serr = 1'bz;
end // if
last_serr = 1'bz;
end // if
end // if
end // if
end else begin
if ( serr_enable && parity_enable ) begin
if ( last_serr === 1'bz ) begin // SERR Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TON
end else if ( last_serr !== 1'b1 ) begin // SERR Driven
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
end // if
pserrnn_out(1'b1,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TVAL
last_serr = 1'b1;
end // if
r_aerr = 1'b0;
r_derr = 1'b0;
end // if
end else begin
if ( last_serr !== 1'bz ) begin // SERR not Floating
pserrnn_out(1'bx,model_times.tpr_pclk_pserrnn,-2 *`time_scale_multiplier); // TH
pserrnn_out(1'bz,model_times.tpr_pclk_pserrnn,0 *`time_scale_multiplier); // TOFF
last_serr = 1'bz;
end // if
r_aerr = 1'b0;
r_derr = 1'b0;
end // if
last_bstate = bstate;
last_ad[31 : 0] = INP.pad;
last_ad[63 : 32] = INP.pd;
last_cbe[3 : 0] = INP.pcxbenn;
last_cbe[7 : 4] = INP.pbenn;
if ( (INP.ptrdynn === 1'b0 && INP.pirdynn === 1'b0) ) begin
check_dparity = `true;
tc = tc + 1;
end else begin
check_dparity = `false;
end // if
if ( last_bstate !== ss_data ) begin
tc = 0;
end // if
end
endtask // parity_checker;
task gen_output;
reg [31 : 0] z32 ;
begin
z32 = (32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz);
if ( (bstate === ss_data) && b(ready) && ! b(t_abort) &&
(direction === write || (direction === read && b(turn_around_delay))) ) begin
trdy_next = 1'b0;
end else begin
trdy_next = 1'b1;
end // if
case ( bstate )
ss_data , sbackoff , sturn_ar : begin
trdy_oe = 1'b1;
end
default begin
trdy_oe = 1'b0;
end
endcase
if ( trdy_oe === 1'b1 && req_space !== spc_space ) begin
if ( trdy_last === 1'bz ) begin // TRDY Floating
ptrdynn_out(1'bx,model_times.tpr_pclk_ptrdynn,0 *`time_scale_multiplier); // TON
ptrdynn_out(trdy_next,model_times.tpr_pclk_ptrdynn,0 *`time_scale_multiplier); // TVAL
end else if ( trdy_last !== trdy_next ) begin // TRDY Driven
ptrdynn_out(1'bx,model_times.tpr_pclk_ptrdynn,-2 *`time_scale_multiplier); // TH
ptrdynn_out(trdy_next,model_times.tpr_pclk_ptrdynn,0 *`time_scale_multiplier); // TVAL
end // if
trdy_last = trdy_next;
end else if ( trdy_oe === 1'b0 ) begin
if ( trdy_last !== 1'bz ) begin // TRDY NOT Floating
ptrdynn_out(1'bx,model_times.tpr_pclk_ptrdynn,-2 *`time_scale_multiplier); // TH
ptrdynn_out(1'bz,model_times.tpr_pclk_ptrdynn,0 *`time_scale_multiplier); // TOFF
trdy_last = 1'bz;
end // if
end // if
if ( (bstate === sbackoff) || ((bstate === ss_data) && (b(t_abort) || b(term) ) &&
(direction === write || (direction === read && b(turn_around_delay)))) ) begin
stop_next = 1'b0;
end else begin
stop_next = 1'b1;
end // if
if ( req_space !== spc_space ) begin
case ( bstate )
ss_data , sbackoff , sturn_ar : begin
if ( stop_last === 1'bz ) begin // STOP Floating
pstopnn_out(1'bx,model_times.tpr_pclk_pstopnn,0 *`time_scale_multiplier); // TON
pstopnn_out(stop_next,model_times.tpr_pclk_pstopnn,0 *`time_scale_multiplier); // TVAL
end else if ( stop_last !== stop_next ) begin // STOP Driven MF 11/16/94 stop problem when master waits
pstopnn_out(1'bx,model_times.tpr_pclk_pstopnn,-2 *`time_scale_multiplier); // TH
pstopnn_out(stop_next,model_times.tpr_pclk_pstopnn,0 *`time_scale_multiplier); // TVAL
end // if
stop_last = stop_next;
end
default begin
if ( stop_last !== 1'bz ) begin // STOP NOT Floating
pstopnn_out(1'bx,model_times.tpr_pclk_ptrdynn,-2 *`time_scale_multiplier); // TH
pstopnn_out(1'bz,model_times.tpr_pclk_pstopnn,0 *`time_scale_multiplier); // TOFF
stop_last = 1'bz;
end // if
end
endcase
end // if
if ( ((bstate === sbackoff) || (bstate === ss_data)) && ! b(t_abort) ) begin
devsel_next = 1'b0;
end else begin
devsel_next = 1'b1;
end // if
if ( req_space !== spc_space ) begin
case ( bstate )
ss_data , sbackoff , sturn_ar : begin
if ( devsel_last === 1'bz ) begin // DEVSEL Floating
pdevselnn_out(1'bx,model_times.tpr_pclk_pdevselnn,0 *`time_scale_multiplier); // TON
pdevselnn_out(devsel_next,model_times.tpr_pclk_pdevselnn,0 *`time_scale_multiplier); // TVAL
devsel_last = devsel_next;
if ( transfer64 ) begin
pack64nn_out(1'bx,model_times.tpr_pclk_pack64nn,0 *`time_scale_multiplier); // TON
pack64nn_out(devsel_next,model_times.tpr_pclk_pack64nn,0 *`time_scale_multiplier); // TVAL
end // if
end else if ( devsel_last !== devsel_next ) begin // DEVSEL Driven
pdevselnn_out(1'bx,model_times.tpr_pclk_pdevselnn,-2 *`time_scale_multiplier); // TH
pdevselnn_out(devsel_next,model_times.tpr_pclk_pdevselnn,0 *`time_scale_multiplier); // TVAL
devsel_last = devsel_next;
if ( transfer64 ) begin
pack64nn_out(1'bx,model_times.tpr_pclk_pack64nn,-2 *`time_scale_multiplier); // TH
pack64nn_out(devsel_next,model_times.tpr_pclk_pack64nn,0 *`time_scale_multiplier); // TVAL
end // if
end // if
end
default begin
if ( devsel_last !== 1'bz ) begin // DEVSEL NOT Floating
pdevselnn_out(1'bx,model_times.tpr_pclk_pdevselnn,-2 *`time_scale_multiplier); // TH
pdevselnn_out(1'bz,model_times.tpr_pclk_pdevselnn,0 *`time_scale_multiplier); // TOFF
pack64nn_out(1'bx,model_times.tpr_pclk_pack64nn,-2 *`time_scale_multiplier); // TH
pack64nn_out(1'bz,model_times.tpr_pclk_pack64nn,0 *`time_scale_multiplier); // TOFF
devsel_last = 1'bz;
end // if
end
endcase
end // if
case ( bstate )
ss_data : begin
if ( direction === read && (turn_around_delay === 1'b1) ) begin
if ( pad_last === z32 ) begin // PAD Floating
pad_out(32'hxxxxxxxx,model_times.tpr_pclk_pad,0 *`time_scale_multiplier); // TON
pad_out(data_int[31 : 0],model_times.tpr_pclk_pad,0 *`time_scale_multiplier); // TVAL
end else if ( pad_last !== data_int[31 : 0] ) begin // PAD Driven
pad_out(32'hxxxxxxxx,model_times.tpr_pclk_pad,-2 *`time_scale_multiplier); // TH
pad_out(data_int[31 : 0],model_times.tpr_pclk_pad,0 *`time_scale_multiplier); // TVAL
end // if
pad_last = data_int[31 : 0];
if ( transfer64 ) begin
if ( pd_last === z32 ) begin // PD Floating
pd_out(32'hxxxxxxxx,model_times.tpr_pclk_pd,0 *`time_scale_multiplier); // TON
pd_out(data_int[63 : 32],model_times.tpr_pclk_pd,0 *`time_scale_multiplier); // TVAL
end else if ( pd_last !== data_int[63 : 32] ) begin // PD Driven
pd_out(32'hxxxxxxxx,model_times.tpr_pclk_pd,-2 *`time_scale_multiplier); // TH
pd_out(data_int[63 : 32],model_times.tpr_pclk_pd,0 *`time_scale_multiplier); // TVAL
end // if
pd_last = data_int[63 : 32];
end // if
end else if ( direction === write ) begin
pad_out(32'hzzzzzzzz,model_times.tpr_pclk_pad,0 *`time_scale_multiplier); // TOFF
pad_last = 32'hzzzzzzzz;
pd_out(32'hzzzzzzzz,model_times.tpr_pclk_pd,0 *`time_scale_multiplier); // TOFF
pd_last = 32'hzzzzzzzz;
end // if
end
sturn_ar : begin
if ( pad_last !== z32 ) begin // PAD NOT Floating
pad_out(32'hxxxxxxxx,model_times.tpr_pclk_pad,-2 *`time_scale_multiplier); // TH
pad_out(32'hzzzzzzzz,model_times.tpr_pclk_pad,0 *`time_scale_multiplier); // TOFF
pad_last = 32'hzzzzzzzz;
if ( (transfer64) ) begin
pd_out(32'hxxxxxxxx,model_times.tpr_pclk_pad,-2 *`time_scale_multiplier); // TH
pd_out(32'hzzzzzzzz,model_times.tpr_pclk_pd,0 *`time_scale_multiplier); // TOFF
pd_last = 32'hzzzzzzzz;
end // if
end // if
end
sidle : begin
if ( (INP.prstnn === 1'b0) ) begin
if ( pad_last !== z32 ) begin // PAD NOT Floating
pad_out(32'hxxxxxxxx,model_times.tpr_pclk_pad,-2 *`time_scale_multiplier); // TH
pad_out(32'hzzzzzzzz,model_times.tpr_pclk_pad,0 *`time_scale_multiplier); // TOFF
pad_last = 32'hzzzzzzzz;
// if (transfer64) then
pd_out(32'hxxxxxxxx,model_times.tpr_pclk_pd,-2 *`time_scale_multiplier); // TH
pd_out(32'hzzzzzzzz,model_times.tpr_pclk_pd,0 *`time_scale_multiplier); // TOFF
pd_last = 32'hzzzzzzzz;
// end if;
end // if
end // if
end
default begin
if ( pad_last !== z32 ) begin // PAD NOT Floating
// pad_out((others => 'X'),model_times.tpr_pclk_pad,-2 ns); -- TH
pad_out(32'hzzzzzzzz,model_times.tpr_pclk_pad,0 *`time_scale_multiplier); // TOFF
pad_last = 32'hzzzzzzzz;
// if (transfer64) then
// pd_out((others => 'X'),model_times.tpr_pclk_pd,-2 ns); -- TH
pd_out(32'hzzzzzzzz,model_times.tpr_pclk_pd,0 *`time_scale_multiplier); // TOFF
pd_last = 32'hzzzzzzzz;
// end if;
end // if
end
endcase
if ( cmd_dlyd2 === write ) begin
perr_oe = trdy_oe_dlyd1;
end else begin
perr_oe = 1'b0;
end // if
trdy_oe_dlyd1 = trdy_oe;
cmd_dlyd2 = cmd_dlyd1;
cmd_dlyd1 = direction;
if ( perr_oe === 1'b1 && parity_enable && req_space !== spc_space ) begin
if ( last_perr === 1'bz ) begin // PERR Floating
pperrnn_out(1'bx,model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier); // TON
pperrnn_out(~ r_derr,model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier); // TVAL
end else if ( ! r_derr !== last_perr ) begin // PERR Driven
pperrnn_out(1'bx,model_times.tpr_pclk_pperrnn,-2 *`time_scale_multiplier); // TH
pperrnn_out(~ r_derr,model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier); // TVAL
end // if
last_perr = ~ r_derr;
end else if ( last_perr === 1'b0 ) begin // S/T/S MF 11/16/94
pperrnn_out(1'bx,model_times.tpr_pclk_pperrnn,-2 *`time_scale_multiplier); // TH
pperrnn_out(1'b1,model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier); // TVAL
last_perr = 1'b1;
end else begin
if ( last_perr !== 1'bz ) begin
pperrnn_out(1'bx,model_times.tpr_pclk_pperrnn,-2 *`time_scale_multiplier); // TH
pperrnn_out(1'bz,model_times.tpr_pclk_pperrnn,0 *`time_scale_multiplier); // TOFF
last_perr = 1'bz;
end // if
end // if
end
endtask // gen_output;
task tristate_pins;
begin
pperrnn <= #(0) 1'bz;
pserrnn <= #(0) 1'bz;
ptrdynn_reg <= #(0) 1'bz;
pdevselnn <= #(0) 1'bz;
pstopnn_reg <= #(0) 1'bz;
ppar_reg <= #(0) 1'bz;
ppar64_reg <= #(0) 1'bz;
pack64nn <= #(0) 1'bz;
pad_out(32'hzzzzzzzz,0,0 *`time_scale_multiplier);
pd_out(32'hzzzzzzzz,0,0 *`time_scale_multiplier);
end
endtask //tristate_pins
task init_slave;
reg [61 : 0] addr ;
reg [31 : 0] data ;
begin
addr = 62'h0000000000000000;
data = 32'hxxxxxxxx;
mem_lower_0 = mem_lower_0_init[63 : 0];
mem_upper_0 = mem_upper_0_init[63 : 0];
mem_lower_1 = mem_lower_1_init[63 : 0];
mem_upper_1 = mem_upper_1_init[63 : 0];
mem_lower_2 = mem_lower_2_init[63 : 0];
mem_upper_2 = mem_upper_2_init[63 : 0];
io_lower_0 = io_lower_0_init[63 : 0];
io_upper_0 = io_upper_0_init[63 : 0];
io_lower_1 = io_lower_1_init[63 : 0];
io_upper_1 = io_upper_1_init[63 : 0];
io_lower_2 = io_lower_2_init[63 : 0];
io_upper_2 = io_upper_2_init[63 : 0];
`ifdef no_pli
// no code
`else
if (model_flags.debug_level > 1) $display("%m: Loading Memory Space");
preload_mem(mem_file);
`endif
`ifdef no_pli
// no code
`else
if (model_flags.debug_level > 1) $display("%m: Loading IO Space");
preload_io(io_file);
`endif
data[31 : 16] = device_id;
data[15 : 0] = vendor_id;
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data;
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_write("cfg_head",addr,data);
`endif
`endif
addr = addr + 2;
data[31 : 8] = class_code;
data[7 : 0] = revision_id;
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data;
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_write("cfg_head",addr,data);
`endif
`endif
addr = addr + 1;
data = 32'h0;
data[23 : 16] = header_type;
data[7 : 0] = cache_line_size;
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data;
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_write("cfg_head",addr,data);
`endif
`endif
line_size = cache_line_size;
data = 32'h0;
for (i = 1; i <= 12; i = i + 1) begin
addr = addr + 1;
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data;
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_write("cfg_head",addr,data);
`endif
`endif
end // loop
// preload of configuration space after generics are assigned.
`ifdef no_pli
// no code
`else
if (model_flags.debug_level > 1) $display("%m: Loading Configuration Space");
preload_cfg(cfg_file);
`endif
addr = 32'h0;
addr = addr + 1;
`ifdef no_pli
data = cfg_head[addr[max_addr_width-1:0]];
`else
`ifdef paged
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_read("cfg_head",addr,data);
`endif
`endif
preload_cmd = 16'h0000;
preload_status = 16'h0000;
if ((data[8] ^ data[9]) !== 1'bx) begin
preload_cmd[9:8] = data[9:8]; // Fast Back-to-Back Enable & SERR Enable
end // if
if (^(data[7:4]) !== 1'bx) begin
preload_cmd[7:4] = data[7:4];
end //if
if (^(data[3:0]) !== 1'bx) begin
preload_cmd[3:0] = data[3:0];
end else begin
preload_cmd[1] = 1'b1;
preload_cmd[0] = 1'b1;
end // if
if ( data[21] !== 1'bx ) begin
preload_status[5] = data[21]; // 66 Mhz capable
end // if
if ( data[22] !== 1'bx ) begin
preload_status[6] = data[22]; // UDF Supported
end // if
if ( data[23] !== 1'bx ) begin
preload_status[7] = data[23]; // Fast Back-to-Back Capable
end // if
if ( (data[26] ^ data[25]) !== 1'bx ) begin
preload_status[10 : 9] = data[26 : 25]; // Devsel Timing
end // if
`ifdef no_pli
// no code
`else
// Build 9 reload file names
mem_fname[0] = mem_file;
mem_fname[1] = {mem_file,"1"};
mem_fname[2] = {mem_file,"2"};
mem_fname[3] = {mem_file,"3"};
mem_fname[4] = {mem_file,"4"};
mem_fname[5] = {mem_file,"5"};
mem_fname[6] = {mem_file,"6"};
mem_fname[7] = {mem_file,"7"};
mem_fname[8] = {mem_file,"8"};
mem_fname[9] = {mem_file,"9"};
io_fname[0] = io_file;
io_fname[1] = {io_file,"1"};
io_fname[2] = {io_file,"2"};
io_fname[3] = {io_file,"3"};
io_fname[4] = {io_file,"4"};
io_fname[5] = {io_file,"5"};
io_fname[6] = {io_file,"6"};
io_fname[7] = {io_file,"7"};
io_fname[8] = {io_file,"8"};
io_fname[9] = {io_file,"9"};
cfg_fname[0] = cfg_file;
cfg_fname[1] = {cfg_file,"1"};
cfg_fname[2] = {cfg_file,"2"};
cfg_fname[3] = {cfg_file,"3"};
cfg_fname[4] = {cfg_file,"4"};
cfg_fname[5] = {cfg_file,"5"};
cfg_fname[6] = {cfg_file,"6"};
cfg_fname[7] = {cfg_file,"7"};
cfg_fname[8] = {cfg_file,"8"};
cfg_fname[9] = {cfg_file,"9"};
`endif
addr64_local = addr64;
iack_local = iack;
iack_vector_local = iack_vector;
data64_local = data64;
//initialize trdy delays
for(i = 0; i <= `max_delay_index; i = i + 1) begin
ddelay[i] = 0;
end
x_transition_l <= x_transition;
request_limit = 1;
addr_decode_cycles = 0;
ddelay[1] = 0;
request_limit_last = 1;
addr_decode_cycles_last = 0;
ddelay1_last = 0;
end
endtask // init_slave
task reset_slave;
reg [61 : 0] addr ;
reg [31 : 0] data ;
begin
addr = 62'h0000000000000000;
data = 32'hxxxxxxxx;
CNTRL.pad <= #(0) `false; // disable timing checks during reset
CNTRL.pcxbenn <= #(0) `false;
CNTRL.ppar <= #(0) `false;
CNTRL.pframenn <= #(0) `false;
CNTRL.ptrdynn <= #(0) `false;
CNTRL.pirdynn <= #(0) `false;
CNTRL.pstopnn <= #(0) `false;
CNTRL.pdevselnn <= #(0) `false;
CNTRL.pidsel <= #(0) `false;
CNTRL.psbonn <= #(0) `false;
CNTRL.psdone <= #(0) `false;
CNTRL.pd <= #(0) `false;
CNTRL.pbenn <= #(0) `false;
CNTRL.ppar64 <= #(0) `false;
CNTRL.preq64nn <= #(0) `false;
CNTRL.pack64nn <= #(0) `false;
CNTRL.plocknn <= #(0) `false;
CNTRL.pperrnn <= #(0) `false;
CNTRL.pserrnn <= #(0) `false;
bstate = sidle;
pperrnn <= #(model_times.tpd_prstnn_pperrnn[lmcver.map(1'bz)]) 1'bz;
pserrnn <= #(model_times.tpd_prstnn_pserrnn[lmcver.map(1'bz)]) 1'bz;
ptrdynn_reg <= #(model_times.tpd_prstnn_ptrdynn[lmcver.map(1'bz)]) 1'bz;
pdevselnn <= #(model_times.tpd_prstnn_pdevselnn[lmcver.map(1'bz)]) 1'bz;
pstopnn_reg <= #(model_times.tpd_prstnn_pstopnn[lmcver.map(1'bz)]) 1'bz;
ppar_reg <= #(model_times.tpd_prstnn_ppar[lmcver.map(1'bz)]) 1'bz;
ppar64_reg <= #(model_times.tpd_prstnn_ppar64[lmcver.map(1'bz)]) 1'bz;
pack64nn <= #(model_times.tpd_prstnn_pack64nn[lmcver.map(1'bz)]) 1'bz;
pad_out(32'hzzzzzzzz,model_times.tpd_prstnn_pad,0 *`time_scale_multiplier);
pd_out(32'hzzzzzzzz,model_times.tpd_prstnn_pd,0 *`time_scale_multiplier);
// Initialize command/status register from preloaded values
addr = addr + 1;
data[31:16] = 16'h0000;
data[15:0] = preload_cmd;
`ifdef no_pli
cfg_head[addr[max_addr_width-1:0]] = data;
`else
`ifdef paged
$lmv_mempage_write("cfg_head",addr[61:9],addr[8:0],data);
`else
$lmv_memory_write("cfg_head",addr,data);
`endif
`endif
if ( data[0] === 1'b1 ) begin
io_enable = `true;
end else begin
io_enable = `false;
end // if
if ( data[1] === 1'b1 ) begin
mem_enable = `true;
end else begin
mem_enable = `false;
end // if
if ( data[3] === 1'b1 ) begin
special_enable = `true;
end else begin
special_enable = `false;
end // if
if ( data[6] === 1'b1 ) begin
parity_enable = `true;
end else begin
parity_enable = `false;
end // if
if ( data[8] === 1'b1 ) begin
serr_enable = `true;
end else begin
serr_enable = `false;
end // if
addr = addr + 1;
addr = addr + 1;
data = 32'h00000000;
end
endtask // reset_slave;
task trace_slave;
reg [1:6*8] lstr;
reg [1:8*8] bstr;
reg [1:15*8] cstr;
reg [1:5*8] astr;
reg [1:5*8] rstr;
reg [1:5*8] tstr;
reg [1:5*8] dstr;
reg [1:10*8] qstr;
reg [1:12*8] sstr;
reg [1:25*8] cmdstr;
begin
case ( command )
0 : begin cmdstr = "INTERRUPT ACKNOWLEDGE "; end
1 : begin cmdstr = "SPECIAL CYCLE "; end
2 : begin cmdstr = "I/O READ "; end
3 : begin cmdstr = "I/O WRITE "; end
4 : begin cmdstr = "RESERVED 4 "; end
5 : begin cmdstr = "RESERVED 5 "; end
6 : begin cmdstr = "MEMORY READ "; end
7 : begin cmdstr = "MEMORY WRITE "; end
8 : begin cmdstr = "RESERVED 8 "; end
9 : begin cmdstr = "RESERVED 9 "; end
10 : begin cmdstr = "CONFIGURATION READ "; end
11 : begin cmdstr = "CONFIGURATION WRITE "; end
12 : begin cmdstr = "MEMORY READ MULTIPLE "; end
13 : begin cmdstr = "DUAL ADDRESS CYCLE "; end
14 : begin cmdstr = "MEMORY READ LINE "; end
15 : begin cmdstr = "MEMORY WRITE & INVALIDATE"; end
default begin cmdstr = "UNKNOWN COMMAND "; end
endcase
case ( sstate )
snp_standby : begin sstr = "STANDBY "; end
snp_busy : begin sstr = "BUSY "; end
snp_clean : begin sstr = "CLEAN "; end
snp_hit_mod : begin sstr = "HIT MODIFIED"; end
endcase
case ( lstate )
free : begin lstr = "FREE "; end
locked : begin lstr = "LOCKED"; end
endcase
case ( bstate )
sidle : begin bstr = "SIDLE "; end
sturn_ar : begin bstr = "STURN_AR"; end
sb_busy : begin bstr = "SB_BUSY "; end
ss_data : begin bstr = "SS_DATA "; end
sbackoff : begin bstr = "SBACKOFF"; end
endcase
case ( cstate )
ready_first : begin cstr = "READY_FIRST "; end
sready : begin cstr = "SREADY "; end
ddelay_first : begin cstr = "DDELAY_FIRST "; end
d_delay : begin cstr = "D_DELAY "; end
terminate : begin cstr = "TERMINATE "; end
terminate_first : begin cstr = "TERMINATE_FIRST"; end
abort_first : begin cstr = "ABORT_FIRST "; end
abort : begin cstr = "ABORT "; end
endcase
case ( req_space )
io_space : begin qstr = "IO SPACE "; end
mem_space : begin qstr = "MEM SPACE "; end
cfg_space : begin qstr = "CFG SPACE "; end
iack_space : begin qstr = "IACK SPACE"; end
spc_space : begin qstr = "SPC SPACE "; end
no_space : begin qstr = "NO SPACE "; end
endcase
if ( b(t_abort) ) begin
astr = "TRUE ";
end else begin
astr = "FALSE";
end // if
if ( b(term) ) begin
tstr = "TRUE ";
end else begin
tstr = "FALSE";
end // if
if ( b(ready) ) begin
rstr = "TRUE ";
end else begin
rstr = "FALSE";
end // if
if ( direction === write ) begin
dstr = "WRITE";
end else begin
dstr = "READ ";
end // if
$display("NOTE at %0t from %m",$time);
$write(" COMMAND = ");
$display("%s",cmdstr);
$write(" BSTATE = ");
$display("%s",bstr);
$write(" CSTATE = ");
$display("%s",cstr);
$write(" LSTATE = ");
$display("%s",lstr);
$write(" SSTATE = ");
$display("%s",sstr);
$write(" SPACE = ");
$display("%s",qstr);
$write(" DIRECTION = ");
$display("%s",dstr);
$write(" READY = ");
$display("%s",rstr);
$write(" TERM = ");
$display("%s",tstr);
$write(" T_ABORT = ");
$display("%s",astr);
$display(" XFER CNT = %0d",transfer_cnt);
$display(" DELAY CNT = %0d",delay_cnt);
$display(" HIT DELAY = %0d",hit_delayer_cycles);
$display(" TURN_AR_DLY = %b\"",turn_around_delay);
end
endtask // trace_slave;
task report_slave;
reg [61:0] addr;
reg [31:0] data0, data1, data2, data3;
reg [1:8*8] astr, dstr, istr;
begin
addr = 62'h0000000000000000;
data0 = 32'hxxxxxxxx;
data1 = 32'hxxxxxxxx;
data2 = 32'hxxxxxxxx;
data3 = 32'hxxxxxxxx;
astr = "DISABLED";
dstr = "DISABLED";
istr = "DISABLED";
if (!((msg_level===`no_msg))) begin
`ifdef no_pli
data0 = cfg_head[addr[max_addr_width-1:0]];
addr = addr + 1;
data1 = cfg_head[addr[max_addr_width-1:0]];
addr = addr + 1;
data2 = cfg_head[addr[max_addr_width-1:0]];
addr = addr + 1;
data3 = cfg_head[addr[max_addr_width-1:0]];
`else
`ifdef paged
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data0);
addr = addr + 1;
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data1);
addr = addr + 1;
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data2);
addr = addr + 1;
$lmv_mempage_read("cfg_head",addr[61:9],addr[8:0],data3);
`else
$lmv_memory_read("cfg_head",addr,data0);
addr = addr + 1;
$lmv_memory_read("cfg_head",addr,data1);
addr = addr + 1;
$lmv_memory_read("cfg_head",addr,data2);
addr = addr + 1;
$lmv_memory_read("cfg_head",addr,data3);
`endif
`endif
if ( addr64_local ) begin
astr = "ENABLED ";
end // if
if ( data64_local ) begin
dstr = "ENABLED ";
end // if
if ( iack_local ) begin
istr = "ENABLED ";
end // if
$display("Note at time %0t from %m",$time);
$display(" \"SYNOPSYS PCISLAVE MODEL 5.3");
$display("");
$display(" Initialized Configuration");
$display(" Device ID = %h",data0[31:16]);
$display(" Vendor ID = %h",data0[15:0]);
$display(" Status = %h",data1[31:16]);
$display(" Command = %h",data1[15:0]);
$display(" Class Code = %h",data2[31:0]);
$display(" Revision ID = %h",data2[7:0]);
$display(" Cache Line Size = %h",data3[7:0]);
$display(" Memory Space 0 = %h : %h",mem_upper_0_init,mem_lower_0_init);
$display(" Memory Space 1 = %h : %h",mem_upper_1_init,mem_lower_1_init);
$display(" Memory Space 2 = %h : %h",mem_upper_2_init,mem_lower_2_init);
$display(" I/O Space 0 = %h : %h",io_upper_0_init,io_lower_0_init);
$display(" I/O Space 1 = %h : %h",io_upper_1_init,io_lower_1_init);
$display(" I/O Space 2 = %h : %h",io_upper_2_init,io_lower_2_init);
$display(" 64 bit addressing = %s",astr);
$display(" 64 bit data = %s",dstr);
$display(" Interrupt Ack = %s",istr);
$write(" Interrupt Vector = %h",iack_vector);
`ifdef no_pli
$display("\n PLI calls disabled");
`else
`ifdef paged
$display("\n Memory is paged");
`endif
`endif
$display("\"");
end
end
endtask // report_slave
task update_timing_flags;
begin
// control setup and hold checks
if ( INP.prstnn === 1'b1 ) begin // Reset negated
CNTRL.pad <= #(0) `true;
CNTRL.pcxbenn <= #(0) `true;
CNTRL.ppar <= #(0) `true;
CNTRL.pframenn <= #(0) `true;
CNTRL.ptrdynn <= #(0) `true;
CNTRL.pirdynn <= #(0) `true;
CNTRL.pstopnn <= #(0) `true;
CNTRL.pdevselnn <= #(0) `true;
CNTRL.pidsel <= #(0) `true;
CNTRL.pd <= #(0) `true;
CNTRL.pbenn <= #(0) `true;
CNTRL.ppar64 <= #(0) `true;
CNTRL.preq64nn <= #(0) `true;
CNTRL.pack64nn <= #(0) `true;
CNTRL.plocknn <= #(0) `true;
CNTRL.pperrnn <= #(0) `true;
CNTRL.pserrnn <= #(0) `true;
end // if
if ( (hit_resolved && hit === 1'b1) ) begin // Hit
CNTRL.r_pad_pclk <= #(0) `true;
CNTRL.r_pd_pclk <= #(0) `true;
CNTRL.r_pcxbenn_pclk <= #(0) `true;
CNTRL.r_pframenn_pclk <= #(0) `true;
CNTRL.r_preq64nn_pclk <= #(0) `true;
CNTRL.r_pidsel_pclk <= #(0) `true;
CNTRL.r_psbonn_pclk <= #(0) `true;
CNTRL.r_psdone_pclk <= #(0) `true;
if ( (direction === read) ) begin
CNTRL.r_pad_pclk <= #(0) `false;
CNTRL.r_pd_pclk <= #(0) `false;
CNTRL.r_ppar_pclk <= #(0) `false;
CNTRL.r_ppar64_pclk <= #(0) `false;
CNTRL.r_pirdynn_pclk <= #(0) `false;
if ( (INP.pirdynn === 1'b0 && INP.ptrdynn === 1'b0) ) begin
CNTRL.r_pbenn_pclk <= #(0) `true;
CNTRL.r_pcxbenn_pclk <= #(0) `true;
CNTRL.r_plocknn_pclk <= #(0) `true;
CNTRL.r_pirdynn_pclk <= #(0) `true;
end else begin
CNTRL.r_pcxbenn_pclk <= #(0) `false;
CNTRL.r_pbenn_pclk <= #(0) `false;
end // if
end else if ( (direction === write) ) begin
if (last_par !== 1'bz) begin
CNTRL.r_ppar_pclk <= #(0) `true;
CNTRL.r_ppar64_pclk <= #(0) `true;
end else begin
CNTRL.r_ppar_pclk <= #(0) `false;
CNTRL.r_ppar64_pclk <= #(0) `false;
end
if ( (INP.pirdynn === 1'b0 && INP.ptrdynn === 1'b0) ) begin
CNTRL.r_pirdynn_pclk <= #(0) `true;
CNTRL.r_pad_pclk <= #(0) `true;
CNTRL.r_pcxbenn_pclk <= #(0) `true;
CNTRL.r_pbenn_pclk <= #(0) `true;
CNTRL.r_plocknn_pclk <= #(0) `true;
if ( transfer64 ) begin
CNTRL.r_pd_pclk <= #(0) `true;
CNTRL.r_pbenn_pclk <= #(0) `true;
end else begin
CNTRL.r_pd_pclk <= #(0) `false;
CNTRL.r_pbenn_pclk <= #(0) `false;
end // if
end else begin
CNTRL.r_pad_pclk <= #(0) `false;
CNTRL.r_pd_pclk <= #(0) `false;
CNTRL.r_pcxbenn_pclk <= #(0) `false;
CNTRL.r_pbenn_pclk <= #(0) `false;
end // if
end // if
| This page: |
Created: | Thu Aug 19 12:02:08 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcislave_fm.v
|