/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
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/* */
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/* foreign patents, or pending applications. */
/* */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/* */
/******************************************************************************/
// *************************************************************************
// @(#)rl_dpc.v 1.23 10/15/93
// rl_dpc.v
//
// Description:
// The Data Path Controller block of memory subsystem in SingleSPARC.
// Refer to SingleSPARC Hardware Spec, section 2.7.4 for block diagram
// and more information.
//
//
// Dependencies:
// mem_cells.vpp defines.v dpc_bi_tri.v dpc_core.v
// dpc_logic.v dpc_cont.v dpc_par.v dpc_dpath.v
//
//
//
// *************************************************************************
// *************************************************************************
// This is the the DPC block. It has all the inter-block connections,
// the 3-state buffers and bi-dir pads.
module rl_dpc
(dp_perr, b_memdata_out, b_mempar_out,
mc_mdata0, dp_ben,
bd_mux_out1, bd_mux_out0, mc_mdata_en0,
b_memdata_in, b_mempar_in,
mc_dpct, mc_curr_st, mc_odat_hld,
mm_oddmpar, mm_parity_en,
pcic_afxm_db_oen,
ss_reset, ss_scan_mode, ss_clock,
mm_issue_req, mm_mreq,
mc_cfb_data, mm_misc2cf, mm_2nd_wd, mc_mbsy,
mm_fb_req,
quad_sel, quad_sel_dwd, out_hld_3, out_hld_2,
am_gnt_l, valid_l, am_read, sync_t0
);
output [1:0] dp_perr
; // Parity-Error condition bits.
output [63:0] b_memdata_out
; // Data out to the Data Pads.
output [1:0] b_mempar_out
; // Parity out to the Parity pads.
output [31:0] mc_mdata0
; // Write Lo-word to internal dat_bus.
// output [31:0] mc_mdata1; // Write Hi-word to internal dat_bus.
// output dp_buf0_en; // Internal Tri-enable control to MMU.
output dp_ben
; // External Tri-enable control to IO-pad.
output [63:0] mc_cfb_data
;
output quad_sel
;
output quad_sel_dwd
;
output out_hld_3
;
output out_hld_2
;
input [31:0] bd_mux_out1
; // In from internal data bus.
input [31:0] bd_mux_out0
; // In from internal data bus.
input mc_mdata_en0
; // Tri_enable, Wr Lo_word, from MMU.
// input mc_mdata_en1; // Tri_enable, Wr Hi_word, from MMU.
input [63:0] b_memdata_in
; // Data in from Data Pads.
input [1:0] b_mempar_in
; // Parity in from the Parity pads.
// bd_mdat bus, when this is asserted.
input [8:0] mc_curr_st
; // MCB current state.
input mc_odat_hld
; // MCB in Idle when 0.
input [5:0] mc_dpct
; // DPC control bus from MCB.
input mm_oddmpar
; // Selects odd/even parity.
input mm_parity_en
; // Selects parity enable.
input pcic_afxm_db_oen
; //IIep 2.0: dma_rd par c
input ss_reset
; // System Reset.
input ss_scan_mode
;
input ss_clock
; // Free running system clock.
// input mm_wbstben0; // strobe for 0th word of store double.
// input mm_wbstben1; // strobe for 1st word of store double.
input mm_issue_req
; //
input [3:0] mm_mreq
; //
input mm_misc2cf
;
input mm_2nd_wd
;
input mc_mbsy
;
input mm_fb_req
;
input am_gnt_l
; // IIe signal : DRAM bus granted to Falcon.
input valid_l
; // IIe signal : DMA r/w data valid
input am_read
; // IIe signal : DMA r/~w direction
input sync_t0
; //IIep 2.0: for dma read par chk
wire [63:0] rid
; // Data in to internal bd_mdata bus.
wire [31:0] mdata0
; // Lo & Hi uni-dir Wr data bus
// wire [31:0] mdata1; // Lo & Hi uni-dir Wr data bus
// from rl_dpc_core.
// wire mdata_en1r; // reg'd Tri_enable to tri32 Hi_wrd
wire mdata_en0
; // scan_en gated Tri_enable to tri32 Lo_wrd
// wire mdata_en1; // scan_en gated Tri_enable to tri32 Hi_wrd
wire fix_1032
; // see comments below
wire Gnd
= 1'b0 ;
wire enable_qlfr
= ~(ss_reset | ss_scan_mode);
/* remove 1 mc_mdata_en,
GReg1 hi_wrd_en (mdata_en1r, ((mc_mdata_en1)&(enable_qlfr)),
ss_clock, Gnd);
// Per fix for bug#1032, the "mdata_en1" is now gated with
// a new signal "fix_1032" that is forced to "1" while ss_reset=1
// or ss_scan_mode=1
assign fix_1032 = (ss_reset ? ss_reset : ss_scan_mode );
assign mdata_en1 = (mdata_en1r & ~fix_1032);
GReg1 lo_wrd_en (mdata_en0r, ((mc_mdata_en0)&(enable_qlfr)),
ss_clock, Gnd);
assign mdata_en0 = (mdata_en0r & ~ss_scan_mode);
*/
// enable needs to be 1 cycle earlier than data using fj tristate cell.
assign fix_1032 = (ss_reset ? ss_reset : ss_scan_mode );
wire mdata_en0_p
= ((mc_mdata_en0)&(enable_qlfr)&(~fix_1032));
/*
GReg1 lo_wrd_en (mdata_en0r, ((mc_mdata_en0)&(enable_qlfr)),
ss_clock, Gnd);
assign mdata_en0 = (mdata_en0r & ~fix_1032);
*/
rl_dpc_core dpc_core( dp_perr, mdata0 ,
b_memdata_out, b_mempar_out, dp_ben,
bd_mux_out1, bd_mux_out0, b_memdata_in, b_mempar_in,
mc_dpct, mc_curr_st, mc_odat_hld,
mm_oddmpar, mm_parity_en,
pcic_afxm_db_oen,
ss_scan_mode, ss_clock,
mm_issue_req, mm_mreq,
mc_cfb_data, mm_misc2cf, mm_2nd_wd,
mc_mbsy, mm_fb_req,
quad_sel, quad_sel_dwd, out_hld_3, out_hld_2,
am_gnt_l, valid_l, am_read,
sync_t0
);
// Added spare cells
// spares rl_dpc_spares (); commented out
// tri32 hi_wrd_wr(mc_mdata1, mdata1, mdata_en1);
//use fj tristate cell
// tri32 lo_wrd_wr(mc_mdata0, mdata0, mdata_en0);
tri_regen_32 lo_wrd_wr(mc_mdata0, mdata0, ss_clock, mdata_en0_p, ss_reset);
endmodule
This page: |
Created: | Thu Aug 19 12:03:11 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_dpc.v
|