/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/* */
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/* */
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/* */
/******************************************************************************/
// @(#)rl_memif_major.v 1.1 10/15/93
/****************************************************************************
* rl_memif_major.v
*
* Description:
* This is the top level module for memory interface.
* The MCB, DPC & RFR modules are instantiated in the
* 'rl_memif' module. No logic is uniquely defined in
* this module. Only connections between the different
* modules are defined.
*
*
* This module is instantiated by the ssparc.v module?
*
*
*
*
****************************************************************************/
module rl_memif_major
( b_memdata_out, b_mempar_out, mc_memaddr, mc_ras_l,
mc_cas_l, mc_moe_l, mc_mwe_l, simm32_sel, dp_ben, mc_mstb_l, mc_mbsy,
mc_caddr_hld, dp_perr, dp_perr_buf,
mc_mdata0, rl_memif_major_scan_out,
mc_refresh, mc_cfb_data, pdm_ready,
s_reply, aen, ab, p_reply_dec, afx_to, prom_p_reply,
quad_sel_dwd, quad_sel_dwd_1, quad_sel,
out_hld_2, out_hld_3,
mc_memaddr_in, afx_rst_page_vld, am_gnt_l, am_cstb_l, am_read,
// falcon_exists,
am_wm, mm_sbae_0,
b_memdata_in, b_mempar_in, mm_pa_a, mm_pa_b, mm_caddr,
mm_issue_req, mm_issue_req2, mm_mreq, mm_page,
mc_mdata_en0,
mm_rf_cntl, mm_oddmpar, mm_parity_en,
pcic_afxm_db_oen,
bd_mux_out1, bd_mux_out0, ss_reset, ss_clock, sp_sel,
rl_memif_major_scan_in, ss_scan_mode,
precharge_early_0,
precharge_early_1,
rfr_clock, rfr_late,
mm_2nd_wd, mm_misc2cf, mm_issue_req_early,
mm_fb_req, mm_fb_size, mm_fb_page,
gclk_1st_phase, p_reply, pcic_p_reply, mm_mem_dbg,
valid_l, cas_cyc, ab_in, am_gnt_l_oen
);
output [63:0] b_memdata_out
; // Data out to the Data Pads for DRAM.
output [1:0] b_mempar_out
; // Parity out to the Parity pads for DRAM.
output [11:00] mc_memaddr
; // Memory address to Out pads for DRAM.
output [07:00] mc_ras_l
; // Four RASes to Out pads for DRAM.
output [03:00] mc_cas_l
; // Two CASes to Out pads for DRAM.
output mc_moe_l
; // The OE to Out pads for DRAM.
output mc_mwe_l
; // The WE to Out pads for DRAM.
output dp_ben
; // External Tri-enable to IO-pad Control.
output mc_mstb_l
; // Data-ready Strobe to MMU.
output mc_mbsy
; // Memory logic busy sig to MMU.
output mc_caddr_hld
; // Hold low addr bits. To MMU.
output [1:0] dp_perr
; // Parity-Error condition bits to MMU.
output [1:0] dp_perr_buf
; // Parity-Error condition bits to MMU.
// output [1:0] dp_perr_reg; //Parity-Error condition bits,registered.
// output dp_buf0_en; // Internal Tri-enable control to mmu
output [31:0] mc_mdata0
; // Write Lo-word to internal dat_bus.
// output [31:0] mc_mdata1; // Write Hi-word to internal dat_bus.
output rl_memif_major_scan_out
;
output mc_refresh
;
output [63:0] mc_cfb_data
; // Bypass data to cache fill bus
output pdm_ready
;
output s_reply
;
output aen
;
output [14:12] ab
;
output [2:0] p_reply_dec
;
output afx_to
;
output quad_sel_dwd
;
output quad_sel_dwd_1
;
output quad_sel
;
output out_hld_2
;
output out_hld_3
;
// IIe addition : Falcon interface signals.
output valid_l
;
output cas_cyc
;
input [14:12] ab_in
;
input [11:0] mc_memaddr_in
;
output am_gnt_l
;
output afx_rst_page_vld
;
output am_gnt_l_oen
;
input am_cstb_l
;
input am_read
;
wire falcon_exists
= 1'b1;
input [1:0] am_wm
;
input mm_sbae_0
;
input [1:0] prom_p_reply
;
input [63:0] b_memdata_in
; // Data in from Data Pads for DRAM.
input [1:0] b_mempar_in
; // Parity in from the Parity pads for DRAM.
input [28:12] mm_pa_a
; // Phys-addr 26:12 from MMU.
input [02:00] mm_pa_b
; // Phys-addr 02:00 from MMU.
input [11:03] mm_caddr
; // Phys-addr 11:03 (latched) from MMU.
input mm_issue_req
; // Valid-request from MMU.
input mm_issue_req2
; // Valid-request from MMU.
input [03:00] mm_mreq
; // Mem cyc-req from MMU.
input mm_page
; // Page mode request from MMU.
input mc_mdata_en0
; // Tri_enable, Wr Lo_word, from MMU.
// input mc_mdata_en1; // Tri_enable, Wr Hi_word, from MMU.
input [3:0] mm_rf_cntl
; // Refr-rate select from MMU.
input mm_oddmpar
; // Selects odd/even parity. From MMU.
input mm_parity_en
; // Selects parity enable. From MMU.
input pcic_afxm_db_oen
; //IIep 2.0: dma_rd par c
input [31:0] bd_mux_out1
; // In from internal data bus.
input [31:0] bd_mux_out0
; // In from internal data bus.
input ss_reset
; // System Reset.
input ss_clock
; // System Clock.
input simm32_sel
; // double density simm select
input [2:0] sp_sel
; // Lo-MHz ("0") or Hi-MHz ("1") select pin. and 150-200Mhz ("2") pin.
input ss_scan_mode
;
input rl_memif_major_scan_in
;
// input mm_wbstben0; // strobe for 0th word of store double.
// input mm_wbstben1; // strobe for 1st word of store double.
// input mm_write_buffer_sel; // selcet from MMU for store buffer write.
// input [63:32] st_write_hi; // High bits from store buffer.
input precharge_early_0
; // Precharge 1 cycle for non-page access.
input precharge_early_1
; // Precharge 1 cycle for non-page access.
// input power_down_mode; // Enters power down except rfr and mcb.
input rfr_clock
; // In power_down_mode, this clock is runing.
input rfr_late
; // In power_down_mode, this late clock is runing.
input mm_misc2cf
; // select to mux data from misc to $ fill.
input mm_2nd_wd
; // select to mux d-word from misc to $ fill.
input mm_issue_req_early
; // mm_issue_req_early to hold off refresh.
input mm_fb_req
; //
input [1:0] mm_fb_size
; //
input mm_fb_page
; //
input gclk_1st_phase
; //
input [1:0] p_reply
; //
input [1:0] pcic_p_reply
; //
input [1:0] mm_mem_dbg
; //
assign dp_perr_buf[1] = dp_perr[1];
assign dp_perr_buf[0] = dp_perr[0];
wire quad_sel_dwd_1;
assign quad_sel_dwd_1 = quad_sel_dwd;
// wire mm_data_view;
// assign mm_data_view = 0;
// assign power_down_mode = 1'b0;
// assign mm_rf_cntl[3] = 1'b1;
wire mm_rf_cntl_3
;
assign mm_rf_cntl_3 = mm_rf_cntl[3];
wire [2:0] mm_rf_cntl_2_0
;
assign mm_rf_cntl_2_0 = mm_rf_cntl[2:0];
wire precharge_early_0, precharge_early_1;
// wire [63:0] b_memdata_in_inv;
// assign b_memdata_in_inv = ~b_memdata_in;
// assign mc_cfb_data = ~b_memdata_in_inv;
// assign mc_cfb_data = b_memdata_in;
// assign precharge_early_0 = 1'b0;
// assign precharge_early_1 = 1'b0;
// assign mm_write_buffer_sel = 1'b0;
// assign mc_cas_l[3] = 1'b1;
// assign mc_cas_l[2] = 1'b1;
// assign mc_ras_l[7] = 1'b1;
// assign mc_ras_l[6] = 1'b1;
// assign mc_ras_l[5] = 1'b1;
// assign mc_ras_l[4] = 1'b1;
wire mc_rack_l
; // Request Ack to RFR.
wire rf_cbr
; // Power-On CbR cycles req from RFR.
wire rf_rreq_l
; // single refr req from RFR
wire [8:0] mc_curr_st
; // MCB current state.
wire [6:0] mc_cyc_reg
; // MCB cycle type in progress.
// wire mc_cyc_reg_4; // MCB cycle type bit 4.
// assign mc_cyc_reg_4 = mc_cyc_reg[4];
wire mc_odat_hld
; // MCB in Idle when 0.
wire [5:0] mc_dpct
; // DPC control bus from MCB.
// assign sp_sel = 0 ;
wire sp_sel_0
;
wire sp_sel_1
;
wire sp_sel_2
;
// assign sp_sel_1 = 1;
// assign sp_sel_1 = 1'b0;
assign sp_sel_2 = sp_sel[2]; // added
assign sp_sel_1 = sp_sel[1];
assign sp_sel_0 = sp_sel[0];
// before mmu is connected, it needs to be here.
// wire mm_misc2cf;
// wire mm_2nd_wd;
// assign mm_misc2cf = 1'b0;
// assign mm_2nd_wd = 1'b0;
// wire sync_t0;
// assign sync_t0 = 1'b1;
// wire [1:0] p_reply;
// assign p_reply [1:0] = 2'h0;
// wire mm_pa_a_28 = 1'b1;
// wire [1:0] mm_fb_size = 2'b0;
// wire [2:0] p_reply_dec;
rl_mcb mcb (mc_memaddr, mc_ras_l, mc_cas_l, mc_moe_l, mc_mwe_l, simm32_sel,
mc_mstb_l, mc_mbsy, mc_rack_l,
mc_dpct, mc_curr_st, mc_cyc_reg, mc_odat_hld, mc_caddr_hld,
mc_refresh, pdm_ready,
s_reply, aen, ab, p_reply_dec, afx_to, prom_p_reply,
mc_memaddr_in, afx_rst_page_vld, am_gnt_l,
am_cstb_l, am_read, falcon_exists, am_wm, mm_sbae_0,
mm_pa_a, mm_pa_b, mm_caddr, mm_issue_req, mm_issue_req2,
mm_mreq, mm_page,
rf_cbr, rf_rreq_l,
ss_reset, rfr_clock, rfr_late,
sp_sel_0, sp_sel_1, sp_sel_2, precharge_early_0,
precharge_early_1,
mm_rf_cntl_3, mm_issue_req_early,
gclk_1st_phase, p_reply, pcic_p_reply, mm_fb_req, mm_fb_size, mm_fb_page,
mm_mem_dbg, valid_l, cas_cyc, ab_in, am_gnt_l_oen );
rl_dpc dpc (dp_perr, b_memdata_out, b_mempar_out,
mc_mdata0, dp_ben,
bd_mux_out1, bd_mux_out0, mc_mdata_en0,
b_memdata_in, b_mempar_in,
mc_dpct, mc_curr_st, mc_odat_hld,
mm_oddmpar, mm_parity_en,
pcic_afxm_db_oen,
ss_reset, ss_scan_mode, ss_clock,
mm_issue_req, mm_mreq,
mc_cfb_data, mm_misc2cf, mm_2nd_wd, mc_mbsy,
mm_fb_req,
quad_sel, quad_sel_dwd, out_hld_3, out_hld_2,
am_gnt_l, valid_l, am_read, gclk_1st_phase
);
rl_rfr rfr (rf_cbr, rf_rreq_l,
rfr_clock, ss_reset, mc_rack_l, mm_rf_cntl_2_0
);
endmodule
This page: |
Created: | Thu Aug 19 12:00:14 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_memif_major.v
|