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// **************************************************************************
// @(#)rl_dpc_core.v	1.23 10/13/93
// rl_dpc_core.v
//
//	Description:
//		The Data-flow and logic core of the DPC in memory subsystem of 
//		SingleSPARC. This does not contain any tri-statable or bi-dir
//		paths.
//		Refer to SingleSPARC Hardware Spec, section 2.7.4 for block diagram
//		and more information.
//
//
//	Dependencies:
//		mem_cells.vpp defines.v dpc_dpath.v dpc_par.v dpc_cont.v dpc_logic.v
//
//
//
// **************************************************************************


// **************************************************************************
// This is the core of the DPC block. It has all the inter-block connections,
//		minus any of the 3-state or bi-dir buffers & pads.


module rl_dpc_core (dp_perr, mc_mdata0 , 
	   				b_memdata_out, b_mempar_out, dp_ben,
	   				bd_mux_out1, bd_mux_out0, b_memdata_in, b_mempar_in,
					mc_dpct, mc_curr_st, mc_odat_hld,
					mm_oddmpar, mm_parity_en, 
					pcic_afxm_db_oen,
					ss_scan_mode, ss_clock,
					mm_issue_req, mm_mreq,
					mc_cfb_data, mm_misc2cf, mm_2nd_wd, 
					mc_mbsy, mm_fb_req,
					quad_sel, quad_sel_dwd, out_hld_3, out_hld_2,	
					am_gnt_l, valid_l, am_read,
					sync_t0
					);

	output	[1:0]	dp_perr;	  // Parity-Error condition bits.
	output	[31:0]	mc_mdata0 ;	  // Low data word, out to internal data bus.
//	output	[31:0]	mc_mdata1 ;   // High data word, out to internal data bus.
	output	[63:0]	b_memdata_out ;	 // Data out to the Data Pads.
	output	[1:0]	b_mempar_out;	 // Parity out to the Parity pads.
//	output			mc_mdata_en0; 	// The enable to MMU for DPC tri-buff 0.
	output			dp_ben;			// External Tri-enable control to IO-pads.
	output	[63:0]	mc_cfb_data;

	output	quad_sel;
	output	quad_sel_dwd;
	output	out_hld_3;
	output	out_hld_2;

	input	[31:0]	bd_mux_out1; // Write data, in from internal data bus.
	input	[31:0]	bd_mux_out0; // Write data, in from internal data bus.
	input	[63:0]	b_memdata_in ;	// Data in from Data Pads.
	input	[1:0]	b_mempar_in;	// Parity in from the Parity latch.
	input	[5:0]	mc_dpct;	  // DPC control bus from MCB.
	input	[8:0]	mc_curr_st;	  // MCB current state.
                                          // IIe chnages : Increased to 9 bits.
	input			mc_odat_hld;  // MCB in Idle when 0.
//	input			mdata_en1 ;
	input			mm_oddmpar;	  // Selects odd/even parity.
	input			mm_parity_en;	  // Selects enable parity.
        input  pcic_afxm_db_oen;                //IIep 2.0: dma_rd par c
	input			ss_scan_mode;
	input			ss_clock;	  // Free running system clock.
        input       mm_issue_req;        // .
        input   [3:0]   mm_mreq;        // 
	input	mm_misc2cf;
	input	mm_2nd_wd;
	input	mc_mbsy;
	input	mm_fb_req;
        input   am_gnt_l;               // IIe signal : Grant DRAM bus to Falcon
        input   valid_l;                // IIe signal : DMA r/w data valid
        input   am_read;                // IIe signal : DMA r/~w direction
        input       sync_t0;    	//IIep 2.0: for dma read par chk


	wire	[1:0]	pari;		  // Parity in from the Parity latch.
	wire	[3:0]	out_hld;
	wire	[1:0]	in_hld;
	wire	[3:0]	mux_sel;
	wire 		dp_buf0_en_dly;
//	wire 		prev_wd_sel;
	wire	[1:0]	gr_hld;
	wire 		gr_out_sel;
	wire	[63:0]	rid;
	wire	[63:0]	pod_dram;
	wire	out_hld_1;
	wire	out_hld_0;
	
	assign out_hld_3 = out_hld[3];
	assign out_hld_2 = out_hld[2];
	assign out_hld_1 = out_hld[1];
	assign out_hld_0 = out_hld[0];

	rl_dpc_dpath   dpc_dpath(	b_memdata_out, pod_dram,  mc_mdata0, rid,
					bd_mux_out1, bd_mux_out0, b_memdata_in, 
					out_hld_1, out_hld_0,in_hld,
					mux_sel, ss_clock,
					mc_cfb_data, mm_misc2cf, dp_buf0_en_dly,
					gr_hld, gr_out_sel);
	
	rl_dpc_logic   dpc_logic(	b_mempar_out, dp_perr, 
					out_hld, in_hld, dp_buf0_en_dly, dp_ben,
					mux_sel, pod_dram ,  rid,  pari ,
					mc_dpct, mc_curr_st, 
					mc_odat_hld, 
					mm_oddmpar, mm_parity_en, 
					pcic_afxm_db_oen,
					ss_scan_mode, ss_clock,
					quad_sel, 
					mm_issue_req, mm_mreq, mm_2nd_wd, mc_mbsy,
					quad_sel_dwd, gr_hld, gr_out_sel, mm_fb_req,
					am_gnt_l, valid_l, am_read,
					sync_t0);
	
	/* The flops, used for registering the incoming Parity bits with the
		dat bits, during reads...*/
// ok not to use in_hld_par here, since it simply load more than needed.
	GReg1		Pari0 (pari[0], b_mempar_in[0], ss_clock, in_hld[0]);
	GReg1		Pari1 (pari[1], b_mempar_in[1], ss_clock, in_hld[1]);

endmodule