/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
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/* Community Source License, microSPARCII ("the License"). You may not use */
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/* */
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/******************************************************************************/
// **************************************************************************
// @(#)rl_dpc_dpath.v 1.14 7/28/93
// rl_dpc_dpath.v
//
// Description:
// The data-path section of the DPC block of memory subsystem in
// SingleSPARC.
// Refer to SingleSPARC Hardware Spec, section 2.7.4 for block diagram
// and more information.
//
//
// Dependencies:
// mem_cells.vpp
//
//
//
// **************************************************************************
/**************************************************************************
* This module contains the uni-directional data-flow path of the DPC block,
* ie the in/out registers and the RMW mux as described in SingleSPARC
* Hardware Spec, section 2.7.4. But the interface to the external data bus
* via bi-dir pads or the connection to the internal data-bus via 3-state
* buffers are seperated into their own modules (rl_dpc_io & rl_dpc_tri)
* and are placed in dpc_bi_tri.v file.
*/
![[Up: rl_dpc_core dpc_dpath]](v2html-up.gif)
module rl_dpc_dpath
( pod, pod_dram, rid_out, rid,
bd_mux_out1, bd_mux_out0, pid, out_hld_1, out_hld_0,
in_hld, mux_sel,
ss_clock,
mc_cfb_data, mm_misc2cf, dp_buf0_en_dly,
gr_hld, gr_out_sel
);
output [63:0] pod; // Data out to the Data Pads.
output [63:0] pod_dram; // Data out to the parity gen for dram data only.
output [31:0] rid_out; // Data from 'in0' & 'in1' 32-bit regs to the
output [63:0] rid; // Data from 'in0' & 'in1' 64-bit regs to parity check
output [63:0] mc_cfb_data;
// 3-st buffs at the internal bi-dir data bus.
input [31:0] bd_mux_out1; // Data input from Internal bi-di data bus.
input [31:0] bd_mux_out0; // Data input from Internal bi-di data bus.
input [63:0] pid; // Data in from Data Pads.
input out_hld_1;
input out_hld_0;
input [1:0] in_hld;
input [3:0] mux_sel;
input ss_clock; // Free running system clock.
// input quad_sel; // select to reg data from out2 and out3 .
input mm_misc2cf;
input dp_buf0_en_dly;
// input prev_wd_sel;
input [1:0] gr_hld;
input gr_out_sel;
wire [63:0] rod;
wire [31:0] bd_mux_out1;
wire [31:0] bd_mux_out0;
wire [63:0] quad_data;
// wire [63:0] rid;
// wire write_buf_sel = mm_write_buffer_sel & ~quad_sel;
// wire bd_mdata_sel = ~write_buf_sel & ~quad_sel;
// Add 32-bit mux to select write buffer data or misc bus for hi 32 bits.
// Add 2 32-bit reg to store quad word write from sbc.
/* the following is moved to the memif_minor block
wire quad_sel_dwd;
assign quad_sel_dwd = prev_wd_sel | quad_sel;
Mux2_32 out1_mux (bd_mux_out1[31:0],bd_mdata[31:0],
quad_data[63:32], quad_sel_dwd);
Mux2_32 out0_mux (bd_mux_out0[31:0], bd_mdata[31:0],
quad_data[31:0], quad_sel);
GReg32 out0 (rod[31:0] , bd_mux_out0[31:0] , ss_clock ,
out_hld[0]);
GReg32 out1 (rod[63:32] , bd_mux_out1[31:0] , ss_clock ,
out_hld[1]);
GReg32 out2 (quad_data[63:32] , bd_mdata[31:0] , ss_clock ,
out_hld[2]);
GReg32 out3 (quad_data[31:0] , bd_mdata[31:0] , ss_clock ,
out_hld[3]);
*/
GReg32 out0 (rod[31:0] , bd_mux_out0[31:0] , ss_clock ,
out_hld_0);
GReg32 out1 (rod[63:32] , bd_mux_out1[31:0] , ss_clock ,
out_hld_1);
// add datapath for graphics reg.
wire [31:0] gr0;
wire [63:32] gr1;
wire [31:0] gr2;
wire [63:32] gr3;
// delay mm_misc2cf_reg to fix hold time
wire mm_misc2cf_reg_delay;
wire mm_misc2cf_reg_delay_2;
wire [63:0] rod_delay;
wire [63:0] rod_delay_2;
wire [63:0] rod_delay_3;
GReg32 grout0 (gr0[31:0], rod_delay_3[31:0], ss_clock, gr_hld[0]);
GReg32 grout1 (gr1[63:32], rod_delay_3[63:32], ss_clock, gr_hld[0]);
GReg32 grout2 (gr2[31:0], gr0[31:0], ss_clock, gr_hld[1]);
GReg32 grout3 (gr3[63:32], gr1[63:32], ss_clock, gr_hld[1]);
// add mux before in reg for asi path
wire Gnd = 1'b0;
// Mux2_32 in1_mux(mc_cfb_data[63:32],pid[63:32],pod[63:32],Gnd);
// Mux2_32 in0_mux(mc_cfb_data[31:0], pid[31:0] ,pod[31:0],Gnd);
// remove hold
// GReg1 misc2cf_reg (mm_misc2cf_reg, mm_misc2cf, ss_clock, Gnd);
Mflipflop_noop_1 misc2cf_reg (mm_misc2cf_reg, mm_misc2cf, ss_clock);
// defined above, actually used here.
JBUFDA misc2cf_delay ( .A(mm_misc2cf_reg), .O(mm_misc2cf_reg_delay) );
JBUFE misc2cf_delay_2 ( .A(mm_misc2cf_reg_delay), .O(mm_misc2cf_reg_delay_2) );
// first set of buffers
JBUFDA cfb_delay_0 ( .A(rod[0]), .O(rod_delay[0]) );
JBUFDA cfb_delay_1 ( .A(rod[1]), .O(rod_delay[1]) );
JBUFDA cfb_delay_2 ( .A(rod[2]), .O(rod_delay[2]) );
JBUFDA cfb_delay_3 ( .A(rod[3]), .O(rod_delay[3]) );
JBUFDA cfb_delay_4 ( .A(rod[4]), .O(rod_delay[4]) );
JBUFDA cfb_delay_5 ( .A(rod[5]), .O(rod_delay[5]) );
JBUFDA cfb_delay_6 ( .A(rod[6]), .O(rod_delay[6]) );
JBUFDA cfb_delay_7 ( .A(rod[7]), .O(rod_delay[7]) );
JBUFDA cfb_delay_8 ( .A(rod[8]), .O(rod_delay[8]) );
JBUFDA cfb_delay_9 ( .A(rod[9]), .O(rod_delay[9]) );
JBUFDA cfb_delay_10 ( .A(rod[10]), .O(rod_delay[10]) );
JBUFDA cfb_delay_11 ( .A(rod[11]), .O(rod_delay[11]) );
JBUFDA cfb_delay_12 ( .A(rod[12]), .O(rod_delay[12]) );
JBUFDA cfb_delay_13 ( .A(rod[13]), .O(rod_delay[13]) );
JBUFDA cfb_delay_14 ( .A(rod[14]), .O(rod_delay[14]) );
JBUFDA cfb_delay_15 ( .A(rod[15]), .O(rod_delay[15]) );
JBUFDA cfb_delay_16 ( .A(rod[16]), .O(rod_delay[16]) );
JBUFDA cfb_delay_17 ( .A(rod[17]), .O(rod_delay[17]) );
JBUFDA cfb_delay_18 ( .A(rod[18]), .O(rod_delay[18]) );
JBUFDA cfb_delay_19 ( .A(rod[19]), .O(rod_delay[19]) );
JBUFDA cfb_delay_20 ( .A(rod[20]), .O(rod_delay[20]) );
JBUFDA cfb_delay_21 ( .A(rod[21]), .O(rod_delay[21]) );
JBUFDA cfb_delay_22 ( .A(rod[22]), .O(rod_delay[22]) );
JBUFDA cfb_delay_23 ( .A(rod[23]), .O(rod_delay[23]) );
JBUFDA cfb_delay_24 ( .A(rod[24]), .O(rod_delay[24]) );
JBUFDA cfb_delay_25 ( .A(rod[25]), .O(rod_delay[25]) );
JBUFDA cfb_delay_26 ( .A(rod[26]), .O(rod_delay[26]) );
JBUFDA cfb_delay_27 ( .A(rod[27]), .O(rod_delay[27]) );
JBUFDA cfb_delay_28 ( .A(rod[28]), .O(rod_delay[28]) );
JBUFDA cfb_delay_29 ( .A(rod[29]), .O(rod_delay[29]) );
JBUFDA cfb_delay_30 ( .A(rod[30]), .O(rod_delay[30]) );
JBUFDA cfb_delay_31 ( .A(rod[31]), .O(rod_delay[31]) );
JBUFDA cfb_delay_32 ( .A(rod[32]), .O(rod_delay[32]) );
JBUFDA cfb_delay_33 ( .A(rod[33]), .O(rod_delay[33]) );
JBUFDA cfb_delay_34 ( .A(rod[34]), .O(rod_delay[34]) );
JBUFDA cfb_delay_35 ( .A(rod[35]), .O(rod_delay[35]) );
JBUFDA cfb_delay_36 ( .A(rod[36]), .O(rod_delay[36]) );
JBUFDA cfb_delay_37 ( .A(rod[37]), .O(rod_delay[37]) );
JBUFDA cfb_delay_38 ( .A(rod[38]), .O(rod_delay[38]) );
JBUFDA cfb_delay_39 ( .A(rod[39]), .O(rod_delay[39]) );
JBUFDA cfb_delay_40 ( .A(rod[40]), .O(rod_delay[40]) );
JBUFDA cfb_delay_41 ( .A(rod[41]), .O(rod_delay[41]) );
JBUFDA cfb_delay_42 ( .A(rod[42]), .O(rod_delay[42]) );
JBUFDA cfb_delay_43 ( .A(rod[43]), .O(rod_delay[43]) );
JBUFDA cfb_delay_44 ( .A(rod[44]), .O(rod_delay[44]) );
JBUFDA cfb_delay_45 ( .A(rod[45]), .O(rod_delay[45]) );
JBUFDA cfb_delay_46 ( .A(rod[46]), .O(rod_delay[46]) );
JBUFDA cfb_delay_47 ( .A(rod[47]), .O(rod_delay[47]) );
JBUFDA cfb_delay_48 ( .A(rod[48]), .O(rod_delay[48]) );
JBUFDA cfb_delay_49 ( .A(rod[49]), .O(rod_delay[49]) );
JBUFDA cfb_delay_50 ( .A(rod[50]), .O(rod_delay[50]) );
JBUFDA cfb_delay_51 ( .A(rod[51]), .O(rod_delay[51]) );
JBUFDA cfb_delay_52 ( .A(rod[52]), .O(rod_delay[52]) );
JBUFDA cfb_delay_53 ( .A(rod[53]), .O(rod_delay[53]) );
JBUFDA cfb_delay_54 ( .A(rod[54]), .O(rod_delay[54]) );
JBUFDA cfb_delay_55 ( .A(rod[55]), .O(rod_delay[55]) );
JBUFDA cfb_delay_56 ( .A(rod[56]), .O(rod_delay[56]) );
JBUFDA cfb_delay_57 ( .A(rod[57]), .O(rod_delay[57]) );
JBUFDA cfb_delay_58 ( .A(rod[58]), .O(rod_delay[58]) );
JBUFDA cfb_delay_59 ( .A(rod[59]), .O(rod_delay[59]) );
JBUFDA cfb_delay_60 ( .A(rod[60]), .O(rod_delay[60]) );
JBUFDA cfb_delay_61 ( .A(rod[61]), .O(rod_delay[61]) );
JBUFDA cfb_delay_62 ( .A(rod[62]), .O(rod_delay[62]) );
JBUFDA cfb_delay_63 ( .A(rod[63]), .O(rod_delay[63]) );
// second set of buffers
JBUFDA cfb_delay_2_0 ( .A(rod_delay[0]), .O(rod_delay_2[0]) );
JBUFDA cfb_delay_2_1 ( .A(rod_delay[1]), .O(rod_delay_2[1]) );
JBUFDA cfb_delay_2_2 ( .A(rod_delay[2]), .O(rod_delay_2[2]) );
JBUFDA cfb_delay_2_3 ( .A(rod_delay[3]), .O(rod_delay_2[3]) );
JBUFDA cfb_delay_2_4 ( .A(rod_delay[4]), .O(rod_delay_2[4]) );
JBUFDA cfb_delay_2_5 ( .A(rod_delay[5]), .O(rod_delay_2[5]) );
JBUFDA cfb_delay_2_6 ( .A(rod_delay[6]), .O(rod_delay_2[6]) );
JBUFDA cfb_delay_2_7 ( .A(rod_delay[7]), .O(rod_delay_2[7]) );
JBUFDA cfb_delay_2_8 ( .A(rod_delay[8]), .O(rod_delay_2[8]) );
JBUFDA cfb_delay_2_9 ( .A(rod_delay[9]), .O(rod_delay_2[9]) );
JBUFDA cfb_delay_2_10 ( .A(rod_delay[10]), .O(rod_delay_2[10]) );
JBUFDA cfb_delay_2_11 ( .A(rod_delay[11]), .O(rod_delay_2[11]) );
JBUFDA cfb_delay_2_12 ( .A(rod_delay[12]), .O(rod_delay_2[12]) );
JBUFDA cfb_delay_2_13 ( .A(rod_delay[13]), .O(rod_delay_2[13]) );
JBUFDA cfb_delay_2_14 ( .A(rod_delay[14]), .O(rod_delay_2[14]) );
JBUFDA cfb_delay_2_15 ( .A(rod_delay[15]), .O(rod_delay_2[15]) );
JBUFDA cfb_delay_2_16 ( .A(rod_delay[16]), .O(rod_delay_2[16]) );
JBUFDA cfb_delay_2_17 ( .A(rod_delay[17]), .O(rod_delay_2[17]) );
JBUFDA cfb_delay_2_18 ( .A(rod_delay[18]), .O(rod_delay_2[18]) );
JBUFDA cfb_delay_2_19 ( .A(rod_delay[19]), .O(rod_delay_2[19]) );
JBUFDA cfb_delay_2_20 ( .A(rod_delay[20]), .O(rod_delay_2[20]) );
JBUFDA cfb_delay_2_21 ( .A(rod_delay[21]), .O(rod_delay_2[21]) );
JBUFDA cfb_delay_2_22 ( .A(rod_delay[22]), .O(rod_delay_2[22]) );
JBUFDA cfb_delay_2_23 ( .A(rod_delay[23]), .O(rod_delay_2[23]) );
JBUFDA cfb_delay_2_24 ( .A(rod_delay[24]), .O(rod_delay_2[24]) );
JBUFDA cfb_delay_2_25 ( .A(rod_delay[25]), .O(rod_delay_2[25]) );
JBUFDA cfb_delay_2_26 ( .A(rod_delay[26]), .O(rod_delay_2[26]) );
JBUFDA cfb_delay_2_27 ( .A(rod_delay[27]), .O(rod_delay_2[27]) );
JBUFDA cfb_delay_2_28 ( .A(rod_delay[28]), .O(rod_delay_2[28]) );
JBUFDA cfb_delay_2_29 ( .A(rod_delay[29]), .O(rod_delay_2[29]) );
JBUFDA cfb_delay_2_30 ( .A(rod_delay[30]), .O(rod_delay_2[30]) );
JBUFDA cfb_delay_2_31 ( .A(rod_delay[31]), .O(rod_delay_2[31]) );
JBUFDA cfb_delay_2_32 ( .A(rod_delay[32]), .O(rod_delay_2[32]) );
JBUFDA cfb_delay_2_33 ( .A(rod_delay[33]), .O(rod_delay_2[33]) );
JBUFDA cfb_delay_2_34 ( .A(rod_delay[34]), .O(rod_delay_2[34]) );
JBUFDA cfb_delay_2_35 ( .A(rod_delay[35]), .O(rod_delay_2[35]) );
JBUFDA cfb_delay_2_36 ( .A(rod_delay[36]), .O(rod_delay_2[36]) );
JBUFDA cfb_delay_2_37 ( .A(rod_delay[37]), .O(rod_delay_2[37]) );
JBUFDA cfb_delay_2_38 ( .A(rod_delay[38]), .O(rod_delay_2[38]) );
JBUFDA cfb_delay_2_39 ( .A(rod_delay[39]), .O(rod_delay_2[39]) );
JBUFDA cfb_delay_2_40 ( .A(rod_delay[40]), .O(rod_delay_2[40]) );
JBUFDA cfb_delay_2_41 ( .A(rod_delay[41]), .O(rod_delay_2[41]) );
JBUFDA cfb_delay_2_42 ( .A(rod_delay[42]), .O(rod_delay_2[42]) );
JBUFDA cfb_delay_2_43 ( .A(rod_delay[43]), .O(rod_delay_2[43]) );
JBUFDA cfb_delay_2_44 ( .A(rod_delay[44]), .O(rod_delay_2[44]) );
JBUFDA cfb_delay_2_45 ( .A(rod_delay[45]), .O(rod_delay_2[45]) );
JBUFDA cfb_delay_2_46 ( .A(rod_delay[46]), .O(rod_delay_2[46]) );
JBUFDA cfb_delay_2_47 ( .A(rod_delay[47]), .O(rod_delay_2[47]) );
JBUFDA cfb_delay_2_48 ( .A(rod_delay[48]), .O(rod_delay_2[48]) );
JBUFDA cfb_delay_2_49 ( .A(rod_delay[49]), .O(rod_delay_2[49]) );
JBUFDA cfb_delay_2_50 ( .A(rod_delay[50]), .O(rod_delay_2[50]) );
JBUFDA cfb_delay_2_51 ( .A(rod_delay[51]), .O(rod_delay_2[51]) );
JBUFDA cfb_delay_2_52 ( .A(rod_delay[52]), .O(rod_delay_2[52]) );
JBUFDA cfb_delay_2_53 ( .A(rod_delay[53]), .O(rod_delay_2[53]) );
JBUFDA cfb_delay_2_54 ( .A(rod_delay[54]), .O(rod_delay_2[54]) );
JBUFDA cfb_delay_2_55 ( .A(rod_delay[55]), .O(rod_delay_2[55]) );
JBUFDA cfb_delay_2_56 ( .A(rod_delay[56]), .O(rod_delay_2[56]) );
JBUFDA cfb_delay_2_57 ( .A(rod_delay[57]), .O(rod_delay_2[57]) );
JBUFDA cfb_delay_2_58 ( .A(rod_delay[58]), .O(rod_delay_2[58]) );
JBUFDA cfb_delay_2_59 ( .A(rod_delay[59]), .O(rod_delay_2[59]) );
JBUFDA cfb_delay_2_60 ( .A(rod_delay[60]), .O(rod_delay_2[60]) );
JBUFDA cfb_delay_2_61 ( .A(rod_delay[61]), .O(rod_delay_2[61]) );
JBUFDA cfb_delay_2_62 ( .A(rod_delay[62]), .O(rod_delay_2[62]) );
JBUFDA cfb_delay_2_63 ( .A(rod_delay[63]), .O(rod_delay_2[63]) );
// third set of buffers
/* remove 1 level of buffers
JBUFDA cfb_delay_3_0 ( .A(rod_delay_2[0]), .O(rod_delay_3[0]) );
JBUFDA cfb_delay_3_1 ( .A(rod_delay_2[1]), .O(rod_delay_3[1]) );
JBUFDA cfb_delay_3_2 ( .A(rod_delay_2[2]), .O(rod_delay_3[2]) );
JBUFDA cfb_delay_3_3 ( .A(rod_delay_2[3]), .O(rod_delay_3[3]) );
JBUFDA cfb_delay_3_4 ( .A(rod_delay_2[4]), .O(rod_delay_3[4]) );
JBUFDA cfb_delay_3_5 ( .A(rod_delay_2[5]), .O(rod_delay_3[5]) );
JBUFDA cfb_delay_3_6 ( .A(rod_delay_2[6]), .O(rod_delay_3[6]) );
JBUFDA cfb_delay_3_7 ( .A(rod_delay_2[7]), .O(rod_delay_3[7]) );
JBUFDA cfb_delay_3_8 ( .A(rod_delay_2[8]), .O(rod_delay_3[8]) );
JBUFDA cfb_delay_3_9 ( .A(rod_delay_2[9]), .O(rod_delay_3[9]) );
JBUFDA cfb_delay_3_10 ( .A(rod_delay_2[10]), .O(rod_delay_3[10]) );
JBUFDA cfb_delay_3_11 ( .A(rod_delay_2[11]), .O(rod_delay_3[11]) );
JBUFDA cfb_delay_3_12 ( .A(rod_delay_2[12]), .O(rod_delay_3[12]) );
JBUFDA cfb_delay_3_13 ( .A(rod_delay_2[13]), .O(rod_delay_3[13]) );
JBUFDA cfb_delay_3_14 ( .A(rod_delay_2[14]), .O(rod_delay_3[14]) );
JBUFDA cfb_delay_3_15 ( .A(rod_delay_2[15]), .O(rod_delay_3[15]) );
JBUFDA cfb_delay_3_16 ( .A(rod_delay_2[16]), .O(rod_delay_3[16]) );
JBUFDA cfb_delay_3_17 ( .A(rod_delay_2[17]), .O(rod_delay_3[17]) );
JBUFDA cfb_delay_3_18 ( .A(rod_delay_2[18]), .O(rod_delay_3[18]) );
JBUFDA cfb_delay_3_19 ( .A(rod_delay_2[19]), .O(rod_delay_3[19]) );
JBUFDA cfb_delay_3_20 ( .A(rod_delay_2[20]), .O(rod_delay_3[20]) );
JBUFDA cfb_delay_3_21 ( .A(rod_delay_2[21]), .O(rod_delay_3[21]) );
JBUFDA cfb_delay_3_22 ( .A(rod_delay_2[22]), .O(rod_delay_3[22]) );
JBUFDA cfb_delay_3_23 ( .A(rod_delay_2[23]), .O(rod_delay_3[23]) );
JBUFDA cfb_delay_3_24 ( .A(rod_delay_2[24]), .O(rod_delay_3[24]) );
JBUFDA cfb_delay_3_25 ( .A(rod_delay_2[25]), .O(rod_delay_3[25]) );
JBUFDA cfb_delay_3_26 ( .A(rod_delay_2[26]), .O(rod_delay_3[26]) );
JBUFDA cfb_delay_3_27 ( .A(rod_delay_2[27]), .O(rod_delay_3[27]) );
JBUFDA cfb_delay_3_28 ( .A(rod_delay_2[28]), .O(rod_delay_3[28]) );
JBUFDA cfb_delay_3_29 ( .A(rod_delay_2[29]), .O(rod_delay_3[29]) );
JBUFDA cfb_delay_3_30 ( .A(rod_delay_2[30]), .O(rod_delay_3[30]) );
JBUFDA cfb_delay_3_31 ( .A(rod_delay_2[31]), .O(rod_delay_3[31]) );
JBUFDA cfb_delay_3_32 ( .A(rod_delay_2[32]), .O(rod_delay_3[32]) );
JBUFDA cfb_delay_3_33 ( .A(rod_delay_2[33]), .O(rod_delay_3[33]) );
JBUFDA cfb_delay_3_34 ( .A(rod_delay_2[34]), .O(rod_delay_3[34]) );
JBUFDA cfb_delay_3_35 ( .A(rod_delay_2[35]), .O(rod_delay_3[35]) );
JBUFDA cfb_delay_3_36 ( .A(rod_delay_2[36]), .O(rod_delay_3[36]) );
JBUFDA cfb_delay_3_37 ( .A(rod_delay_2[37]), .O(rod_delay_3[37]) );
JBUFDA cfb_delay_3_38 ( .A(rod_delay_2[38]), .O(rod_delay_3[38]) );
JBUFDA cfb_delay_3_39 ( .A(rod_delay_2[39]), .O(rod_delay_3[39]) );
JBUFDA cfb_delay_3_40 ( .A(rod_delay_2[40]), .O(rod_delay_3[40]) );
JBUFDA cfb_delay_3_41 ( .A(rod_delay_2[41]), .O(rod_delay_3[41]) );
JBUFDA cfb_delay_3_42 ( .A(rod_delay_2[42]), .O(rod_delay_3[42]) );
JBUFDA cfb_delay_3_43 ( .A(rod_delay_2[43]), .O(rod_delay_3[43]) );
JBUFDA cfb_delay_3_44 ( .A(rod_delay_2[44]), .O(rod_delay_3[44]) );
JBUFDA cfb_delay_3_45 ( .A(rod_delay_2[45]), .O(rod_delay_3[45]) );
JBUFDA cfb_delay_3_46 ( .A(rod_delay_2[46]), .O(rod_delay_3[46]) );
JBUFDA cfb_delay_3_47 ( .A(rod_delay_2[47]), .O(rod_delay_3[47]) );
JBUFDA cfb_delay_3_48 ( .A(rod_delay_2[48]), .O(rod_delay_3[48]) );
JBUFDA cfb_delay_3_49 ( .A(rod_delay_2[49]), .O(rod_delay_3[49]) );
JBUFDA cfb_delay_3_50 ( .A(rod_delay_2[50]), .O(rod_delay_3[50]) );
JBUFDA cfb_delay_3_51 ( .A(rod_delay_2[51]), .O(rod_delay_3[51]) );
JBUFDA cfb_delay_3_52 ( .A(rod_delay_2[52]), .O(rod_delay_3[52]) );
JBUFDA cfb_delay_3_53 ( .A(rod_delay_2[53]), .O(rod_delay_3[53]) );
JBUFDA cfb_delay_3_54 ( .A(rod_delay_2[54]), .O(rod_delay_3[54]) );
JBUFDA cfb_delay_3_55 ( .A(rod_delay_2[55]), .O(rod_delay_3[55]) );
JBUFDA cfb_delay_3_56 ( .A(rod_delay_2[56]), .O(rod_delay_3[56]) );
JBUFDA cfb_delay_3_57 ( .A(rod_delay_2[57]), .O(rod_delay_3[57]) );
JBUFDA cfb_delay_3_58 ( .A(rod_delay_2[58]), .O(rod_delay_3[58]) );
JBUFDA cfb_delay_3_59 ( .A(rod_delay_2[59]), .O(rod_delay_3[59]) );
JBUFDA cfb_delay_3_60 ( .A(rod_delay_2[60]), .O(rod_delay_3[60]) );
JBUFDA cfb_delay_3_61 ( .A(rod_delay_2[61]), .O(rod_delay_3[61]) );
JBUFDA cfb_delay_3_62 ( .A(rod_delay_2[62]), .O(rod_delay_3[62]) );
JBUFDA cfb_delay_3_63 ( .A(rod_delay_2[63]), .O(rod_delay_3[63]) );
*/
assign rod_delay_3[63:0] = rod_delay_2[63:0];
Mux2_32 in1_mux(mc_cfb_data[63:32],pid[63:32],rod_delay_3[63:32],mm_misc2cf_reg_delay_2);
Mux2_32 in0_mux(mc_cfb_data[31:0], pid[31:0] ,rod_delay_3[31:0],mm_misc2cf_reg_delay_2);
GReg32 in0 (rid[31:0], mc_cfb_data[31:0] , ss_clock , in_hld[0]);
GReg32 in1 (rid[63:32], mc_cfb_data[63:32], ss_clock, in_hld[1]);
// wire [63:0] pod_dram;
Mux8x8_2to1 dmux (pod_dram[63:0] , rod[63:0] , rid[63:0] ,
{mux_sel[3:0] , mux_sel[3:0]} );
// add mux for graphics after rmw path.
Mux2_32 gr1_mux(pod[63:32],pod_dram[63:32],gr3[63:32],gr_out_sel);
Mux2_32 gr0_mux(pod[31:0], pod_dram[31:0] ,gr2[31:0],gr_out_sel);
Mux2_32 rid_out_mux(rid_out[31:0], rid[63:32], rid[31:0], dp_buf0_en_dly);
endmodule
| This page: |
Created: | Thu Aug 19 12:02:25 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_dpc_dpath.v
|