/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)sc.v
***
****************************************************************************
****************************************************************************/
//
// Verilog Library For: stdcells_swift
// revision:"8.0.0"
// date : "Apr-22-1993, 17:36"
//
//
//
// *********************************
// * VERILOG LIBRARY PROLOG *
// *********************************
//
// April 92, created
// 03-05-93, modified most ff's to match with sunrise lib
// 03-10-93, removed all "p-arcs" for flip-flops
// 03-31-93, renamed all fj_xxx flops to xxx,
// 04-20-93, moved all flops back to fj_xxx again
//
// *********************************
// * NON-SCAN FLIP-FLOPS *
// * (Referenced by "gen_ver") *
// *********************************
// D Flip-Flop
// D Flip-Flop, with async clear
// D Flip-Flop, with async set
// D Flip-Flop, with async clear & set
// *********************************
// * SCAN FLIP-FLOPS *
// * (Referenced by "gen_ver") *
// *********************************
// scan D Flip-Flop
// scan D Flip-Flop, with async clear
// scan D Flip-Flop, with async set
// scan D Flip-Flop, with async clear & set
// *********************************
// * LATCH MODELS *
// * (Referenced by "gen_ver") *
// *********************************
// *********************************
// * STRANGE CONTROL GATES *
// * (Referenced by "gen_ver") *
// *********************************
// merge dual-polarity control to single (for transmission gate)
// *********************************
// * MISC GATES *
// * (Used in hand-written models) *
// *********************************
// ******************************************
//
// Power Clip Cells
//
![[Up: ME_TIEOFF gnd]](v2html-up.gif)
module N1Z000
( O ); /* 0 Clip */
output O;
assign O = 1'b0;
endmodule
module N1Z001( O ); /* 1 Clip */
output O;
assign O = 1'b1;
endmodule
// *********************************
// * END-OF-PROLOG *
// *********************************
// Standard Inverter
module ACINVA(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Power Clock Inverter
module ACINVB(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Double Power Clock Inverter
module ACINVC(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Double Power Clock Inverter
module ACINVD(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Tripple Power Clock Inverter
module ACINVE(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Tripple Power Clock Inverter
module ACINVF(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Quadruple Power Clock Inverter
module ACINVG(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Quadruple Power Clock Inverter
module ACINVH(A, O);
input A;
output O;
not g0(O, A);
endmodule
// 1-bit Full Adder
module ADD2(A, B, CIN, S, C);
input A;
input B;
input CIN;
output S;
output C;
xor g0(S, A, B, CIN);
and g1(w3, A, B);
or g2(w8, A, B);
and g3(w6, CIN, w8);
or g4(C, w3, w6);
endmodule
// 3 input Full Adder
module ADD3(X1, X2, X3, CIN, S, C, COUT);
input X1;
input X2;
input X3;
input CIN;
output S;
output C;
output COUT;
xor g0(S, X1, X2, X3, CIN);
not g1(w9, X3);
or g2(w7, CIN, w9);
and g3(w4, X1, X2, w7);
not g4(w12, X1);
xor g5(w13, X2, X3);
and g6(w10, CIN, w12, w13);
not g7(w19, X3);
and g8(w16, CIN, X1, w19);
or g9(C, w4, w10, w16);
or g10(w20, X1, X2);
and g11(COUT, w20, X3);
endmodule
// 4 input Full Adder
module ADD4(X1, X2, X3, X4, CIN, S, C, COUT);
input X1;
input X2;
input X3;
input X4;
input CIN;
output S;
output C;
output COUT;
xor g0(S, X1, X2, X3, X4, CIN);
and g1(w8, X1, X2);
and g2(w11, X3, X4);
or g3(w7, w8, w11);
and g4(w5, CIN, w7);
xor g5(w15, CIN, X1);
not g6(w19, X3);
not g7(w20, X4);
and g8(w14, w15, X2, w19, w20);
not g9(w23, X1);
not g10(w24, X2);
xor g11(w25, X3, X4);
and g12(w21, CIN, w23, w24, w25);
not g13(w29, CIN);
xnor g14(w32, X1, X2);
and g15(w28, w29, X3, X4, w32);
not g16(w38, X3);
not g17(w39, X4);
and g18(w35, CIN, X1, w38, w39);
or g19(C, w5, w14, w21, w28, w35);
or g20(w40, X1, X2);
or g21(w43, X3, X4);
and g22(COUT, w40, w43);
endmodule
// 2-Input NOR Gate
module PP1(X, Y, P);
input X;
input Y;
output P;
nor g0(P, X, Y);
endmodule
// 2-Input NOR Gate
module PP2(X0, X1, Y2, Y3, P0, P1);
input X0;
input X1;
input Y2;
input Y3;
output P0;
output P1;
nor g0(P0, X0, Y3);
nor g1(P1, X1, Y2);
endmodule
// 2-Input NOR Gate
module PP3(X0, X1, X2, Y1, Y2, Y3, P0, P1, P2);
input X0;
input X1;
input X2;
input Y1;
input Y2;
input Y3;
output P0;
output P1;
output P2;
nor g0(P0, X0, Y3);
nor g1(P1, X1, Y2);
nor g2(P2, X2, Y1);
endmodule
// 2-Input NOR Gate
module PP4(X0, X1, X2, X3, Y0, Y1, Y2, Y3, P0, P1, P2,
P3);
input X0;
input X1;
input X2;
input X3;
input Y0;
input Y1;
input Y2;
input Y3;
output P0;
output P1;
output P2;
output P3;
nor g0(P0, X0, Y3);
nor g1(P1, X1, Y2);
nor g2(P2, X2, Y1);
nor g3(P3, X3, Y0);
endmodule
// mux - nor
module PP21(X0, X1, Y2, Y3, S, C, PASS, P0, P1, P2, P3);
input X0;
input X1;
input Y2;
input Y3;
input S;
input C;
input PASS;
output P0;
output P1;
output P2;
output P3;
nor g0(P0, X0, Y3);
nor g1(P1, X1, Y2);
and g2(P2, S, PASS);
and g3(P3, C, PASS);
endmodule
// GND or input mux
module PP23(S, C, PASS, P0, P1);
input S;
input C;
input PASS;
output P0;
output P1;
and g0(P0, S, PASS);
and g1(P1, C, PASS);
endmodule
// mux - nor
module PP24(X, Y, S, C, PASS, P0, P1, P2);
input X;
input Y;
input S;
input C;
input PASS;
output P0;
output P1;
output P2;
nor g0(P0, X, Y);
and g1(P1, S, PASS);
and g2(P2, C, PASS);
endmodule
// mux - nor
module PP25(X0, X1, Y2, Y3, S, C, PASS, P0, P1, P2);
input X0;
input X1;
input Y2;
input Y3;
input S;
input C;
input PASS;
output P0;
output P1;
output P2;
nor g0(P0, X1, Y2);
nor g1(w3, X0, Y3);
not g2(w6, PASS);
and g3(w2, w3, w6);
and g4(w7, S, PASS);
or g5(P1, w2, w7);
and g6(P2, C, PASS);
endmodule
// mux - nor
module PP26(X0, X1, X2, Y1, Y2, Y3, S, C, PASS, P0, P1,
P2);
input X0;
input X1;
input X2;
input Y1;
input Y2;
input Y3;
input S;
input C;
input PASS;
output P0;
output P1;
output P2;
nor g0(P0, X2, Y1);
nor g1(w3, X1, Y2);
not g2(w6, PASS);
and g3(w2, w3, w6);
and g4(w7, S, PASS);
or g5(P1, w2, w7);
nor g6(w11, X0, Y3);
not g7(w14, PASS);
and g8(w10, w11, w14);
and g9(w15, C, PASS);
or g10(P2, w10, w15);
endmodule
// mux - nor
module PP52_27(X0, X1, X2, X3, Y0, Y1, Y2, Y3, S, C, PASS,
P0, P1, P2, P3);
input X0;
input X1;
input X2;
input X3;
input Y0;
input Y1;
input Y2;
input Y3;
input S;
input C;
input PASS;
output P0;
output P1;
output P2;
output P3;
nor g0(P0, X3, Y0);
nor g1(w3, X2, Y1);
not g2(w6, PASS);
and g3(w2, w3, w6);
and g4(w7, S, PASS);
or g5(P1, w2, w7);
nor g6(w11, X1, Y2);
not g7(w14, PASS);
and g8(w10, w11, w14);
and g9(w15, C, PASS);
or g10(P2, w10, w15);
nor g11(P3, X0, Y3, PASS);
endmodule
// Standard Inverter
module MACINVA(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Power Clock Inverter
module MACINVB(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Double Power Clock Inverter
module MACINVC(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Double Power Clock Inverter
module MACINVD(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Tripple Power Clock Inverter
module MACINVE(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Tripple Power Clock Inverter
module MACINVF(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Quadruple Power Clock Inverter
module MACINVG(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Quadruple Power Clock Inverter
module MACINVH(A, O);
input A;
output O;
not g0(O, A);
endmodule
// ALL CLOCK BUFFERS
//module ACALLBUF(SS_CLK, RFR_CLK, RFR_LATE, RCC_CLK, SBUS_CLK,
module ACALLBUF(SS_CLK, RFR_CLK, RFR_LATE, RCC_CLK,
SBOCLK, PCI_CLK, GCLK, SS_CLK_T, SS_CLK_L, SS_CLK_B,
SS_CLK_R, RFR_CLK_D, RFR_LATE_D, GCLK_I, REF_CLK_I,
//SBOCLK_S, SBUS_CLK_I, PCI_CLK_I, RCC_CLK_M);
SBOCLK_S, PCI_CLK_I, RCC_CLK_M);
input SS_CLK;
input RFR_CLK;
input RFR_LATE;
input RCC_CLK;
//input SBUS_CLK;
input SBOCLK;
input PCI_CLK;
input GCLK;
output SS_CLK_T;
output SS_CLK_L;
output SS_CLK_B;
output SS_CLK_R;
output RFR_CLK_D;
output RFR_LATE_D;
output GCLK_I;
output REF_CLK_I;
output SBOCLK_S;
//output SBUS_CLK_I;
output PCI_CLK_I;
output RCC_CLK_M;
buf g0(SS_CLK_T, SS_CLK);
buf g1(SS_CLK_L, SS_CLK);
buf g2(SS_CLK_B, SS_CLK);
buf g3(SS_CLK_R, SS_CLK);
buf g4(RFR_CLK_D, RFR_CLK);
buf g5(RFR_LATE_D, RFR_LATE);
buf g6(GCLK_I, GCLK);
buf g7(REF_CLK_I, SS_CLK);
buf g8(SBOCLK_S, SBOCLK);
//buf g9(SBUS_CLK_I, SBUS_CLK);
buf g10(PCI_CLK_I, PCI_CLK);
buf g11(RCC_CLK_M, RCC_CLK);
endmodule
// 8 SS_CLK Buffers
module ACSSBUF(SS_CLK_UNBUF, SS_CLK_BUF1, SS_CLK_BUF2, SS_CLK_BUF3,
SS_CLK_BUF4, SS_CLK_BUF5, SS_CLK_BUF6, SS_CLK_BUF7,
SS_CLK_BUF8);
input SS_CLK_UNBUF;
output SS_CLK_BUF1;
output SS_CLK_BUF2;
output SS_CLK_BUF3;
output SS_CLK_BUF4;
output SS_CLK_BUF5;
output SS_CLK_BUF6;
output SS_CLK_BUF7;
output SS_CLK_BUF8;
buf g0(SS_CLK_BUF1, SS_CLK_UNBUF);
buf g1(SS_CLK_BUF2, SS_CLK_UNBUF);
buf g2(SS_CLK_BUF3, SS_CLK_UNBUF);
buf g3(SS_CLK_BUF4, SS_CLK_UNBUF);
buf g4(SS_CLK_BUF5, SS_CLK_UNBUF);
buf g5(SS_CLK_BUF6, SS_CLK_UNBUF);
buf g6(SS_CLK_BUF7, SS_CLK_UNBUF);
buf g7(SS_CLK_BUF8, SS_CLK_UNBUF);
endmodule
// 8 SS_CLK Buffers and RFR_CLK and RFR_LATE buffers
module ACSS2MEM(SS_CLK_UNBUF, RFR_CLK_UNBUF, RFR_LATE_UNBUF,
SS_CLK_BUF1, SS_CLK_BUF2, SS_CLK_BUF3, SS_CLK_BUF4,
SS_CLK_BUF5, SS_CLK_BUF6, SS_CLK_BUF7, SS_CLK_BUF8,
RFR_CLK, RFR_LATE);
input SS_CLK_UNBUF;
input RFR_CLK_UNBUF;
input RFR_LATE_UNBUF;
output SS_CLK_BUF1;
output SS_CLK_BUF2;
output SS_CLK_BUF3;
output SS_CLK_BUF4;
output SS_CLK_BUF5;
output SS_CLK_BUF6;
output SS_CLK_BUF7;
output SS_CLK_BUF8;
output RFR_CLK;
output RFR_LATE;
buf g0(SS_CLK_BUF1, SS_CLK_UNBUF);
buf g1(SS_CLK_BUF2, SS_CLK_UNBUF);
buf g2(SS_CLK_BUF3, SS_CLK_UNBUF);
buf g3(SS_CLK_BUF4, SS_CLK_UNBUF);
buf g4(SS_CLK_BUF5, SS_CLK_UNBUF);
buf g5(SS_CLK_BUF6, SS_CLK_UNBUF);
buf g6(SS_CLK_BUF7, SS_CLK_UNBUF);
buf g7(SS_CLK_BUF8, SS_CLK_UNBUF);
buf g8(RFR_CLK, RFR_CLK_UNBUF);
buf g9(RFR_LATE, RFR_LATE_UNBUF);
endmodule
// 8 SS_CLK Buffers and RCC_CLK buffer
module ACSS2MISC(SS_CLK_UNBUF, RCC_CLK_UNBUF, SS_CLK_BUF1,
SS_CLK_BUF2, SS_CLK_BUF3, SS_CLK_BUF4, SS_CLK_BUF5,
SS_CLK_BUF6, SS_CLK_BUF7, SS_CLK_BUF8, RCC_CLK);
input SS_CLK_UNBUF;
input RCC_CLK_UNBUF;
output SS_CLK_BUF1;
output SS_CLK_BUF2;
output SS_CLK_BUF3;
output SS_CLK_BUF4;
output SS_CLK_BUF5;
output SS_CLK_BUF6;
output SS_CLK_BUF7;
output SS_CLK_BUF8;
output RCC_CLK;
buf g0(SS_CLK_BUF1, SS_CLK_UNBUF);
buf g1(SS_CLK_BUF2, SS_CLK_UNBUF);
buf g2(SS_CLK_BUF3, SS_CLK_UNBUF);
buf g3(SS_CLK_BUF4, SS_CLK_UNBUF);
buf g4(SS_CLK_BUF5, SS_CLK_UNBUF);
buf g5(SS_CLK_BUF6, SS_CLK_UNBUF);
buf g6(SS_CLK_BUF7, SS_CLK_UNBUF);
buf g7(SS_CLK_BUF8, SS_CLK_UNBUF);
buf g8(RCC_CLK, RCC_CLK_UNBUF);
endmodule
// 8 SS_CLK Buffers and SBO_CLK buffer
module ACSS2SBC(SS_CLK_UNBUF, SBO_CLK_UNBUF, SS_CLK_BUF1,
SS_CLK_BUF2, SS_CLK_BUF3, SS_CLK_BUF4, SS_CLK_BUF5,
SS_CLK_BUF6, SS_CLK_BUF7, SS_CLK_BUF8, SBO_CLK);
input SS_CLK_UNBUF;
input SBO_CLK_UNBUF;
output SS_CLK_BUF1;
output SS_CLK_BUF2;
output SS_CLK_BUF3;
output SS_CLK_BUF4;
output SS_CLK_BUF5;
output SS_CLK_BUF6;
output SS_CLK_BUF7;
output SS_CLK_BUF8;
output SBO_CLK;
buf g0(SS_CLK_BUF1, SS_CLK_UNBUF);
buf g1(SS_CLK_BUF2, SS_CLK_UNBUF);
buf g2(SS_CLK_BUF3, SS_CLK_UNBUF);
buf g3(SS_CLK_BUF4, SS_CLK_UNBUF);
buf g4(SS_CLK_BUF5, SS_CLK_UNBUF);
buf g5(SS_CLK_BUF6, SS_CLK_UNBUF);
buf g6(SS_CLK_BUF7, SS_CLK_UNBUF);
buf g7(SS_CLK_BUF8, SS_CLK_UNBUF);
buf g8(SBO_CLK, SBO_CLK_UNBUF);
endmodule
// end of stdcells_swiftsp library
// 1-bit Half Adder
module JHAD1A(A, B, S, CO);
input A;
input B;
output S;
output CO;
xor g0(S, A, B);
and g1(CO, A, B);
endmodule
// Hi-speed 1-bit Full Adder
module JFAD1B(A, B, CI, S, CO);
input A;
input B;
input CI;
output S;
output CO;
xor g0(S, A, B, CI);
and g1(w3, A, B);
or g2(w8, A, B);
and g3(w6, CI, w8);
or g4(CO, w3, w6);
endmodule
// 1-bit Full Adder
module JFAD1A(A, B, CI, S, CO);
input A;
input B;
input CI;
output S;
output CO;
xor g0(S, A, B, CI);
and g1(w3, A, B);
or g2(w8, A, B);
and g3(w6, CI, w8);
or g4(CO, w3, w6);
endmodule
// 1-bit Full Adder
module JFAD1C(A, B, CI, S, CO);
input A;
input B;
input CI;
output S;
output CO;
xor g0(S, A, B, CI);
and g1(w3, A, B);
or g2(w8, A, B);
and g3(w6, CI, w8);
or g4(CO, w3, w6);
endmodule
// Hi-speed 1-bit Full Adder
module JFAD1D(A, B, CI, S, CO);
input A;
input B;
input CI;
output S;
output CO;
xor g0(S, A, B, CI);
and g1(w3, A, B);
or g2(w8, A, B);
and g3(w6, CI, w8);
or g4(CO, w3, w6);
endmodule
// 2-bit Full Adder
module JFAD2A(A1, A2, B1, B2, CI, S1, S2, CO);
input A1;
input A2;
input B1;
input B2;
input CI;
output S1;
output S2;
output CO;
xor g0(S1, A1, B1, CI);
or g1(w6, A1, B1);
and g2(w4, CI, w6);
and g3(w9, A1, B1);
or g4(w3, w4, w9);
xor g5(S2, w3, A2, B2);
and g6(w14, A2, B2);
or g7(w18, A2, B2);
and g8(w22, A1, B1);
and g9(w25, A1, CI);
and g10(w28, B1, CI);
or g11(w21, w22, w25, w28);
and g12(w17, w18, w21);
or g13(CO, w14, w17);
endmodule
// 2-bit Full Adder
module JFAD2C(A1, A2, B1, B2, CI, S1, S2, CO);
input A1;
input A2;
input B1;
input B2;
input CI;
output S1;
output S2;
output CO;
xor g0(S1, A1, B1, CI);
or g1(w6, A1, B1);
and g2(w4, CI, w6);
and g3(w9, A1, B1);
or g4(w3, w4, w9);
xor g5(S2, w3, A2, B2);
and g6(w16, A1, B1);
and g7(w19, A2, B2);
or g8(w15, w16, w19);
or g9(w22, A2, B2);
and g10(w14, w15, w22);
or g11(w27, A1, B1);
or g12(w30, A2, B2);
and g13(w25, CI, w27, w30);
or g14(CO, w14, w25);
endmodule
// Power Buffer
... (truncated)
module JBUFC(A, O);
input A;
output O;
buf g0(O, A);
endmodule
// Double Power Buffer
module JBUFD(A, O);
input A;
output O;
buf g0(O, A);
endmodule
// Quadruple Power Buffer
module JBUFE(A, O);
input A;
output O;
buf g0(O, A);
endmodule
// Delay Buffer
... (truncated)
module JBUFDA(A, O);
input A;
output O;
buf g0(O, A);
endmodule
// Standard Inverter
module JINVA(A, O);
input A; // this is the input
output O;
not g0(O, A);
endmodule
// Power Inverter
module JINVB(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Double Power Inverter
module JINVC(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Triple Power Inverter
module JINVD(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Quadruple Power Inverter
module JINVE(A, O);
input A;
output O;
not g0(O, A);
endmodule
// 2-1 AOI
module JD21A(A1, A2, B, O);
input A1;
input A2;
input B;
output O;
and g0(w0, A1, A2);
nor g1(O, w0, B);
endmodule
// 2-2 AOI
module JD22A(A1, A2, B1, B2, O);
input A1;
input A2;
input B1;
input B2;
output O;
and g0(w0, A1, A2);
and g1(w3, B1, B2);
nor g2(O, w0, w3);
endmodule
// 2-1-1 AOI
module JD211A(A1, A2, B1, B2, O);
input A1;
input A2;
input B1;
input B2;
output O;
and g0(w0, A1, A2);
nor g1(O, w0, B1, B2);
endmodule
// 2&1-1 AOI
module JD121A(A1, A2, B, C, O);
input A1;
input A2;
input B;
input C;
output O;
or g0(w1, A1, A2);
and g1(w0, w1, B);
nor g2(O, w0, C);
endmodule
// 3-1 AOI
module JD31A(A1, A2, A3, B, O);
input A1;
input A2;
input A3;
input B;
output O;
and g0(w0, A1, A2, A3);
nor g1(O, w0, B);
endmodule
// 2-3 AOI
module JD23A(A1, A2, B1, B2, B3, O);
input A1;
input A2;
input B1;
input B2;
input B3;
output O;
and g0(w0, A1, A2);
and g1(w3, B1, B2, B3);
nor g2(O, w0, w3);
endmodule
// 2-2-1 AOI
module JD122A(A1, A2, B1, B2, C, O);
input A1;
input A2;
input B1;
input B2;
input C;
output O;
and g0(w0, A1, A2);
and g1(w3, B1, B2);
nor g2(O, w0, w3, C);
endmodule
// 2-1-1-1 AOI
module JD2111A(A1, A2, B1, B2, B3, O);
input A1;
input A2;
input B1;
input B2;
input B3;
output O;
and g0(w0, A1, A2);
nor g1(O, w0, B1, B2, B3);
endmodule
// 3-3 AOI
module JD33A(A1, A2, A3, B1, B2, B3, O);
input A1;
input A2;
input A3;
input B1;
input B2;
input B3;
output O;
and g0(w0, A1, A2, A3);
and g1(w4, B1, B2, B3);
nor g2(O, w0, w4);
endmodule
// Power 3-3 AOI
module JD33B(A1, A2, A3, B1, B2, B3, O);
input A1;
input A2;
input A3;
input B1;
input B2;
input B3;
output O;
and g0(w0, A1, A2, A3);
and g1(w4, B1, B2, B3);
nor g2(O, w0, w4);
endmodule
// 2-2-2 AOI
module JD222A(A1, A2, B1, B2, C1, C2, O);
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
output O;
and g0(w0, A1, A2);
and g1(w3, B1, B2);
| This page: |
Created: | Thu Aug 19 12:01:10 1999 |
| From: |
../../../sparc_v8/lib/rtl/sc.v
|