/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
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/******************************************************************************/
// @(#)rl_rst_cntl.v 1.8 9/14/93
// Reset Control state machine - instantiated in misc.v
module rl_rst_cntl
(
gclk_phase_bit1,
reset_out,
input_reset_l,
rcc_rst_l,
last_phi,
iu_error,
iu_error_l,
mm_hold_rst,
rcc_clk,
reset_any,
reset_nonwd,
rs_dsbl_clocks,
rs_dsbl_clocks_in,
rs_stop_even,
rs_watchdog,
// add the following for 2.0 reset changes
sw_rst,
en_sw_rst_nonwd,
pci_slave_mode,
en_pci_sw_rst,
pci_rst_pin_in_l,
pci_rst_pin_out_l,
pci_rst_int_l,
ss_scan_mode,
ss_scan_in,
ss_scan_out
) ;
input gclk_phase_bit1
; //import from rl_clk_stop for bug 595 fix
output reset_out
; // To rl_clk_stop, for Bug 562 fix
input input_reset_l
; // Reset input from MACIO
// Input_reset synchronized to 20-MHz free clock, ANDed with ~scan_mode_sync
input rcc_rst_l
;
// Reset input from IU
input iu_error
;
output iu_error_l
; // Half of fix for bug 851
// This indicates that reset should be held active because there is
// memory activity in progress (see bug 806).
input mm_hold_rst
;
// 40-MHz (nominal) clock. Not gated by clock stop, but does have
// scan clock muxed in.
input rcc_clk
;
// This toggles at a 20-MHz rate, to be used as a clock hold
input last_phi
;
// Reset for watchdog-resettable logic - de-asssertion
// synchronized with rcc_clk.
output reset_any
;
// Reset for non-watchdog-resettable logic - de-asssertion
// synchronized with rcc_clk.
output reset_nonwd
;
// This signal is asserted if the most recent reset was a watchdog reset.
output rs_watchdog
;
// Disable clocks to allow reset transitions to propagate.
output rs_dsbl_clocks
;
output rs_dsbl_clocks_in
; // Input to 20-MHz FF
// Stop clocks when rcc_rst_l is de-asserted
output rs_stop_even
;
// add the following for 2.0 reset changes
input sw_rst
;
input en_sw_rst_nonwd
;
input pci_slave_mode
;
input en_pci_sw_rst
;
input pci_rst_pin_in_l
;
output pci_rst_pin_out_l
;
output pci_rst_int_l
;
input ss_scan_mode
;
input ss_scan_in
;
output ss_scan_out
;
/*-------------- end of I/O declarations ------------------*/
// Note: all FF scan-in inputs will be left unconnected. These nets
// will be automatically scan-stitched by back-end tools, and
// explicitly scan-stitched (by pseudo-continuous assigns)
// for stand-alone clk/misc simulation.
// State machine encoding. The two MSBs are used directly
// as {reset_out, rs_dsbl_clocks}, according
// to the following truth table:
//
// Reset
// Dsbl_clocks
// rsm_idle 00
// rsm_err1 00
// rsm_err2 00
// rsm_on1 01
// rsm_on2 11
// rsm_on3 11
// rsm_on4 11
// rsm_rst1 10
// rsm_rst2 10
// rsm_rst3 10
// rsm_rst4 10
// rsm_off1 11
// rsm_off2 01
// rsm_off3 01
// rsm_off4 01
`define rsm_idle 4'b1010
`define rsm_err1 4'b1001
`define rsm_err2 4'b1000
`define rsm_on1 4'b1100
`define rsm_on2 4'b0110
`define rsm_on3 4'b0111
`define rsm_on4 4'b0101
`define rsm_rst1 4'b0000 // This *must* be 0000 (we reset to it)
`define rsm_rst2 4'b0010
`define rsm_rst3 4'b0011
`define rsm_rst4 4'b0001
`define rsm_off1 4'b0100
`define rsm_off2 4'b1110
`define rsm_off3 4'b1111
`define rsm_off4 4'b1101
// add the following two wires for 2.0 reset fixes
wire pci_rst_pin_d1_l
, pci_rst_pin_sync_l
;
// Use this to reset FFs which must transition only on sbclk edges.
// add sw reset to the following
// wire rcc_rst_even_l = ~(~rcc_rst_l & last_phi) ;
wire rcc_rst_even_l
= ~((~rcc_rst_l | sw_rst | ~pci_rst_pin_sync_l &
en_pci_sw_rst ) & last_phi) ;
// rcc_rst_even_l forces the state machine to rsm_rst1, a state where clocks
// are turned on and the reset outputs are asserted.
wire [3:0] rst_state
;
wire [3:0] rst_next_state
=
rst_state_next(rst_state, iu_error, mm_hold_rst, gclk_phase_bit1) ;
Mflipflop_srh_4 rsm_reg(rst_state, rst_next_state,
ss_scan_mode, /*scan-in*/, ~last_phi,
rcc_rst_even_l, rcc_clk) ;
wire reset_out = ~rst_state[3] ;
wire rs_dsbl_clocks = rst_state[2] ;
// The rs_dsbl_clocks output which goes to the clk_cntl state machine
// must be advanced by one 80-MHz cycle to avoid single-cycle 80-MHz
// paths. Generate a signal which is the next-state of rs_dsbl_clocks.
// rl_clk_cntl will sample this in the third quarter of the 20-MHz
// free cycle to create the signal it needs. Since all state machine
// inputs which might cause changes on this signal change only on
// sbclk positive edges, we have 3 80-MHz cycles to set up this signal.
// iu_error and mm_hold_rst should not factor into this - check synopsys.
//
// include sw reset below
// wire rs_dsbl_clocks_in = rst_next_state[2] & rcc_rst_l ;
wire rs_dsbl_clocks_in = rst_next_state[2] & (rcc_rst_l & ~sw_rst & ~
(~pci_rst_pin_sync_l & en_pci_sw_rst)) ;
// add a debounce on the pci reset input pin
Mflipflop_1 pci_rst_sync1(pci_rst_pin_d1_l,pci_rst_pin_in_l,rcc_clk,~last_phi);
Mflipflop_1 pci_rst_sync2(pci_rst_pin_sync_l,pci_rst_pin_d1_l,rcc_clk,~last_phi);
function [3:0] rst_state_next ;
input [3:0] rst_state ;
input iu_error ;
input mm_hold_rst ;
input gclk_phase_bit1; //import for bug 595 fix
begin
// if (~rcc_rst_even_l) rst_state_next = `rsm_rst1 ;
case (rst_state) // synopsys parallel_case
// Normal operating state - stay here until there's an iu_error
`rsm_idle :
rst_state_next = (iu_error ? `rsm_err1 : `rsm_idle) ;
// iu_error has been asserted - do a watchdog reset.
// The IU is not able to reset properly if the MMU or cache
// controllers are busy working on any Ld/St/Fetch accesses
// for the IU (see bug 806). Delay the start of reset_any
// until (sustain_imhold|sustain_dmhold|wrbuf_pend) is
// inactive. We know that no new cache control activity
// will be initiated by the IU from the time we enter rsm_err1
// - the last possible access would be a Ld/St which enters
// the R when the trapped instruction enters the W (iu_error
// is asserted when the trapped instruction enters W).
//
// Ld F D E W R R R R R R R
// trap F D E W W W W W W W
// iu_error = = = = = = = = = = . . .
// mm_hold_rst = = = = =
// rst_state I I I I I E E E E E E O O O O . . .
// 1 1 2 2 2 2 1 1 2 2
// reset_any = = =
//
// We added the rsm_err2 state to avoid dependencies on
// mm_hold_rst in the rsm_err->rsm_on1 transition - that
// would potentially cause timing problems in rs_dsbl_clocks .
`rsm_err1 :
rst_state_next = (mm_hold_rst ? `rsm_err1 : `rsm_err2) ;
`rsm_err2 : rst_state_next = `rsm_on1 ;
// Clocks are disabled during the next four states.
// One clocks-off cycle with reset still de-asserted (to avoid
// races in the destination FFs).
`rsm_on1 : rst_state_next = `rsm_on2 ;
// Take three 20-MHz cycles to assert reset.
`rsm_on2 : rst_state_next = `rsm_on3 ;
`rsm_on3 : rst_state_next = `rsm_on4 ;
`rsm_on4 : rst_state_next = `rsm_rst1 ;
// Assert the reset outputs for four 20-MHz cycles.
// Clocks are enabled during these four states.
// In addition to being the successor of state rsm_on4
// (for synchronous assertion in response to iu_error),
// state rsm_rst1 is where we go whenever rcc_rst_even_l
// is asserted.
/* FIX for bug 595 for div-by-4 and div_by-5 */
// On de-assertion of rcc_rst_even_l, stay in rsm_rst1 until the
// sbclk cycle which ends with an sbclk positive edge
// coincident with a gclk positive edge.
//`rsm_rst1 : rst_state_next = `rsm_rst2 ;
`rsm_rst1 : rst_state_next = gclk_phase_bit1 ? `rsm_rst2 : `rsm_rst1;
/* END OF FIX */
`rsm_rst2 : rst_state_next = `rsm_rst3 ;
`rsm_rst3 : rst_state_next = `rsm_rst4 ;
`rsm_rst4 : rst_state_next = `rsm_off1 ;
// Clocks are disabled during the next four states.
`rsm_off1 : rst_state_next = `rsm_off2 ;
// Wait three 20-MHz cycles as we de-assert the reset outputs.
`rsm_off2 : rst_state_next = `rsm_off3 ;
`rsm_off3 : rst_state_next = `rsm_off4 ;
`rsm_off4 : rst_state_next = `rsm_idle ;
// synopsys translate_off
default : rst_state_next = 'bx ;
// synopsys translate_on
endcase
end
endfunction
// This keeps track of whether the current reset sequence was
// caused by an external reset or by iu_error.
// Reset on rcc_rst_even_l, set when in rsm_err1 state.
Mflipflop_srh wd_ff(rs_watchdog, rs_watchdog|(rst_state==`rsm_err1),
ss_scan_mode, /*scan-in*/, ~last_phi,
rcc_rst_even_l, rcc_clk) ;
// Generate the actual reset outputs.
// Turn off state-machine-generated reset during scan (don't
// gate off the input_reset_l term, or else the chip might
// explode on power-up).
// modify below to add internal sw reset
wire reset_any =
(reset_out & ~ss_scan_mode) | ~input_reset_l ;
wire reset_nonwd =
// (reset_out & ~rs_watchdog & ~ss_scan_mode) | ~input_reset_l ;
// turn on when sw reset and en_sw_rst_nonwd
(reset_out & sw_rst & en_sw_rst_nonwd & ~ss_scan_mode) |
// turn on when not sw reset & ~watchdog OR input reset
// or when pci reset is driving a s/w reset
(reset_out & ~sw_rst & ~rs_watchdog & ~ss_scan_mode) | ~input_reset_l ;
// add the following for 2.0 reset
// only turn on pci reset pin when the pci master and then for input resets
// or sw resets. (watchdogs won't do it.)
// the reset_nonwd must be qualified with ~en_pci_sw_rst or we could get in a
// mode where the pci reset pin is kept on forever and we never get out of reset
wire pci_rst_pin_out_l = ~(~pci_slave_mode & (~input_reset_l | sw_rst |
~en_pci_sw_rst & reset_nonwd));
// turn on internal reset irregardless of pci_slave mode.
// the pci internal reset must respond immediately to input reset or pci
// reset if if enabled.
wire pci_rst_int_l = ~ (~input_reset_l | sw_rst | reset_nonwd |
~pci_rst_pin_in_l & en_pci_sw_rst );
// This signal stops clocks on the rsm_rst1->rsm_rst2 transition when
// rcc_rst_l is de-asserted. Used only when trst is inactive.
// Note that rcc_rst_l does not appear in this equation - that's because
// this signal is used only to set a FF (in rl_clk_stop) which is
// reset by rcc_rst_l.
// Fix for bug 595. Delay assertion of rs_stop_even until rsm_rst2.
// otherwise clock will stop and reset state machine hangs in rsm_rst1
// while waiting to match gclk and sbclk
//wire rs_stop_even = (rst_state==`rsm_rst1) & ~rs_watchdog ;
wire rs_stop_even = (rst_state==`rsm_rst2) & ~rs_watchdog ; //BUG FIX 595
// Half of bug 851 fix
wire iu_error_l = ~iu_error ;
endmodule
This page: |
Created: | Thu Aug 19 12:00:15 1999 |
| From: |
../../../sparc_v8/ssparc/clk_misc/misc/rtl/rl_rst_cntl.v
|