/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
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/* */
/******************************************************************************/
//****************************************************************************
// @(#)misc.v 1.27 9/14/93
// misc.v
//
// Description:
// Miscellaneous SingleSPARC logic. Includes Jtag and part of clock
// control logic
//
//
//
//****************************************************************************
module misc
(
gclk_phase_late_a1,
gclk_1st_phase,
stop_after_0,
stop_after_1,
stop_after_2,
stop_after_3,
stop_after_4,
div_ctl,
next2last_phi,
rcc_clk,
reset_any,
reset_nonwd,
ss_scan_mode,
ss_misc_scan_in,
ss_misc_scan_out,
input_reset_l,
// add the following for 2.0 resets
sw_rst,
en_sw_rst_nonwd,
pci_slave_mode,
en_pci_sw_rst,
pci_rst_pin_in_l,
pci_rst_pin_out_l,
pci_rst_int_l,
iu_error,
iu_error_l,
mm_hold_rst,
mm_event,
iu_event,
ext_event_l,
int_event_l,
rcc_rst_l,
start,
stop,
free_phase_late_a1,
first_phi,
last_phi,
rs_dsbl_clocks_in,
standby_dsbl_sysclk_a1,
standby_dsbl_tlb,
standby_req,
standby,
pcic_idle,
memif_idle,
ic_standby_f,
dc_standby_w,
logic_0,
logic_1
);
input [1:0] gclk_phase_late_a1
;
output gclk_1st_phase
;
input standby
;
input pcic_idle
;
output standby_req
;
input memif_idle
;
input ic_standby_f
;
input dc_standby_w
;
output standby_dsbl_sysclk_a1
;
output standby_dsbl_tlb
;
output stop_after_0
;
output stop_after_1
;
output stop_after_2
;
output stop_after_3
;
output stop_after_4
;
input [1:0] div_ctl
;
output next2last_phi
;
input rcc_rst_l
;
output start
;
output stop
;
input [2:0] free_phase_late_a1
;
output first_phi
;
output last_phi
;
output rs_dsbl_clocks_in
;
input rcc_clk
; // buffered version of rcc_clk_unbuf
// with skew matched to ss_clock
output reset_any
; // reset to internal blocks
output reset_nonwd
; // reset to internal blocks
input ss_scan_mode
; // Scan enable
output ss_misc_scan_out
;
input ss_misc_scan_in
;
input input_reset_l
; // input reset from MACIO
// add the following for 2.0 reset cleanup
input sw_rst
;
input en_sw_rst_nonwd
;
input pci_slave_mode
;
input en_pci_sw_rst
;
input pci_rst_pin_in_l
;
output pci_rst_pin_out_l
;
output pci_rst_int_l
;
input iu_error
; // error mode from IU
output iu_error_l
;
input mm_hold_rst
;
input mm_event
;
input iu_event
;
input ext_event_l
;
output int_event_l
;
output logic_0
, logic_1
; // Constants, generated within this module
// Avoid warnings on nets to be scan-stitched
wire rst_scan_in
, clk_scan_in
, rst_scan_out
, clk_scan_out
,
ctr_scan_in
, ctr_scan_out
, ss_misc_scan_out ;
rl_rst_cntl rst_cntl(
.gclk_phase_bit1 (gclk_phase_bit1
), //import for 595 bug fix
.reset_out (reset_out
),
.input_reset_l (input_reset_l),
.rcc_rst_l (rcc_rst_l),
.iu_error (iu_error),
.iu_error_l (iu_error_l),
.mm_hold_rst (mm_hold_rst),
.rcc_clk (rcc_clk),
.last_phi (last_phi),
.reset_any (reset_any),
.reset_nonwd (reset_nonwd),
.rs_dsbl_clocks (rs_dsbl_clocks
),
.rs_dsbl_clocks_in (rs_dsbl_clocks_in),
.rs_watchdog (rs_watchdog
),
.rs_stop_even (rs_stop_even
),
// add the following for 2.0 reset changes
.sw_rst (sw_rst),
.en_sw_rst_nonwd(en_sw_rst_nonwd),
.pci_slave_mode (pci_slave_mode),
.en_pci_sw_rst (en_pci_sw_rst),
.pci_rst_pin_in_l (pci_rst_pin_in_l),
.pci_rst_pin_out_l(pci_rst_pin_out_l),
.pci_rst_int_l (pci_rst_int_l),
.ss_scan_mode (ss_scan_mode),
.ss_scan_in (rst_scan_in),
.ss_scan_out (rst_scan_out)
) ;
rl_clk_stop clk_stop(
.gclk_phase_bit1 (gclk_phase_bit1), //export for 595 bug fix
.reset_out (reset_out),
.mm_hold_rst (mm_hold_rst),
.gclk_1st_phase (gclk_1st_phase),
.gclk_phase_late_a1 (gclk_phase_late_a1[1:0]),
.hold_count (hold_count
),
.rcc_rst_even_l (rcc_rst_even_l
),
.standby_dsbl_sysclk_a1 (standby_dsbl_sysclk_a1),
.standby_dsbl_tlb (standby_dsbl_tlb),
.standby_req (standby_req),
.standby (standby),
.pcic_idle (pcic_idle),
.memif_idle (memif_idle),
.ic_standby_f (ic_standby_f),
.dc_standby_w (dc_standby_w),
.terminal_count_l (terminal_count_l
),
.ext_event_l (ext_event_l),
.int_event_l (int_event_l),
.mm_event (mm_event),
.iu_event (iu_event),
.rcc_clk (rcc_clk),
.free_phase_late_a1 (free_phase_late_a1[2:0]),
.stop_after_0 (stop_after_0),
.stop_after_1 (stop_after_1),
.stop_after_2 (stop_after_2),
.stop_after_3 (stop_after_3),
.stop_after_4 (stop_after_4),
.first_phi (first_phi),
.last_phi (last_phi),
.next2last_phi (next2last_phi),
.div_ctl (div_ctl[1:0]),
.start (start),
.stop (stop),
.rs_stop_even (rs_stop_even),
.rs_dsbl_clocks (rs_dsbl_clocks),
.reset_nonwd (reset_nonwd),
.rcc_rst_l (rcc_rst_l),
.ss_scan_mode (ss_scan_mode),
.ss_scan_in (clk_scan_in),
.ss_scan_out (clk_scan_out),
.logic_0 (logic_0),
.logic_1 (logic_1)
) ;
rl_cyc_ctr cyc_ctr (
.terminal_count_l (terminal_count_l),
.hold_count (hold_count),
.rcc_rst_even_l (rcc_rst_even_l),
.ss_scan_mode (ss_scan_mode),
.ss_scan_in (ctr_scan_in),
.ss_scan_out (ctr_scan_out),
.rcc_clk (rcc_clk)
) ;
// Spare flipflops - put them here so we can accurately model the
// scan chain for jtag_test
// synopsys translate_off
ASFFRHA __spare_gate_ff_0_g2_v12_0_s112(
.D (1'b0),
.H (1'b0),
.R (1'b0),
.SM (ss_scan_mode),
.CK (rcc_clk)
) ;
ASFFRHA __spare_gate_ff_0_g1_v12_0_s108(
.D (1'b0),
.H (1'b0),
.R (1'b0),
.SM (ss_scan_mode),
.CK (rcc_clk)
) ;
// synopsys translate_on
endmodule
This page: |
Created: | Thu Aug 19 11:59:55 1999 |
| From: |
../../../sparc_v8/ssparc/clk_misc/misc/rtl/misc.v
|