Other Applications 

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Summaries

This application note discusses methodology and optimization settings for Leonardo, Alliance Series and ModelSim when targeting all Xilinx devices.  The intent of this app note is to present a single methodology that works, not to exhaustively explore all the different options in the toolsets.

This application note is intended to assist designers who are using Synplicity and Xilinx to design a high density FPGA (100K gates).  Phase I describes synthesis-specific techniques and Phase II describes implementation-specific (place and route) techniques for optimizing a design for speed.

This application note describes the functionality and integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e.g. low pass) and a sample rate of 5.44 mega-samples per second or 784 MIPS using an XC4000-4 device. The application note also describes how to set the coefficients of the FIR Filter to meet the needs of other applications.

This technical paper discusses optimization techniques of digital signal processing algorithms into FPGAs. FPGAs offer both price and performance advantages over traditional off-the-shelf DSP solutions.

This paper discusses the benefits of using programmable logic in Digital Signal Processing (DSP) applications. Two case studies - a 16-tap, 8-bit fixed-point FIR filter and a 24-bit Viterbi decoder - demonstrate the advantages of using programmable logic. The summary includes general information on how to decide if programmable logic is best for your DSP application.

FPGAs have become a competitive alternative for high-performance DSP applications, previously dominated by general-purpose DSP and ASIC devices. This paper describes the benefits of using an FPGA as a DSP Co-processor, as well as a stand-alone DSP Engine. Two case studies, a Viterbi Decoder Co-processor and a 16-Tap FIR Filter, are used to illustrate how the FPGA can radically accelerate system performance and reduce component count in a DSP application. Finally, different implementation techniques for reducing hardware requirements and increasing performance are described in detail.

The implementation of digital filters with sample rates above just a few MHz are generally difficult and expensive to realize using standard digital signal processors. At this point the potential of distributed arithmetic and parallel processing performed in a Xilinx FPGA becomes the ideal solution. The re-programmable aspect of FPGAs permits optimum use of the available gates in the form of Constant (K) Coefficient Multipliers (KCMs), while enabling the filter to be tuned or changed at any time. Filters employing fully parallel KCMs are ideal for sample rates exceeding 27 MHz with the example able to operate above 50 MHz. This paper identifies the implementation of a Finite Impulse Response Filter using constant (k) coefficient multipliers in the XC4000E.

This paper introduces the Xilinx Field Programmable Gate Array (FPGA) technology and helps you understand how FPGAs can be used for DSP system implementation. You will find a comparison of the implementation of a simple DSP function in both Programmable DSP (pDSP) and Gate Array technology. A brief explanation of Gate Array technology is followed by a description of Xilinx FPGA technology.

This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may evoke a "so what" response. Its speed will be compared to the more standard single-chip DSP design. We propose to compare Xilinx FPGA performance with an exhaustive list of DSP devices. The test benchmark, established in 1995, is the execution time of a 256-point FFT. The speed in the FPGA design is set by the computation time of the radix 2 butterfly. For 16-bit data and a 50 MHz system clock the computation time indicated is 320 ns. The number of butterfly computations ((N/2)log₂N) for a 256-point FFT is: 
(256/2)log₂ 256 = 128 x 8 = 1024

This paper discusses the use of Distributed Arithmetic to build faster FIR Filters in FPGAs and compares the performance to other off-the-shelf devices, including the Harris HSP43881. The candidate for this speed challenge is the symmetrical FIR filter; specifically, a programmable 8-tap filter with 8 bits of both coefficient and data values. It is programmable in the sense that its gate resources can be configured to do other tasks. Our adversary is the fixed-point "DSP" chip which, in single precision, processes 16-bit words.

In this document the Distributed Arithmetic algorithm is derived and examples are offered that illustrate its effectiveness in producing gate-efficient designs. Distributed Arithmetic plays a key role in embedding DSP functions in the Xilinx XC4000 family of FPGA devices.

This Application Note describes a Plug and Play ISA interface reference design using a Xilinx XC4003, or larger, FPGA device. This design implements the features used in a majority of Plug and Play designs but does not implement every option available within the Plug and Play specification.

An application note and design files for a microcontroller with dynamic bus sizing. Uses Xilinx LogiBLOX. VIEWlogic design files and a QBASIC-based assembler are available.

An application note and design files for building a pulse-width modulation circuit in Xilinx programmable logic. Uses Xilinx LogiBLOX. VIEWlogic design files are available.

This design is the result of a collaborative effort between C-Cube Microsystems, Auravision Corporation (Fremont, CA), Xilinx, and Ring Zero Systems (San Mateo, CA). The design is a Motion-JPEG video codec for ISA bus PC platforms based on the CL550 JPEG, which features a direct hardware interface to the Auravision VxP500 Video Processor.

This manual provides a general overview of designing FPGAs with HDLs. It includes design hints for the novice HDL user, as well as for the experienced user who is designing FPGAs for the first time. Written for the Xilinx M1 development tools.

A Synopsys-specific version of the generic Synthesis and Simulation Design Guide.  Written for the Xilinx M1 development tools.

A supplement to the  Xilinx Macro Library Guide describing the new and different macros available within the XC5200 design library.

This application note describes how to configure an SRAM-based FPGA over a processor bus. It also illustrates the source code required to download a configuration bitstream using an IBM PC as a host microprocessor. 'C' source code is provided. Useful in reconfigurable computing applications.

This document describes the procedures necessary to program Xilinx XC9500 CPLD designs in an HP 3070 test environment.

This document describes the procedures necessary to program Xilinx XC9500 CPLD designs in a GenRad test environment.