|
|
|
|
|
|
Xilinx Answer #6104 : 2.1i JTAG Programmer - Programming via JTAG, DONE goes high but registers not responding
Xilinx Answer #6074 : M1.5iSP2 : XC4000XV net delays changed in the new speed files.
Xilinx Answer #5398 : FPGA: Can I drive an IO when there is no power to the device?
Xilinx Answer #4750 : XC4000xv bitstream information. (number of frames, bits per frame)
Xilinx Answer #4585 : Recommended replacement parts for discontinued XC4000A parts
Xilinx Answer #3631 : FPGA Configuration: Unconnected MODE pins may result in failed configuration for 4000/X devices
Xilinx Answer #3393 : Hardwire: What package are available in Hardwire for FPGA?
Xilinx Answer #3283 : XC4000XL/XV: XV vs XL Architectural Differences
Xilinx Answer #2953 : JTAG - Latched instruction in the Test-Logic-Reset state of XC4K/XC5K/XC9K parts
Xilinx Answer #2529 : XC4000E/EX/XL: The 4KE devices are not bitstream compatible to their equivalent 4KEX/XL devices
Xilinx Answer #2527 : XC4000E: Clarification about the IOB diagram specified on the data book
Xilinx Answer #2195 : JTAG - Do Update Latches and Data Registers get reset in Test Logic Reset State?
Xilinx Answer #2026 : Configuration: APM - Can RDY/BSY be used to signal start of configuration instead of INIT?
Xilinx Answer #1836 : The oscillator in the 4000 FPGA is disabled (if OSC4 unused) after configuration.
Xilinx Answer #1787 : 4000EX/XL: Can I use both the Output FF (OFD) and the Output MUX (OMUX2) of an IOB at the same time?
Xilinx Answer #1220 : JTAG - How to 'turn on' jtag circuitry via XDE and EPIC for XC4K/XC5K devices
Xilinx Answer #695 : XC4000H: Input/Output mode defaults for 4000H
Xilinx Answer #508 : XC4000/XC5200: PROGRAM pin designed to ignore glitches <50nS)
Xilinx Answer #499 : XC4000/XC5200: How accurate are the internal oscillators in these devices?
Xilinx Answer #348 : 94 DATA BOOK: P 2-68 incorrectly list 4025 as available in mq208, not in pq223
Xilinx Answer #236 : 94 DATA BOOK: 4010 pinouts missing reference to DOUT page 2-63
Xilinx Answer #214 : 94 DATA BOOK: DATA 4 (I) missing on page 2-43 of 1994 data book
Xilinx Answer #178 : XC4000: What values do rams contain immediately after configuration?
Xilinx Answer #107 : XC4000: Table of Connections To and From BUFGP and BUFGS
Xilinx Answer #103 : XC4000: The Five Configurations of TBUFs
Xilinx Answer #102 : FPGA Configuration: DONE Doesn't Go High; General XC4000 Debugging Hints