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Arithmetic Functions
Signal Integrity
| IBIS models of Virtex devices for use with
some third party simulators |
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IBIS
Models |
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Application Notes
For further information on signal integrity, an on-line source
for information is
Signal Consulting.
Below is a sample of resources regarding signal integrity:
Customer Comments
"The Virtex series is the best of breed not just because of
the advances in I/O technology and DLLs, but in gate density as
well," said Paul Chang, manager of Hardware Design Group at Cisco
Systems. "I'm very impressed with the Virtex SelectI/O and DLL
capabilities that enable us to manage both chip-to-chip
interconnections within a single board, as well as board-to-board
connections via the backplane. From an overall system design, the
Virtex series allows us to get to market quickly without all the
signal integrity issues at the board level. At Cisco, we're excited
about the further enhancements in Virtex-E and look forward to using
Virtex-E in our next generation systems."
Power
Power Estimator
The Virtex Power estimator worksheet estimates power consumption
for a Virtex design before it is downloaded. It considers the design
resource usage, toggle rates, I/O power, and many other factors in
the estimation. The formulas used for calculations in the program
are based on actual test design measurements.
Xilinx provides two versions of the power estimator, an Excel 97
version that works with Microsoft Office 97 software, and a CGI
version for use with web browsers. They are identical in terms of
estimations and data entries.
User Guide
User
License & Worksheets
Configuration/Reconfiguration
Configuration
The flexible Virtex architecture is an array of configurable
logic blocks (CLBs) surrounded by programmable input/output blocks
(IOBs), all interconnected by a rich hierarchy of fast, versatile
routing resources. The abundance of routing resources permits the
Virtex series to accommodate even the largest and most complex
designs. The SRAM-based Virtex FPGAs are customized when loading
configuration data into the internal memory cells. This
configuration data is stored and loaded by a dedicated, drop-in
Xilinx configuration
PROM, stored in system memory and loaded by an embedded
microprocessor, or loaded by a cable using JTAG
programming. When loading with a PROM or microprocessor, designers
choose master-serial, slave-serial, or Select-MAPTM (parallel) mode.
Reconfiguration
Advanced systems employing multiple FPGAs often use an embedded
CPU for system-level operating tasks, including FPGA configuration:
the CPU monitors operation of FPGA subsystems or provides real-time
control; Networking systems may use FPGAs on communications ports;
advanced systems designs exploit the soft FPGA logic to give field
upgradability of hardware; ports can be independently configured
based on network protocol requirements. In many systems, monitoring
of real-time operation of FPGAs is needed. In an ATM switch, for
example, cells passing through a port can be tabulated in an FPGA
and read by a CPU at minute intervals to monitor network ATM cell
traffic. The VirtexSelectMAP (TM) interface enables high-speed
(400MB/s) configuration or partial configuration of the FPGA.
Through a Semaphore mechanism, the SelectMAP port can read and write
to the configured logic, which is the equivalent of microprocessor
peripheral status and control registers. Semaphores rely on Virtex
partial-configuration technology. When combined with
re-configuration of FPGA logic, they let a single Status/Control
register set be visible to the CPU, even as different designs are
loaded into the FPGA.
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