Xilinx Answer #8177 : 2.1i COREGEN, C_IP4: Known Issues in the C

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2.1i COREGEN, C_IP4: Known Issues in the C_IP4 IP Update

Record #8177
Product Family: Software

Product Line: LogiCore

Product Part: Coregen IP Modules

Problem Title:

2.1i COREGEN, C_IP4: Known Issues in the C_IP4 IP Update

Problem Description:
Urgency: standard

General Description:
Known Issues in the C_IP4 IP Update

Solution 1:

VHDL Simulation Analyze Order:
---------------------------------------------------
(Xilinx Solution #6250) has been updated to indicate the order in which
the VHDL behavioral simulation models must be analyzed for this
release.

KNOWN ISSUES:

General:
-------------
1. 2.1i COREGEN: Main core customization GUI can be closed while Register
Options box remains open. (Xilinx Solution #6148)

DA FIR Core
--------------------
Only the Serial Distributed Arithmetic FIR Filter is supported in this version of the DA FIR Filter Core.

FFT Cores: ----------------- 2. 2.1i COREGEN, VIRTEX, FFT: "WARNING: Core vfft16 did not generate product VerilogSim." / Only VHDL simulation support is available for the Virtex FFT modules (Xilinx Solution #8261)

3. 2.1i COREGEN, C_IP4, VIRTEX, FFT: "Generating the core will overwrite the following [xdsp_xxxx.edn] files" when generating more than one FFT (Xilinx Solution #8304)

RAM-Based SHIFT REGISTER Core: ---------------------------------------------------------- 4. 2.1i COREGEN, C_IP4: "FATAL: RPM arrangement for a1/RAM_0/BIT_1 cannot be placed in RPM arrangement for a1/RAM_0 due to resource contention." for RAM-Based Shift Register (Xilinx Solution #8315)

5. 2.1i COREGEN, C_IP4: RAM-based SHIFT REGISTER behavioral model does not
match backannotated simulation when CE = 'X' (Xilinx Solution #8314)

Asynchronous FIFO
-------------------------------
There are two known problems associated with the Verilog behavioral model for the Asynchronous FIFO:

1. 2.1i COREGEN, C_IP4: Virtex ASYNCH FIFO "Port not found" error during Verilog-XL simulation (Xilinx Solution #8372)

2. 2.1 COREGEN, VERILOG: "Too many module instance parameter assignments in
async_fifo_v1.v" (Xilinx Solution #8374)

FIXED:
======

1. The MIF files for the Block and Distributed Memories are now always written out every time these cores are generated. If you wish to regenerate these cores using an XCO file generated using a previous release, you will need to make sure that the "write_mif" parameter is set to "true", otherwise generation using that XCO file will fail.

2. 2.1i COREGEN: Missing MIF file for Virtex Single and Dual Port Block RAM modules (Xilinx Solution #7539)

3. 2.1i COREGEN, C_IP2: Virtex Variable Parallel Multiplier model shows only a 1-cycle latency in Verilog behavioral simulation (Xilinx Solution #8233)

----------------------------------------------------------------------------------------------------
--------------------------------------------
In addition, with the exception of the "Fixed" items noted above, the known issues documented for the C_IP1, C_IP2 and C_IP3 releases still apply, as documented in
(Xilinx Solution #7149), (Xilinx Solution #7395), and (Xilinx Solution #7895), respectively.

End of Record #8177 - Last Modified: 01/31/00 21:40

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