The Configuration Problem Solver
Related Solution Records
The STARTUP sequence has not completed.
Solution 4681: "BitGen M1.5: Startup Clock can be specified by options or read from design."
Solution 3631: "FPGA Configuration: Unconnected MODE Pins may cause FPGAs to not reconfigure."
Solution 158: "FPGA Configuration: DONE goes High but Output never become Active."
Solution 117: "FPGA Configuration: Preparing a bitstream for Peripheral Configuration."
HISTORY
Family:
XC4000X
Mode:
Synchronous Peripheral
DONE:
HIGH
LDC:
LOW
