The Configuration Problem Solver
Related Solution Records
FPGA should be active.
Solution 5024: "FPGA Configuration: DONE is HIgh, device doesn't operate."
Solution 4681: "BitGen M1.5: Startup Clock can be specified by options or read from design."
Solution 2427: "Hardware Debugger: Polarity of Reset signal is active Low."
Solution 1579: "FPGA Configuration: Size of external pulldown needed to create a Logic Low."
HISTORY
Family:
XC4000X
Mode:
Master Serial
DONE:
HIGH
LDC:
LOW
CCLK:
STOP
