The Configuration Problem Solver
Related Solution Records
The STARTUP sequence has not completed.
Solution 4681: "BitGen M1.5: Startup Clock can be specified by options or read from design."
Solution 1579: "FPGA Configuration: Size of external pulldown needed to create a Logic Low."
Solution 158: "FPGA Configuration: DONE goes High but Output never become Active."
HISTORY
Family:
XC4000X
Mode:
Master Serial
DONE:
HIGH
LDC:
LOW
CCLK:
RUN
