RE: [sv-cc] errata 458

Well, yes, one could certainly do that.  My concern is
that I developed my interpretation by analogy with what
we did in the diagram for "32.14 Variables".  In that
diagram, we had the ranges attached only to bit var,
logic var, and array var.  Are you suggesting that we
do it differently for nets, or should we change the
Variables diagram too?

Regards,
Jim Vellenga

--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
---------------------------------------------------------- 
  
 

] -----Original Message-----
] From: Francoise Martinolle 
] Sent: Tuesday, May 03, 2005 11:25 PM
] To: Jim Vellenga; Francoise Martinolle; sv-cc@eda.org
] Subject: RE: [sv-cc] errata 458
] 
]  I looked up draft 5 for that matter and the vpiLeftRange and 
] RighRange are
] off the net
] class which I think is correct. An integer or time net can be 
] considered to
] have
] an implicit range which is implementation defined and a VPI 
] application
] should be 
] able to access it. An packed struct or enum net may have an 
] implicit or explicit range as well. We need to specify is 
] that can return
] the implied implicit
] range.
] The only mistake I see is the double arrow on the leftRange 
] relationship.
] I can make a proposal if we agree on this.
] 
] Francoise
]     '
] 
] -----Original Message-----
] From: Jim Vellenga [mailto:vellenga] 
] Sent: Tuesday, May 03, 2005 4:27 PM
] To: Francoise Martinolle; sv-cc@eda.org
] Subject: RE: [sv-cc] errata 458
] 
] Francoise,
] 
] As you noted, the range iteration is actually correct.
] But there are two mistakes in the vpiLeftRange and 
] vpiRightRange relations.
] Both of them should be coming off of logic net only (and not 
] off of time
] net).  The original proposal (before the first ballot) had it 
] correctly, but
] it got lost in the editing.
] 
] Also, (and the original proposal had this wrong), the 
] vpiLeftRange should
] only have one arrow.
] 
] Regards,
] Jim V.
] 
] --------------------------------------------------------- 
] James H. Vellenga                            978-262-6381 
] Engineering Director                   (FAX) 978-262-6636 
] Cadence Design Systems, Inc.         vellenga@cadence.com 
] 270 Billerica Rd
] Chelmsford, MA 01824-4179
] "We all work with partial information." 
] ---------------------------------------------------------- 
]   
]  
] 
] ] -----Original Message-----
] ] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] ] Behalf Of Francoise Martinolle
] ] Sent: Tuesday, May 03, 2005 1:08 PM
] ] To: sv-cc@eda.org
] ] Subject: [sv-cc] errata 458
] ] 
] ] I responded to errata 458 (added a bug note). There is 
] ] nothing to correct in the diagram 
] ] (see my explanation).
] ]  
] ] Francoise
] ]        '
] ] 
] 
] 
]