RE: [sv-cc] Mantis items against Draft 6 which have not yet been reviewed

Hi Charles and Stu,

Thanks for the reminders on the Mantis reviews.
I reviewed 1865.  It has one minor oversight in I.10.1.2:

   I.10.1.2 Canonical representation of packed arrays
   /*
    * DPI representation of packed arrays.
    * 2-state and 4-state vectors, exactly the same as PLI's avalue/bvalue.
    */
   #ifndef VPI_VECVAL
   #define VPI_VECVAL
   typedef struct vpi_vecval {
   ...

In the above, "struct vpi_vecval" needs to be "struct t_vpi_vecval".

The Mantis item is already in "Editor" state, so I'm not quite
sure what I should do with it.  I'm leaving it alone for now.

Thanks,
Doug


> -----Original Message-----
> From: owner-sv-cc@server.eda.org [mailto:owner-sv-cc@server.eda.org] On Behalf Of Charlie Dawson
> Sent: Thursday, August 14, 2008 9:33 AM
> To: SV-CC
> Subject: [sv-cc] Mantis items against Draft 6 which have not yet been reviewed
> 
> Hi Guys,
> 
> I'm in the P1800 meeting, and I'm getting some flack because we
> haven't reviewed all of the Mantis Items which were implemented
> in draft 6. :-)
> 
> Here is the list:
> 
> Item  Owner    Title
> ----  -------- ---------------------------------------------------
> 2262  Steve D. Missing definition in vpi_user.h for vpiIsProtected
> 2063  Abi      Three minor typos in 36.15, 36.21, and 36.25
> 2009  Chuck    HDL example shown in detail 3 section 36.14 (Refere
> 1898  Bassam   Describe the explicit mapping from assertion system
> 1865  Doug     Inconsistent field definitions for s_vpi_vecval in
> 1570  Ralph    Clarify legality of 'integer' and 'time' as DPI
> 1456  Ralph    Clarify, circumscribe restrictions on use of DPI
> 1385  Chuck    Please document compatibility issues between 1364
> 1367  Abi      Section 27.11 Ports - the port and port bit objects
> 1716  Ralph    Clarify handling of DPI formals/actuals with rand
> 
> Ralph and Doug, can you review your items, or do I need to find
> someone else to review them?  Please let me know.
> 
>    -Chas
> 
> --
> Charles Dawson
> Senior Engineering Manager
> NC-Verilog Team
> Cadence Design Systems, Inc.
> 270 Billerica Road
> Chelmsford, MA  01824
> (978) 262 - 6273
> chas@cadence.com
> 
> 
> --
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