CPLD Hardware & Software Tools: Tips and Techniques
Core Tools
Power Sequencing/Consumption
Pin-Locking
Timing
Hardware Solutions
to view the
PDF files below.
Power Sequencing/Estimation
Solution 2717: How to control Power Consumption
Solution 2146: XC9500: How to place a macrocell/signal in low power mode (LOWPWR) in a CPLD
Solution 2653: Power estimation in 9500 family devices
XC9500: Does Vccint have to be powered up before Vccio?
XC9500 CPLD Power Sequencing
Pin-Locking
Solution 2719: How to control Pinout of a CPLD
Pin Preassigning with XC9500 CPLDs
Core Tools
Solution 1684: XACT-CPLD: How to switch between the XACT9000 software and the XACTstep software without rebooting
Solution 2704: How does CPLD Auto Device Selection Work
Solution 2729: How to Control Logic Optimization in a CPLD
Solution 983: XC9500: How to set FAST slew rate for 9K outputs in PLUSASM and ABEL
Solution 2860: How to read the CPLD report (.RPT) file?
XC9500 design optimization
Timing
Solution 2732: How to control Timing Paths in a CPLD
M1.3/M1.4 CPLD: How to calculate the timing accross a latch in a 9K device
M1, Timing, CPLD: What are negative setup times in CPLD Performance report?
M1.3/M1.4 CPLD: How to create timing simulation netlist in the XNF format
Using the XC9500 Timing model
Hardware Solutions
XC9500: How many outputs can you simultaneously drive at 24 mA?
XC9500: Device Slew Rates (Rise/Fall times) with capacitive loads
XC9500: How are unused I/O pins handled?
XC9500: When can the XC9500 internal IOB pullups be accessed?
XC9500: Maximum Icc by package type< /a>
Typical I/V Characteristics of XC9500 Outputs
Designing with XC9500 CPLDs
Metastability Considerations
PDF files below.