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//  @(#)condmux.v	1.1  4/7/92
//

module CondMux (C,
                CS,
                notReset,
                notAbortNulExc,
                DyadicOprExc,
		notBrTakenMIS,
                notBrTaken);
input [15:0] C;
input [4:0] CS;
input notAbortNulExc,
      DyadicOprExc,
      notReset;
output notBrTakenMIS;
output notBrTaken;

ME_TIEOFF toff (vdd, gnd);

wire [3:0] T;
wire [4:0] CoS;

ME_INVA h_1 (DyadicOprExc, notDyadicOprExc);
ME_AND3_B h_0 (notAbortNulExc, notReset,
             notDyadicOprExc,
             notPreventBr);

ME_AND2_B c_0(CS[0], notPreventBr, CoS[0]);
ME_AND2_B c_1(CS[1], notPreventBr, CoS[1]);
ME_AND2   c_2(CS[2], notPreventBr, CoS[2]);
ME_AND2   c_3(CS[3], notPreventBr, CoS[3]);
ME_AND2   c_4(CS[4], notPreventBr, CoS[4]);

// C[15] takes different route
ME_MUX4B vx_3 (CoS[0], CoS[1], C[12],C[13],C[14],gnd,  T[3]);
ME_MUX4B vx_2 (CoS[0], CoS[1], C[8],C[9],C[10],C[11],   T[2]);
ME_MUX8B vx_0 (CoS[0], CoS[1], CoS[2], C[0],C[1],C[2],C[3],C[4],C[5],C[6],C[7],C0_7);

ME_NMUX2B vc_1 (CoS[3],  C0_7, T[3],     notC0_11);
ME_XOR2_B vd_0 (notC0_11, CoS[4], notBrTakenNoFrac);

ME_INVA vc_2 (CoS[2], notCoS2);
ME_NAND2 vc_3 (notCoS2, CoS[3], notSelFracConds);
ME_NMUX2B vc_4 (notSelFracConds, T[2], notBrTakenNoFrac,
                BrTakenSlowRC);

// Make a special case of RoundingCondition CoS = {1, 1, 1, 1, 1} ie invert not Rounding condition

ME_AND4   sp_0 (CoS[0], CoS[1], CoS[2], CoS[3], RCSelected);
ME_AND2   sp_1 (CoS[4], RCSelected, ControlForRCPos);

ME_NMUX2B_B sp_2 (ControlForRCPos, BrTakenSlowRC, C[15], notBrTaken);
ME_NMUX2B_B sp_3 (ControlForRCPos, BrTakenSlowRC, C[15], notBrTakenMIS);

endmodule