/***************************************************************************
****************************************************************************
***
*** Program File: @(#)dcc_bp.vpp
***
***
****************************************************************************
****************************************************************************/
/*
This contains IU-specific code to support dcc and the PC breakpoints.
*/
module Mdcc_bp
() ;
// These define the sampling used by dcc_instr.
wire [7:0] instr_byte0
, instr_byte1
, instr_byte2
, instr_byte3
, instr_byte4
,
instr_byte5
, instr_byte6
, instr_byte7
, instr_byte8
, instr_byte9
,
instr_byte10
, instr_byte11
, instr_byte12
, instr_byte13
,
instr_byte14
, instr_byte15
, instr_byte16
,
instr_byte17
, instr_byte18
, instr_byte19
,
instr_byte20
, instr_byte21
, instr_byte22
,
instr_byte23
, instr_byte24
, instr_byte25
, instr_byte26
,
instr_byte27
, instr_byte28
;
// Signal which tells us when iu.iuchip.pc.dpc belongs to a valid first flow.
// Used for PC breakpoints.
wire fpc_valid
= `IU.iuchip.decode.iu_fetch_f ;
wire dpc_valid
= (
// Not valid if IU is held
!`IU.iuchip.hold
// Not valid if it will send a nop or trap into E-cycle
&& !`IU.iuchip.decode.ir_control.hnoptrap_into_ex
// Not valid if a Help flow
&& !`IU.iuchip.decode.ir_control.d_hhn[2]
) ;
wire epc_valid
= (
// Not valid if IU is held
!`IU.iuchip.hold
// Not valid if a Help flow
&& !`IU.iuchip.decode.ir_control.e_hhn[2]
) ;
wire wpc_valid
= (
// Not valid if IU is held
!`IU.iuchip.hold
// Not valid if a Help flow
&& !`IU.iuchip.decode.ir_control.w_hhn[2]
) ;
wire rpc_valid
= (
// Not valid if IU is held
!`IU.iuchip.hold
// Not valid if a Help flow
&& !`IU.iuchip.decode.ir_control.r_hhn[2]
) ;
function fpc_break ;
input [31:0] adr ;
fpc_break =
(adr[31:2] == `IU.iuchip.pc.car[31:2]) && fpc_valid ;
endfunction
function dpc_break ;
input [31:0] adr ;
dpc_break = (adr[31:2] == `IU.iuchip.pc.dpc[31:2]) && dpc_valid ;
endfunction
function epc_break ;
input [31:0] adr ;
epc_break = (adr[31:2] == `IU.iuchip.pc.epc[31:2]) && epc_valid ;
endfunction
function wpc_break ;
input [31:0] adr ;
wpc_break = (adr[31:2] == `IU.iuchip.pc.wpc[31:2]) && wpc_valid ;
endfunction
function rpc_break ;
input [31:0] adr ;
rpc_break = (adr[31:2] == `IU.iuchip.pc.tpc[31:2]) && rpc_valid ;
endfunction
//---------------------------------------------------------------------
wire [31:0] f_is
, a_iseq
, d_iseq
, d_iseq_a1
, df_iseq_a1
,
fe_iseq
, fo_iseq
, be_iseq
, bo_iseq
, ice_iseq
, ico_iseq
,
q1_iseq
, q2_iseq
, q3_iseq
, q4_iseq
, df_iseq
, ef_iseq
, o_iseq
, of_iseq
;
wire [31:0] d_seq
, e_seq
, w_seq
, r_seq
;
wire target_g
=
`IU.iuchip.decode.pc_cntl.sadr_aa
| `IU.iuchip.decode.sadr_jmprett
;
Mflipflop tf_reg (
target_f
, target_g,
Msystem
.clock, `IU.iuchip.hold
) ;
// This signal means that the IU is accepting a doubleword of ICache
// data. The next access gets a new sequence number.
wire use_ic_data
=
`SSPARC_CORE.cc.ic_cntl.fetch_f & ~`IU.iuchip.hold_control.hold_ic & (
`IU.iuchip.hold
// If pipe is held, instr can go into Backup reg (unless
// queue is full).
? (~`IU.iuchip.decode.pc_cntl.hld_backup
& `IU.iuchip.decode.pc_cntl.load_q)
// If pipe is not held, instr goes into pipe or into queue.
// 'take_icdata' is the mux select for ic_ibus/backup.
: (`IU.iuchip.decode.pc_cntl.take_icdata
& (`IU.iuchip.decode.pc_cntl.fetch_ic
| `IU.iuchip.decode.pc_cntl.load_q)
)
) ;
wire fetch_odd
= `SSPARC_CORE.cc.ic_cntl.fetch_f ;
// Whoops - can't really tell when we're fetching an odd address.
wire fetch_even
= fetch_odd ;
Mflipflop_rh_32 fis_reg (f_is, (f_is + fetch_odd + fetch_even),
~use_ic_data, ~`IU.iuchip.reset, Msystem.clock
) ;
assign fe_iseq = fetch_even ? f_is : 'bx ;
assign fo_iseq = fetch_odd ? (f_is+fetch_even) : 'bx ;
Mflipflop_h_32 beis_reg ( be_iseq, fe_iseq,
`IU.iuchip.decode.pc_cntl.hld_backup, Msystem.clock) ;
Mflipflop_h_32 bois_reg ( bo_iseq, fo_iseq,
`IU.iuchip.decode.pc_cntl.hld_backup, Msystem.clock) ;
Mflipflop_h_32 ais_reg ( a_iseq,
(`IU.iuchip.decode.pc_cntl.toq_2_alt ? q1_iseq : 'bx
),
`IU.iuchip.queue.hold_alt, Msystem.clock) ;
Mflipflop_h_32 q4is_reg ( q4_iseq,
(`IU.iuchip.decode.pc_cntl.nq_state<16) ? 'bx : ico_iseq,
`IU.iuchip.queue.hold_q4_real, Msystem.clock) ;
Mflipflop_h_32 q3is_reg ( q3_iseq,
(`IU.iuchip.decode.pc_cntl.nq_state<8) ? 'bx : (
`IU.iuchip.decode.pc_cntl.sel_even3 ? ice_iseq : (
`IU.iuchip.decode.pc_cntl.sel_odd3 ? ico_iseq : (
`IU.iuchip.decode.pc_cntl.sel_shift3 ? q4_iseq : (
'bx)))),
`IU.iuchip.queue.hold_q3_real, Msystem.clock) ;
Mflipflop_h_32 q2is_reg ( q2_iseq,
(`IU.iuchip.decode.pc_cntl.nq_state<4) ? 'bx : (
`IU.iuchip.decode.pc_cntl.sel_even2 ? ice_iseq : (
`IU.iuchip.decode.pc_cntl.sel_odd2 ? ico_iseq : (
`IU.iuchip.decode.pc_cntl.sel_fold2 ? q4_iseq : (
`IU.iuchip.decode.pc_cntl.sel_shift2 ? q3_iseq : (
'bx))))),
`IU.iuchip.queue.hold_q2_real, Msystem.clock) ;
assign ice_iseq =
`IU.iuchip.decode.pc_cntl.take_icdata ? fe_iseq : be_iseq ;
assign ico_iseq =
`IU.iuchip.decode.pc_cntl.take_icdata ? fo_iseq : bo_iseq ;
Mflipflop_h_32 q1is_reg ( q1_iseq,
(`IU.iuchip.decode.pc_cntl.nq_state<2) ? 'bx : (
`IU.iuchip.decode.pc_cntl.sel_even1 ? ice_iseq : (
`IU.iuchip.decode.pc_cntl.sel_odd1 ? ico_iseq : (
`IU.iuchip.decode.pc_cntl.sel_fold1 ? q3_iseq : (
`IU.iuchip.decode.pc_cntl.sel_shift1 ? q2_iseq : (
'bx))))),
`IU.iuchip.queue.hold_q1_real, Msystem.clock) ;
// Selection of D-stage input
assign d_iseq_a1 =
`IU.iuchip.decode.pc_cntl.fetch_ic_even ? ice_iseq : (
`IU.iuchip.decode.pc_cntl.fetch_ic_odd ? ico_iseq : (
`IU.iuchip.decode.pc_cntl.fetch_TOQ ? q1_iseq : (
`IU.iuchip.decode.pc_cntl.fetch_SIQ ? q2_iseq : (
`IU.iuchip.decode.pc_cntl.fetch_alt ? a_iseq : (
`IU.iuchip.decode.pc_cntl.cant_unload ? o_iseq : (
'bx )))))) ;
assign df_iseq_a1 =
`IU.iuchip.decode.pc_cntl.can_fold
? (`IU.iuchip.decode.pc_cntl.cant_unload ? of_iseq : q1_iseq)
: 'bx ;
Mflipflop_h_32 dis_reg ( d_iseq, d_iseq_a1,
`IU.iuchip.queue.hld_dirreg_real, Msystem.clock) ;
Mflipflop_h_32 dfis_reg ( df_iseq, df_iseq_a1,
`IU.iuchip.decode.pc_cntl.hold_br1, Msystem.clock) ;
Mflipflop_h_32 oops_reg ( o_iseq,
(`IU.iuchip.decode.hld_dirreg ? d_iseq_a1 : 'bx),
`IU.iuchip.queue.hld_dir2_real, Msystem.clock) ;
Mflipflop_h_32 oops_f_reg ( of_iseq,
(`IU.iuchip.decode.hld_dirreg ? df_iseq_a1 : 'bx),
`IU.iuchip.queue.hld_dir2_real, Msystem.clock) ;
Mflipflop_h_32 efis_reg ( ef_iseq,
(`IU.iuchip.decode.pc_cntl.nfold_in_e ? df_iseq : 'bx),
`IU.iuchip.decode.pc_cntl.hold, Msystem.clock) ;
// Initialize to X on reset, then initialize to 0 on the first fetched
// instruction.
Mflipflop_h_32 ds_reg (
d_seq,
`IU.iuchip.reset ? 'bx : (
(d_seq==='bx) ? (`IU.iuchip.decode.pc_cntl.fetch_ic ? 0 :'bx ) : (
(`IU.iuchip.decode.d_nop | `IU.iuchip.decode.interlock) ? d_seq : (
d_seq+1))),
`IU.iuchip.hold, Msystem.clock
) ;
Mflipflop_h_32 es_reg (e_seq, d_seq, `IU.iuchip.hold, Msystem.clock) ;
Mflipflop_h_32 ws_reg (w_seq, e_seq, `IU.iuchip.hold, Msystem.clock) ;
Mflipflop_h_32 rs_reg (r_seq, w_seq, `IU.iuchip.hold, Msystem.clock) ;
wire [10:0] d_opcode
=
`IU.iuchip.decode.htrap_into_ex ? ({9'o010 | 9'o400, 2'b00}) :
{
`IU.iuchip.decode.ir_control.d_hhn[2],
`IU.iuchip.decode.ir.in_dec[31:30],
`IU.iuchip.decode.ir.in_dec[24:19],
`IU.iuchip.decode.ir_control.d_hhn[1:0]
} ;
wire [10:0] e_opcode
= {
`IU.iuchip.decode.ir_control.e_hhn[2],
`IU.iuchip.decode.ir.e_op,
`IU.iuchip.decode.ir.e_op3,
`IU.iuchip.decode.ir_control.e_hhn[1:0]
} ;
wire [10:0] w_opcode
= {
`IU.iuchip.decode.ir_control.w_hhn[2],
`IU.iuchip.decode.ir.w_op,
`IU.iuchip.decode.ir.w_op3,
`IU.iuchip.decode.ir_control.w_hhn[1:0]
} ;
wire [10:0] r_opcode
= {
`IU.iuchip.decode.ir_control.r_hhn[2],
`IU.iuchip.decode.ir.r_op,
`IU.iuchip.decode.ir.r_op3,
`IU.iuchip.decode.ir_control.r_hhn[1:0]
} ;
wire d_nop = (d_opcode==({9'o000 | 9'o400, 2'b00})) ;
wire e_nop
= (e_opcode==({9'o000 | 9'o400, 2'b00})) ;
wire w_nop
= (w_opcode==({9'o000 | 9'o400, 2'b00})) ;
wire r_nop
= (r_opcode==({9'o000 | 9'o400, 2'b00})) ;
Mflipflop_rh trap_ff(trap_r
, `IU.TRAP,
`IU.iuchip.hold, ~`IU.iuchip.reset, Msystem.clock) ;
wire start_trap
= `IU.TRAP & ~trap_r ;
// These define the sampling used by dcc_instr
assign instr_byte0 = d_seq ;
assign instr_byte1 = e_seq ;
assign instr_byte2 = w_seq ;
assign instr_byte3 = r_seq ;
assign instr_byte4 = {
`IU.iuchip.decode.interlock,
`IU.iuchip.decode.ANNUL,
start_trap,
`IU.iuchip.hold,
d_nop, e_nop, w_nop, r_nop
} ;
reg [10:0] htrap
; initial htrap
= ({9'o010 | 9'o400, 2'b00}) ;
assign instr_byte5 = {
`IU.iuchip.hold_control.hold_ic,
target_f,
`IU.iuchip.hold_control.dmiss_line |`SSPARC_CORE.dwait_w,
`IU.iuchip.decode.pc_cntl.fetch_alt,
`IU.iuchip.decode.mm_iacc_exc_d,
`IU.iuchip.decode.htrap_into_ex
? {htrap[10], htrap[1:0]}
: `IU.iuchip.decode.ir_control.d_hhn[2:0]
} ;
assign instr_byte6
= `IU.iuchip.decode.htrap_into_ex
? {htrap[9:8], 5'b0, htrap[7]}
: `IU.iuchip.decode.ir.in_dec[31:24] ;
assign instr_byte7
= `IU.iuchip.decode.htrap_into_ex
? {htrap[6:2], 3'b0}
: `IU.iuchip.decode.ir.in_dec[23:16] ;
assign instr_byte8
= `IU.iuchip.decode.htrap_into_ex
? 0
: `IU.iuchip.decode.ir.in_dec[15:8] ;
assign instr_byte9
= `IU.iuchip.decode.htrap_into_ex
? 0
: `IU.iuchip.decode.ir.in_dec[7:0] ;
wire [31:3] iva_f
;
Mflipflop_noop_29 iva_reg(iva_f[31:3], `SSPARC_CORE.iu_iva_g[31:3],
Msystem.clock) ;
assign instr_byte10 = iva_f[31:24] ;
assign instr_byte11 = iva_f[23:16] ;
assign instr_byte12 = iva_f[15:8] ;
assign instr_byte13 = {iva_f[7:3],3'b0} ;
assign instr_byte14 = fe_iseq ;
assign instr_byte15 = fo_iseq ;
wire istream
=
~`SSPARC_CORE.cc.ic_cntl.ic_idle & ~`IU.iuchip.hold_control.hold_ic ;
wire dstream
= ~`SSPARC_CORE.cc.dc_cntl.dcc_idle & ~`SSPARC_CORE.cc.dwait_w
& (~`SSPARC_CORE.cc.enbl_dtag_match_w | `SSPARC_CORE.cc.dt_hit) ;
assign instr_byte16 = {
1'b0, `SSPARC_CORE.dc_shold, dstream, 1'b1, 1'b0, 1'b0, istream, 1'b0
} ;
assign instr_byte17 = d_iseq ;
assign instr_byte18 = a_iseq ;
assign instr_byte19 = q1_iseq ;
assign instr_byte20 = q2_iseq ;
assign instr_byte21 = q3_iseq ;
assign instr_byte22 = q4_iseq ;
assign instr_byte23 = be_iseq ;
assign instr_byte24 = bo_iseq ;
assign instr_byte25 = df_iseq ;
assign instr_byte26 = ef_iseq ;
assign instr_byte27 = o_iseq ;
assign instr_byte28 = of_iseq ;
endmodule
This page: |
Created: | Thu Aug 19 12:02:16 1999 |
| From: |
../../../sparc_v8/env/rtl/dcc_bp.vpp
|