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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)fifo4_next_29.v
***
***  Description:
***    Implements a 4 deep, 29 bit wide fifo with the next read entry viewable.
***    This fifo holds the mapped afx address for presentation to the pci_core.
*** 
****************************************************************************
****************************************************************************/

module fifo4_next_29(	
		reset,			//fifo reset
		clock,			//fifo clock
		data_in,		//data in (variable width)
		read,			//read fifo
		write,			//write fifo

		full_count,		//full count
 		data_out,		// fifo data out
		next_data_out		// fifo data out (rd_ptr +1)
		);
		

// Fifo is 4 entries deep, variable width default is 2 bit

// deviates slightly from the standard fifo in that the full count decrement
// from reads is delayed.  This is to take into consideration the asynch
// nature of reading the entries.  We need to be able to stream reads while
// the "ack" on reads is delayed for full handling.  The decrement signal
// will not be stable until 1/2 way through this clock.

	parameter WIDTH = 28;

input	reset;
input 	clock;
input	[WIDTH:0] data_in;
input   read;
input	write;

output [2:0] full_count;
output [WIDTH:0] data_out;
output [WIDTH:0] next_data_out;


wire [WIDTH:0] reg0,reg1,reg2,reg3;
reg [1:0] wr_ptr, rd_ptr, rd_ptr_plus10;
reg [1:0] rd_ptr0, rd_ptr1, rd_ptr2, rd_ptr_plus11,rd_ptr_plus12;
reg [2:0] full_count;

wire [WIDTH:0] data_out ;
wire [WIDTH:0] next_data_out;

wire spare;
wire spare1;

// read ptr read - ups
MUX4to1_10 MUX0(data_out[9:0],rd_ptr0,reg0[9:0],reg1[9:0],reg2[9:0],reg3[9:0]);

MUX4to1_10 MUX1(data_out[19:10],rd_ptr1,reg0[19:10],reg1[19:10],reg2[19:10],reg3[19:10]);

MUX4to1_10 MUX2({spare,data_out[28:20]},rd_ptr2,{1'b0,reg0[28:20]},{1'b0,reg1[28:20]},{1'b0,reg2[28:20]},{1'b0,reg3[28:20]});

// read ptr read + 1 read - ups
MUX4to1_10 MUX3(next_data_out[9:0],rd_ptr_plus10,reg0[9:0],reg1[9:0],reg2[9:0],reg3[9:0]);

MUX4to1_10 MUX4(next_data_out[19:10],rd_ptr_plus11,reg0[19:10],reg1[19:10],reg2[19:10],reg3[19:10]);

MUX4to1_10 MUX5({spare1,next_data_out[28:20]},rd_ptr_plus12,{1'b0,reg0[28:20]},{1'b0,reg1[28:20]},{1'b0,reg2[28:20]},{1'b0,reg3[28:20]});

// load fifos and increment of read and write pointers

wire load_reg0 = write & (wr_ptr == 2'b00);
wire load_reg1 = write & (wr_ptr == 2'b01);
wire load_reg2 = write & (wr_ptr == 2'b10);
wire load_reg3 = write & (wr_ptr == 2'b11);

REG29 REG0(	.data_out		(reg0),
		.clock			(clock),
		.load_en		(load_reg0),
		.data_in		(data_in));

REG29 REG1(	.data_out		(reg1),
		.clock			(clock),
		.load_en		(load_reg1),
		.data_in		(data_in));

REG29 REG2(	.data_out		(reg2),
		.clock			(clock),
		.load_en		(load_reg2),
		.data_in		(data_in));

REG29 REG3(	.data_out		(reg3),
		.clock			(clock),
		.load_en		(load_reg3),
		.data_in		(data_in));

wire [1:0] rd_ptr_inc = rd_ptr + 2'b01;

wire [1:0] rd_ptr_plus_inc = read ? (rd_ptr_inc + 2'b01) : rd_ptr_inc;

always @(posedge clock)
  begin
    rd_ptr_plus10 <= #1 rd_ptr_plus_inc; 
    rd_ptr_plus11 <= #1 rd_ptr_plus_inc;
    rd_ptr_plus12 <= #1 rd_ptr_plus_inc;
  end

wire [1:0] rd_ptr_in = reset ? 2'b00 : read ? rd_ptr_inc  : rd_ptr;

always @(posedge clock)
begin

  begin
  rd_ptr <= #1 rd_ptr_in;
  rd_ptr0 <= #1 rd_ptr_in;
  rd_ptr1 <= #1 rd_ptr_in;
  rd_ptr2 <= #1 rd_ptr_in;
  end

  
end

wire [1:0] wr_ptr_in = reset ? 2'b00 : write ? (wr_ptr + 2'b01) : wr_ptr;

always @(posedge clock)
begin

  wr_ptr <= #1 wr_ptr_in;
  
end

// generate full_count;  0 at reset
// increment on write and no read
// decrement on read and no write
// holds on either no read, no write OR read and write
always @(posedge clock)
begin

if (reset )
  full_count <= 3'b000;

else if (write & ~read)
  full_count <= #1 (full_count + 3'b001);

else if (~write & read)
  full_count <= #1 (full_count - 3'b001);

end

endmodule