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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)final_adder.v
***
****************************************************************************
****************************************************************************/

//  @(#)final_adder.v	1.2  7/10/92
//
// **************************************************************
//  final_add  -- generate rounded 53-bit mantissa given 54-bit
//		  carry-sum, sticky, and c51.
//
// **************************************************************


module final_adder (
		  mantissa,
		  inexact,
		  frac_ovf,
		  sum,
		  carry,
		  mode,
		  sign,
		  sticky,
		  c51,
		  double_precision
		  );

    output [52:0] mantissa;
    output inexact;
    output frac_ovf;		// fraction overflow (mantissa >= 2.0)

    input  [105:51] sum;	// recoded
    input  [105:52] carry;	// recoded
    input  [1:0] mode;
    input  sign;
    input sticky;
    input c51;
    input double_precision;


    wire [105:54] sum_0, sum_1;
    wire [1:0] select, man_n;

    ME_TIEOFF t1 (, LOW) ;


    adder52
	add52_0 (			// 52-bit dual adder
		 .sum_0( sum_0[105:54] ),
		 .sum_1( sum_1[105:54] ),
		 .x( {carry[105:54]} ),
		 .y( {sum[105:54]} )
		 );

    add2_3
	add2_3 (
		c54,
		{lsb, g, r},
		{carry[53:52], LOW},
		sum[53:51],
		c51
		);

    fpm_round
	round (
	       rnd_n,
	       rnd_v,
	       lsb,
	       g,
	       r,
	       sticky,
	       sign,
	       mode[1:0]
	       );

    man_n
	man_n_0 (
		 man_n[1:0],
		 c54_n,
		 {lsb, g},
		 rnd_n,
		 c54
		 );

    man_v
	man_v_0 (
		 man_v,
		 c54_v,
		 lsb,
		 rnd_v,
		 c54
		 );

    select
	select0 (
		frac_ovf,		// fraction overflow (mantissa >= 2.0)
		select[1:0],
		sum_0[105],
		sum_1[105],
		sum_0[76],
		sum_1[76],
		c54_n,
		c54_v,
		c54,
		double_precision
		);

    inexact
	inexact0 (
	       inexact,
	       select[1],	// final_overflow (after rounding)
	       g,
	       r,
	       sticky
	       );

    ME_MUX41H53
	mux4to1 (
		 mantissa[52:0],
		 {sum_0[104:54], man_n[1:0]},
		 {sum_1[104:54], man_n[1:0]},
		 {sum_0[105:54], man_v},
		 {sum_1[105:54], man_v},
		 select[1:0]
		 );

endmodule