/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
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/* registered trademarks of Sun Microsystems, Inc. in the United States and */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)interface.v
***
****************************************************************************
****************************************************************************/
// @(#)interface.v 1.16 3/17/93
// interface.v
//-----------------------------------------------------------------------------
// INTERFACE logic for input and output signals
module Minterface
( ss_reset, nnreset, nreset, reset,
del_resetm,
iexc_for_int_hi,
mm_iacc_exc_d,
mm_iacc_mmu_miss_d,
mm_iacc_err_tlb_d, mm_iacc_wp_exc_d, parity_error_d,
iacc_exc_mmumiss_d,
this_s, sup_ex_trap,
IRL, int_req_lev, pint_req_lev,
hld_dirreg, hold,
e_asim, alternate_e,
iu_asi_e,
use_ps, s, psm,
ss_clock, ANNUL, d_nop, d_trap
);
input ss_reset
; // asynchronous reset input
output nnreset
; // synchronized version of ss_reset
output nreset
; // synchronized version of nnreset
output reset
; // latched reset
output del_resetm
; // master latched version of reset
//output enbl_fetch; // same as ~reset
input [10:2] iexc_for_int_hi
;
//input mm_iacc_exc; // F cycle mm_iacc_exc
output mm_iacc_exc_d
; // D cycle version
//input mm_iacc_mmu_miss;
output mm_iacc_mmu_miss_d
;
//input mm_iacc_err_tlb;
output mm_iacc_err_tlb_d
;
output mm_iacc_wp_exc_d
;
output parity_error_d
;
output iacc_exc_mmumiss_d
;
output this_s
;
output sup_ex_trap
;
// input nWE; // IU generated write enable control for LSW
input [3:0] IRL
; // Interrupt Request Level Input to IU
output [3:0] int_req_lev
; // Interrupt Request Level (synchronized)
output [3:0] pint_req_lev
; // pipelined version
// input hld_dir; // used to hold mm_iacc_exc_d reg
input hld_dirreg
; // ditto.
input hold
; // main hold
input [5:0] e_asim
; // E state ASI
// input [5:0] w_asim; // W stage ASI
input alternate_e
; // use e_asi
//input alternate_w; // use w_asi
// input normal_asi0; // normal ASI
output [5:0] iu_asi_e
; // Address Space Identifier for E
// output [5:0] iu_asi_w; // Address Space Identifier for W
input use_ps
;
input s
;
input psm
;
input ss_clock
; // system clock
input ANNUL
;
input d_nop
;
input d_trap
;
// input hld_we; // hold control for WE flip-flops
//input SCANMODE; // scan mode
// input ss_scan_mode;
// input SCANDIN; // scan data in
// input BOOT; // pin to control non-arch. mode of chip
// ASI INTERFACE
wire [5:0] asi_e_mux1
= {5'b00101,s};
// Expanded macro begin.
// cmux2(iu_asi_e_mux, 6, iu_asi_e, asi_e_mux1, e_asim[5:0], alternate_e)
function [6:1] iu_asi_e_mux ;
input [6:1] in0_fn ;
input [6:1] in1_fn ;
input select_fn ;
reg [6:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
iu_asi_e_mux = out_fn ;
end
endfunction
assign iu_asi_e = iu_asi_e_mux( asi_e_mux1, e_asim[5:0], alternate_e) ;
// Expanded macro end.
/*
* for tsunami
wire [5:0] asi_e_mux1 = {5'b00101,normal_asi0}; // for tsunami
*/
/*
* mm_iacc_exc interface
*take iexc_for_int_hi bus - holds I$ access status bits.
* [10:9] even/odd parity error (iaer)
* [8] translation error (iaer)
* [7] mmu miss (mmumissexc)
* [6] invalid address error (iexc)
* [5] sbus error (iaer)
* [4] sbus timeout (iaer)
* [3] protection violation (iexc)
* [2] supervisor execute only (iexc)
*
* special encoding of invalid address error and protection
* violation both on indicates a instruction watchpoint trap.
* the MMU will guarantee that only a watchpoint trap can
* turn on the two individual trap lines simultaneously
*/
// register it since signal from mmu is F cycle. need it in D.
// use hld_dir and hld_dirreg to hold this signal. this is
// in the event of a miss, we need to be able to bring in the
// exception status just like we bring in the instruction.
wire this_s;
// Expanded macro begin.
// cmux2(this_s_mux, 1, this_s, s, psm, use_ps)
function [1:1] this_s_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
this_s_mux = out_fn ;
end
endfunction
assign this_s = this_s_mux(s, psm, use_ps) ;
// Expanded macro end.
wire sup_ex_trap = iexc_for_int_hi[2] & ~this_s;
wire nmm_iacc_exc_d
=
iexc_for_int_hi[6] & ~iexc_for_int_hi[3]
// | iexc_for_int_hi[5]
// | iexc_for_int_hi[4]
| iexc_for_int_hi[3] & ~iexc_for_int_hi[6]
| sup_ex_trap
;
wire hld_dirreg_real
= hld_dirreg | hold;
wire mm_iacc_exc_d;
Mflipflop_1 mm_iacc_exc_d_reg_1(mm_iacc_exc_d,nmm_iacc_exc_d, ss_clock,hld_dirreg_real) ;
wire mm_iacc_mmu_miss_d;
Mflipflop_1 mm_iacc_mm_reg_1(mm_iacc_mmu_miss_d,iexc_for_int_hi[7], ss_clock,hld_dirreg_real) ;
wire nmm_iacc_err_tlb_d
=
iexc_for_int_hi[8]
| iexc_for_int_hi[5]
| iexc_for_int_hi[4];
wire mm_iacc_err_tlb_d;
Mflipflop_1 mm_iac_err_tlb_1(mm_iacc_err_tlb_d,nmm_iacc_err_tlb_d, ss_clock,hld_dirreg_real) ;
wire nmm_iacc_wp_exc_d
= iexc_for_int_hi[6] & iexc_for_int_hi[3];
wire mm_iacc_wp_exc_d;
Mflipflop_1 mm_iacc_wp_exc_d_reg_1(mm_iacc_wp_exc_d,nmm_iacc_wp_exc_d, ss_clock,hld_dirreg_real) ;
wire nparity_error_d
= iexc_for_int_hi[10] | iexc_for_int_hi[9];
wire parity_error_d;
Mflipflop_1 parity_error_d_reg_1(parity_error_d,nparity_error_d, ss_clock,hld_dirreg_real) ;
// remove mm_iacc_wp_exc_d since MMU changed the way
// it wants to do iwp traps
wire iacc_exc_mmumiss_d_almost
=
mm_iacc_exc_d | mm_iacc_mmu_miss_d
| mm_iacc_err_tlb_d | parity_error_d
// | mm_iacc_wp_exc_d
;
wire not_stuff2
= ~ANNUL & ~d_nop & ~d_trap;
wire iacc_exc_mmumiss_d =
iacc_exc_mmumiss_d_almost & not_stuff2;
// | trapd_iaer;
/*
* not needed for warthog
// mm_dacc_exc interface
// register it since signal from mmu is W cycle. need it in R.
// use hold_r_reg to hold this register. this is really used
// in the event of a miss, we need to bring the exception status
// in with the data word.
REGWIRE mm_dacc_exc_r;
REG(mm_dacc_exc_r_reg,1,mm_dacc_exc_r,mm_dacc_exc, ss_clock,hold)
REGWIRE mm_dacc_mmu_miss_r;
REG(mm_dacc_mmm_reg,1,mm_dacc_mmu_miss_r,mm_dacc_mmu_miss, ss_clock,hold)
// wire dacc_exc_mmumiss_r = mm_dacc_exc_r | mm_dacc_mmu_miss_r;
// mm_dacc_err interface
// equivalent to mm_dacc_exc interface
REGWIRE mm_dacc_err_r;
REG(mm_dacc_err_r_reg,1,mm_dacc_err_r,mm_dacc_err, ss_clock,hold)
wire ndacc_exc_err_mmumiss_r =
mm_dacc_exc | mm_dacc_mmu_miss
| mm_dacc_err
;
REGWIRE dacc_exc_err_mmumiss_r;
REG(deemm_r_reg,1,dacc_exc_err_mmumiss_r,ndacc_exc_err_mmumiss_r, ss_clock,hold)
*/
// RESET INTERFACE
// NOTE:
// A register module is being used here instead of the macro
// because the macro is not sensitive to data changes, only
// the negative edge of clock and hold. The MregisterD module,
// on the other hand is sensitive to data changes. This is
// necessary because "fb RESET_IN 1" and "fb RESET_IN 0" are
// applied after the negative edges of clock and hold.
wire nnnreset
;
Mflipflop_1 nnnreset_reg_1(nnnreset, ss_reset, ss_clock, 1'b0) ;
// synopsys translate_off
// defparam nnnreset_reg.bits = 1;
// synopsys translate_on
wire nnreset;
Mflipflop_1 nnreset_reg_1( nnreset, nnnreset, ss_clock, 1'b0) ;
wire nreset;
Mflipflop_1 nreset_reg_1( nreset, nnreset, ss_clock, 1'b0) ;
wire reset;
Mflipflop_1 reset_reg_1( reset, nreset, ss_clock, 1'b0) ;
// synopsys translate_off
wire reset_dummy
;
Mflipflop_1 reset_dummy_reg_1(reset_dummy,nreset,ss_clock,1'b0) ;
// synopsys translate_on
wire del_resetm;
Mflipflop_1 del_reset_reg_1( del_resetm, reset, ss_clock, 1'b0) ;
// don't allow fetch when reset is active
// wire enbl_fetch = ~reset & ~picfpc_mismatch;
/*
* Not used anywhere. who did this? me?
REGWIRE verilog_reset;
// Temporary kludge, which doesn't allow hierarchical names like
// Msystem.iu.iuchip.RESET.
#ifdef REGWIRE_IS_WIRE
// synopsyzable version
REG(verilog_reset_reg,1, verilog_reset, ss_reset, ss_clock, 1'b0)
#else
// real design
REG(verilog_reset_reg,1, verilog_reset, `IU.iuchip.ss_reset, ss_clock, 1'b0)
#endif
*/
// IRL Interface
// The IRL is asynchronous and is therefore double-registered
// REGWIRE [3:0] irl1;
// REG(irl_reg1,4, irl1, IRL, ss_clock, 1'b0)
wire [3:0] irl2
;
Mflipflop_4 irl_reg2_4( irl2, IRL, ss_clock, 1'b0) ;
wire [3:0] irl3
;
Mflipflop_4 irl_reg3_4( irl3, irl2, ss_clock, 1'b0) ;
wire [3:0] irlc
=
// synopsys translate_off
((irl2==irl3)===1'bx) ? 'bx :
// synopsys translate_on
irl2==irl3 ? irl3 : 0;
wire [3:0] int_req_lev;
Mflipflop_4 irl_reg4_4( int_req_lev, irlc, ss_clock, hold) ;
wire [3:0] pint_req_lev;
Mflipflop_4 pirl_reg4_4( pint_req_lev, int_req_lev, ss_clock, hold) ;
// SCAN interface
// wire scan_mode; // used to be reg
// DSSLAVE(smode_slv,1, scan_mode, SCANMODE, ss_clock)
// Can't find this reg in Valid drawings.
// reg scan_in;
// REG(extra_bit,1, scan_in, SCANDIN, ss_clock, hold)
endmodule
This page: |
Created: | Thu Aug 19 12:02:45 1999 |
| From: |
../../../sparc_v8/ssparc/iu/Mdecode/rtl/interface.v
|