/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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//
// @(#)Module: mem.v
// @(#)Date/Time: 11/3/93
// @(#)Revision: 1.36
// @(#)D/T LModi: 11/3/93
// ***************************************************************************
// @(#)mem.v 1.36 11/3/93
//
// Description:
//
//
// Created: May 1, 1990
//
// Dependencies:
//
//
// *****************************************************************************
![[Up: rl_mcb mem]](v2html-up.gif)
module MEM_Device_Operating_Environment
();
`define RC_OFF +4'b0001 // Refresh is off
`define RC_0000 +13'd128 // Every 128 clocks
`define RC_0001 +13'd0 // No Refresh
`define RC_0010 +13'd704 // Every 704 clocks
`define RC_0011 +13'd896 // Every 896 clocks
`define RC_0100 +13'd1216 // Every 1216 clocks
`define RC_0101 +13'd5120 // Every 5120 clocks
`define RC_0110 +13'd1408 // Every 1408 clocks
`define RC_0111 +13'd1792 // Every 1792 clocks
`define RC_1XXX +32'hzzzzzzzz // Self-refresh mode
`define SPEED70 +3'b000 // Speed select is 70MHz
`define SPEED85 +3'b001 // Speed select is 85MHz
`define SPEED100 +3'b010 // Speed select is 100MHz
`define SPEED125 +3'b011 // Speed select is 125MHz
`define SPEED150 +3'b100 // Speed select is 150MHz
`define SPEED175 +3'b110 // Speed select is 175MHz
`define SPEED200 +3'b111 // Speed select is 200MHz
`define mc_ras_l `SS_SCOPE.mc_ras_l
`define mc_cas_l `SS_SCOPE.mc_cas_l
`define mc_mwe_l `SS_SCOPE.mc_mwe_l
// IIe note : Moved the definitions of mm_mreq and mm_rf_cntl from defines.v
//`define mc_mbsy `rl_memif.mc_mbsy
`ifdef MEMIF_GATE_LEVEL
`define mc_mbsy `rl_memif.memif_major.mc_mbsy
`define mm_mreq `SSPARC_CORE.memif_major.mm_mreq
`define mm_rf_cntl `SSPARC_CORE.memif_major.mm_rf_cntl
`else
`define mc_mbsy `rl_memif.mc_mbsy
`define mm_mreq `SSPARC_CORE.ssparc_memif.mm_mreq
`define mm_rf_cntl `SSPARC_CORE.ssparc_memif.mm_rf_cntl
`endif
// kwok
`define mm_icstben `SSPARC_CORE.mm_icstben
`define mm_dcstben `SSPARC_CORE.mm_dcstben
`define mm_iostben `MMU_CNTL.marb_sm.mm_iostben
`define ab_14 `SSPARC_CORE.w_ab_out[14]
`define ab_13 `SSPARC_CORE.w_ab_out[13]
//`ifdef MEMIF_GATE_LEVEL
// `define rf_rreq_l `rl_memif.memif_major.rfr_reqgen_ffsr_req_GReg_1_1_Mflipflop_0_0_dff.Q
//`else
// `define rf_rreq_l `rl_memif.memif_major.rfr.rf_rreq_l
//`endif
`ifdef MEMIF_GATE_LEVEL
`define rf_rreq_l `rl_memif.memif_major.rfr_reqgen_ffsr_req_GReg_1_1_Mflipflop_0_0_dff.Q
`else
`define rf_rreq_l `rl_memif.memif_major.rfr.rf_rreq_l
`endif
reg [63:0] datareg;
reg [11:0] adrreg;
reg [1:0] parityreg;
reg [3:0] MREQ_1, MREQ;
reg MWE_L0 ;
reg MM_ISSUE_REQ_0;
reg [3:0] CAS_L_0,
CAS_L_1,
CAS_L_2,
CAS_L_3,
CAS_L_4,
CAS_L_5,
CAS_L_6,
CAS_L_7;
reg [3:0] MM_RF_CNTL_0,
MM_RF_CNTL_1;
reg MM_ICSTBEN;
reg MM_DCSTBEN;
reg MM_IOSTBEN;
integer MBSY_1,MBSY;
integer MMU;
integer RFR;
integer RREQ_L_1, RREQ_L;
integer RESET_REFRESH, RESET_REFRESH_COUNT, RREQ_COUNT;
integer RST; // Added it to know when reset went away (var.) //1:0
integer RAP_CHANN; //31:0
integer MULTI_CHANNEL_DESCRIPTOR; //31:0
integer refresh_rate;
initial
begin :INITIAL_MEMORY_MONITOR
RAP_CHANN = $fopen("monitor.log");
if (RAP_CHANN == +32'h00000000)
$write("\n %0d: ### Warning! mem.v Can't open monitor.log:{%0t}\n",Mclocks.cycle_count,$stime);
else
MULTI_CHANNEL_DESCRIPTOR[31:00] = {RAP_CHANN[31:01], +1'b1};
end
always @(posedge `SS_SCOPE.rfr_clock && `rst)
fork :reset_MEMORY_MONITOR
MBSY_1 = +1'b1;
MBSY = +1'b1;
MMU = +1'b0;
// memory request type
MREQ_1[3:0] = +4'h0;
MREQ[3:0] = +4'h0;
// memory issue request
MM_ISSUE_REQ_0 = +1'b0;
// the refresh count tracking
RFR = +1'b0;
RREQ_L_1 = +1'b0;
RREQ_L = +1'b0;
RESET_REFRESH = +1'b1;
RESET_REFRESH_COUNT = +4'h0;
RREQ_COUNT = +10'd0;
// memory write enable
MWE_L0 = +1'b1;
// the cas lines
CAS_L_7[3:0] = +4'b1111;
CAS_L_6[3:0] = +4'b1111;
CAS_L_5[3:0] = +4'b1111;
CAS_L_4[3:0] = +4'b1111;
CAS_L_3[3:0] = +4'b1111;
CAS_L_2[3:0] = +4'b1111;
CAS_L_1[3:0] = +4'b1111;
CAS_L_0[3:0] = +4'b1111;
MM_RF_CNTL_1[3:0] = +4'b0001;
MM_RF_CNTL_0[3:0] = +4'b0001;
RST[1:0] = +2'b11;
// debug feature lines
MM_ICSTBEN = +1'b1;
MM_DCSTBEN = +1'b1;
MM_IOSTBEN = +1'b1;
join // reset_MEMORY_MONITOR
//
always @(posedge `SS_SCOPE.rfr_clock && !`rst && !`SS_SCOPE.ss_scan_mode && !Mclocks.scan_operation)
begin :ALWAYS_MEMORY_MONITOR
RREQ_COUNT = RREQ_COUNT + +1'b1;
// if asserted the memory is busy
MBSY_1 = MBSY;
MBSY = `mc_mbsy;
MREQ[3:0] = `mm_mreq[3:0];
MM_ISSUE_REQ_0 = `mm_issue_req;
RREQ_L_1 = RREQ_L;
RREQ_L = `rf_rreq_l;
MWE_L0 = `mc_mwe_l;
CAS_L_7[3:0] = CAS_L_6[3:0];
CAS_L_6[3:0] = CAS_L_5[3:0];
CAS_L_5[3:0] = CAS_L_4[3:0];
CAS_L_4[3:0] = CAS_L_3[3:0];
CAS_L_3[3:0] = CAS_L_2[3:0];
CAS_L_2[3:0] = CAS_L_1[3:0];
CAS_L_1[3:0] = CAS_L_0[3:0];
CAS_L_0[3:0] = `mc_cas_l[3:0];
MM_RF_CNTL_1[3:0] = MM_RF_CNTL_0[3:0];
MM_RF_CNTL_0[3:0] = `mm_rf_cntl[3:0];
RST[0] = `rst ;
MM_ICSTBEN = `mm_icstben;
MM_DCSTBEN = `mm_dcstben;
MM_IOSTBEN = `mm_iostben;
/*
Verify memory lines
Sample the data, address and parity lines up to the start of the write
operation (cas and we are enabled). Save that data into a register and
compare the data, parity and address bus to the register values at each
clock, until the write operation is complete.
*/
/*
This happen second, after the registers have been intialized
*/
if (`mc_mwe_l == 0 && `mc_cas_l[3:0] != 'hf)
begin
if (datareg != `BOARD.ssparc.b_memdata)
begin
$display("*** ERROR: data lines changed after cas enabled");
Mclocks.error_count = Mclocks.error_count + 1;
end
if (parityreg != `BOARD.ssparc.b_mempar)
begin
$display("*** ERROR: parity lines changed after cas enabled");
Mclocks.error_count = Mclocks.error_count + 1;
end
if (adrreg != `BOARD.ssparc.mc_memaddr)
begin
$display("*** ERROR: address lines changed after cas enabled");
Mclocks.error_count = Mclocks.error_count + 1;
end
end
/*
This happens first, prior to cas enable - intialize the compare registers
*/
if (`mc_mwe_l == 0 && `mc_cas_l[3:0] == 'hf)
begin
datareg = `BOARD.ssparc.b_memdata;
parityreg = `BOARD.ssparc.b_mempar;
adrreg = `BOARD.ssparc.mc_memaddr;
end
// Put delay for the sampling
#2 ;
/* ------------------------------------------------
Checks for refresh counter and logic
-----------------------------------------------
*/
if ((MM_RF_CNTL_0[3:0] != `mm_rf_cntl[3:0]) && ($time > 50 )) begin
case (`mm_rf_cntl)
// Refresh is off
4'b0001:begin
$write("\n %0d: ### Warning! mem.v(1) REFRESH is OFF since PCR[13:10]=4'b0001 {%0t}\n",Mclocks.cycle_count,$stime);
refresh_rate = `RC_0001;
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// Refresh is on
4'b0000:begin
refresh_rate = `RC_0000;
$write("\n %0d: INFO! mem.v REFRESH every 128 MCLKs since PCR[13:10]=4'b0000 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0010:begin
refresh_rate = `RC_0010;
$write("\n %0d: INFO! mem.v REFRESH every 704 MCLKs since PCR[13:10]=4'b0010 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0011:begin
refresh_rate = `RC_0011;
$write("\n %0d: INFO! mem.v REFRESH every 896 MCLKs since PCR[13:10]=4'b0011 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0100:begin
refresh_rate = `RC_0100;
$write("\n %0d: INFO! mem.v REFRESH every 1216 MCLKs since PCR[13:10]=4'b0100 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0101:begin
refresh_rate = `RC_0101;
$write("\n %0d: INFO! mem.v REFRESH every 5120 MCLKs since PCR[13:10]=4'b0101 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0110:begin
refresh_rate = `RC_0110;
$write("\n %0d: INFO! mem.v REFRESH every 1408 MCLKS since PCR[13:10]=4'b0110 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0111:begin
refresh_rate = `RC_0111;
$write("\n %0d: INFO! mem.v REFRESH every 1792 MCLKS since PCR[13:10]=4'b0111 {%0t}\n",Mclocks.cycle_count,$stime);
end
// Self Refresh Dram mode
4'b1???:begin
$write("\n %0d: INFO! mem.v SELF REFRESH MODE since PCR[13:10]=4'b1xxx {%0t}\n",Mclocks.cycle_count,$stime);
end
endcase
end
// Check for mmu - memif interface protocol.
// The protocol checks for correct combination
// of mc_mbsy and mm_issue_req and mm_mreq.
/*
if (!MBSY && `mc_mbsy) // check for memory busy going active
if(( (((!MREQ[3] && !`mm_mreq[2] && !`mm_mreq[1] && `mm_mreq[0] ) // read 2 words
||(!MREQ[3] && !`mm_mreq[2] && `mm_mreq[1] && !`mm_mreq[0] ) // read 4 words
||(!MREQ[3] && `mm_mreq[2] && !`mm_mreq[1] && !`mm_mreq[0] ) // read 8 words
) &&( MREQ[3] == `mm_mreq[3]) // the msb should be stable for read
) // end of read condition
||(
( ( MREQ[3] && !MREQ[2] && !MREQ[1] && MREQ[0]) // 1byte write
||( MREQ[3] && !MREQ[2] && MREQ[1] && !MREQ[0]) // 2byte write
||( MREQ[3] && !MREQ[2] && MREQ[1] && MREQ[0]) // 4byte write
||( MREQ[3] && MREQ[2] && !MREQ[1] && !MREQ[0]) // 8byte write
||( MREQ[3] && MREQ[2] && !MREQ[1] && MREQ[0]) // 16byte write
) &&( MREQ == `mm_mreq) // the whole field should be stable for read
) // end of write condition
)
&& MM_ISSUE_REQ_0 // Check for mm_issue_req -delayed by one clock
||
`mm_rf_cntl[3] // Check for Self refresh asserted
||
// (`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.mcb_sm.mm_afx_gnt) ||
!RREQ_L) ; // Check for basic refresh asserted
else
begin
$write("\n %0d: *** Error! mem.v illegal mc_mbsy and mm_issue_req and mm_req combination {%0t} \n", Mclocks.cycle_count, $stime);
$write("\n %0d: *** Error! mem.v mm_mreq in the cycle of issue_req is = %h mm_mreq in the cycle following issue_req is = %h mm_issue_req =%b, \n", Mclocks.cycle_count, MREQ, `mm_mreq, MM_ISSUE_REQ_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
*/
/* --------------------------------------------------- */
// Check for mmu - memif debug feature interface protocol. kwok
// The protocol checks for correct combination
// of mm_mem_dbg, mm_iccfstb, mm_dccfstb, mm_iostben and ab[14:13] and mc_mstb_l.
// ARAY do this only if not AFX dma
if (`SSPARC_CORE.w_am_gnt_l)
if (((( `mc_cas_l[0] && (!CAS_L_0[0]) ) || ( `mc_cas_l[1] && (!CAS_L_0[1]) )
|| ( `mc_cas_l[2] && (!CAS_L_0[2]) ) || ( `mc_cas_l[3] && (!CAS_L_0[3]) ))
&& !(( `mc_cas_l[0] && (!CAS_L_0[0]) ) && ( `mc_cas_l[1] && (!CAS_L_0[1]) )
&& ( `mc_cas_l[2] && (!CAS_L_0[2]) ) && ( `mc_cas_l[3] && (!CAS_L_0[3]) )) )
&& ( `mc_mwe_l && (MWE_L0) ) && !`mc_mbsy ) begin //cas_l,but !all was just de-asserted
//if (!((`mm_icstben && (`ab[14:13]==2'b00)) ||
// (`mm_dcstben && (`ab[14:13]==2'b01)) ||
// (`mm_iostben && (`ab[14:13]==2'b11)) ||
// (!`mm_icstben && !`mm_dcstben && !`mm_iostben && (`ab[14:13]==2'b10)) )) begin
if (!((MM_ICSTBEN && (!`ab_14 && !`ab_13)) ||
(MM_DCSTBEN && (!`ab_14 && `ab_13)) ||
(MM_IOSTBEN && (`ab_14 && `ab_13)) ||
(!MM_ICSTBEN && !MM_DCSTBEN && !MM_IOSTBEN && (`ab_14 && !`ab_13)) )) begin
$write("\n %0d: *** Error! mem.v debug feature incorrect {%0t} \n", Mclocks.cycle_count, $stime);
$write("\n %0d: *** Error! mem.v ab[14:13] at rising CAS_l is = %b %b mm_icstben is = %b mm_dcstben is = %b mm_iostben is =%b, \n", Mclocks.cycle_count, `ab_14, `ab_13, MM_ICSTBEN, MM_DCSTBEN, MM_IOSTBEN);
// Mclocks.error_count = Mclocks.error_count + 1;
end
end
/* ----------------------------------------------------
Refer to Table 5, page 140 of Swift CPU Spec. -
Rev. 1.2 11/16/92
---------------------------------------------------
*/
// Check for CAS active times - CAS[0]
if ( `mc_cas_l[0] && (!CAS_L_0[0]) ) begin // cas_l was just de-asserted
case (Msystem.speed_select)
`SPEED70:begin // read active 3 cycles, write active 2 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[0] || CAS_L_2[0] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[0] low for less than 3 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[0] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[0] low for less than 2 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED85, `SPEED100:begin // read active 4 cycles, write active 2 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[0] low for less than 4 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[0] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[0] low for less than 2 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
// IIe note : The write enable is valid only in non-Falcon cycles.
`SPEED125:begin // read active 5 cycles, write active 3 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] || CAS_L_4[0] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[0] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[0] || CAS_L_2[0] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[0] low for less than 3 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED150:begin // read active 6 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] || CAS_L_4[0] || CAS_L_5[0]) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[0] low for less than 6 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[0] low for less than 4 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED175:begin // read active 7 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] || CAS_L_4[0] || CAS_L_5[0] || CAS_L_6[0] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[0] low for less than 7 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] || CAS_L_4[0] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[0] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED200:begin // read active 8 cycles, write active 5 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] || CAS_L_4[0] || CAS_L_5[0] || CAS_L_6[0] || CAS_L_7[0] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[0] low for less than 8 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[0] || CAS_L_2[0] || CAS_L_3[0] || CAS_L_4[0] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[0] low for less than 5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
endcase // for speed_select
end // check for cas time
// Check for CAS active times - CAS[1]
if ( `mc_cas_l[1] && (!CAS_L_0[1]) ) begin // cas_l was just de-asserted
case (Msystem.speed_select)
`SPEED70:begin // read active 3 cycles, write active 2 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[1] || CAS_L_2[1] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[1] low for less than 3 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[1] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[1] low for less than 2 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED85, `SPEED100:begin // read active 4 cycles, write active 2 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[1] low for less than 4 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[1] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[1] low for less than 2 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED125:begin // read active 5 cycles, write active 3 cycles
if (MWE_L0 && ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] || CAS_L_4[1] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[1] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[1] || CAS_L_2[1] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[1] low for less than 3 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED150:begin // read active 6 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] || CAS_L_4[1] || CAS_L_5[1]) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[1] low for less than 6 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[1] low for less than 4 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED175:begin // read active 7 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] || CAS_L_4[1] || CAS_L_5[1] || CAS_L_6[1] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[1] low for less than 7 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] || CAS_L_4[1] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[1] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED200:begin // read active 8 cycles, write active 5 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] || CAS_L_4[1] || CAS_L_5[1] || CAS_L_6[1] || CAS_L_7[1] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[1] low for less than 8 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[1] || CAS_L_2[1] || CAS_L_3[1] || CAS_L_4[1] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[1] low for less than 5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
endcase // for speed_select
end // check for cas time
// Check for CAS active times - CAS[2]
if ( `mc_cas_l[2] && (!CAS_L_0[2]) ) begin // cas_l was just de-asserted
case (Msystem.speed_select)
`SPEED70:begin // read active 3 cycles, write active 2 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[2] || CAS_L_2[2] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[2] low for less than 3 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[2] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[2] low for less than 2 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED85, `SPEED100:begin // read active 4 cycles, write active 2 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[2] low for less than 4 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[2] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[2] low for less than 2 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED125:begin // read active 5 cycles, write active 3 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] || CAS_L_4[2] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[2] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[2] || CAS_L_2[2] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[2] low for less than 3 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED150:begin // read active 6 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] || CAS_L_4[2] || CAS_L_5[2]) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[2] low for less than 6 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[2] low for less than 4 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED175:begin // read active 7 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] || CAS_L_4[2] || CAS_L_5[2] || CAS_L_6[2] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[2] low for less than 7 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] || CAS_L_4[2] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[2] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED200:begin // read active 8 cycles, write active 5 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] || CAS_L_4[2] || CAS_L_5[2] || CAS_L_6[2] || CAS_L_7[2] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[2] low for less than 8 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[2] || CAS_L_2[2] || CAS_L_3[2] || CAS_L_4[2] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[2] low for less than 5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
endcase // for speed_select
end // check for cas time
// Check for CAS active times - CAS[3]
if ( `mc_cas_l[3] && (!CAS_L_0[3]) ) begin // cas_l was just de-asserted
case (Msystem.speed_select)
`SPEED70:begin // read active 3 cycles, write active 2 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[3] || CAS_L_2[3] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[3] low for less than 3 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[3] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[3] low for less than 2 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED85, `SPEED100:begin // read active 4 cycles, write active 2 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[3] low for less than 4 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[3] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[3] low for less than 2 cycles at 85-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED125:begin // read active 5 cycles, write active 3 cycles
if (MWE_L0) begin
// this was a read
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] || CAS_L_4[3] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[3] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[3] || CAS_L_2[3] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[3] low for less than 3 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED150:begin // read active 6 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] || CAS_L_4[3] || CAS_L_5[3]) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[3] low for less than 6 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[3] low for less than 4 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED175:begin // read active 7 cycles, write active 4 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] || CAS_L_4[3] || CAS_L_5[3] || CAS_L_6[3] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[3] low for less than 7 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] || CAS_L_4[3] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[3] low for less than 5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
`SPEED200:begin // read active 8 cycles, write active 5 cycles
if (MWE_L0 & ~(`SSPARC_CORE.ssparc_memif.memif_major.mcb.mcb_lgc.cyc_reg == 7'h5c)) begin
// this was a read
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] || CAS_L_4[3] || CAS_L_5[3] || CAS_L_6[3] || CAS_L_7[3] ) begin
$write("\n %0d: *** Error! mem.v READ:mc_cas_l[3] low for less than 8 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
else begin
// this was a write
if( CAS_L_1[3] || CAS_L_2[3] || CAS_L_3[3] || CAS_L_4[3] ) begin
$write("\n %0d: *** Error! mem.v WRITE:mc_cas_l[3] low for less than 5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
end
endcase // for speed_select
end // check for cas time
end // always big loop ALWAYS_MEMORY_MONITOR
/* ---------------------------------------------------------
Check for RAS precharge times
based on Table 5: Page 140 Swift Spec. Rev1.2
--------------------------------------------------------
*/
// Check for RAS precharge times - RAS[0]
integer ras_pre_start_time_0, ras_pre_end_time_0 ;
always @(posedge `mc_ras_l[0]) begin
ras_pre_start_time_0 = $time;
end
always @(negedge `mc_ras_l[0]) begin
ras_pre_end_time_0 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_0 - ras_pre_start_time_0) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[0] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_0);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_0 - ras_pre_start_time_0) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[0] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_0);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_0 - ras_pre_start_time_0) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[0] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_0);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_0 - ras_pre_start_time_0) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[0] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_0);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_0 - ras_pre_start_time_0) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[0] precharge for less than 7.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_0);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_0 - ras_pre_start_time_0) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[0] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_0);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for RAS precharge times - RAS[1]
integer ras_pre_start_time_1, ras_pre_end_time_1 ;
always @(posedge `mc_ras_l[1]) begin
ras_pre_start_time_1 = $time;
end
always @(negedge `mc_ras_l[1]) begin
ras_pre_end_time_1 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_1 - ras_pre_start_time_1) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[1] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_1);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_1 - ras_pre_start_time_1) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[1] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_1);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_1 - ras_pre_start_time_1) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[1] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_1);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_1 - ras_pre_start_time_1) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[1] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_1);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_1 - ras_pre_start_time_1) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[1] precharge for less than 7.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_1);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
| This page: |
Created: | Thu Aug 19 12:02:20 1999 |
| From: |
../../../sparc_v8/system/rtl/mem.v |