/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
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/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)rl_mcb.v 1.23 10/18/93
/****************************************************************************
* rl_mcb.v
*
* Description:
* The Memory Control Block (MCB) of memory subsystem in SingleSPARC.
* The bulk of logic and state machines controlling RAM accesses
* and the RAM address muxes are defined here.
*
* This file basically contains the two modules Mcb_SM (in mcb_sm.v)
* and Col_Row_Addr (in row_col_mux.v) and some interconnect logic
* providing the MCB functionality.
*
* Refer to SingleSPARC Hardware Spec, section 2.7.3 for block diagram
* and more information.
*
*
* Dependencies:
* defines.v mem_cells.v row_col_mux.v mcb_sm.v
*
*
****************************************************************************/
/************************************************************************
* This module contains the MCB's Logic.
*/
module rl_mcb
(
mc_memaddr, mc_ras_l, mc_cas_l, mc_moe_l, mc_mwe_l, simm32_sel,
mc_mstb_l, mc_mbsy,
mc_rack_l,
mc_dpct, mc_curr_st, mc_cyc_reg, mc_odat_hld,
mc_caddr_hld, mc_refresh, pdm_ready,
s_reply, aen, ab, p_reply_dec, afx_to, prom_p_reply,
mc_memaddr_in, afx_rst_page_vld, am_gnt_l, am_cstb_l, am_read,
falcon_exists, am_wm, mm_sbae_0,
mm_pa_a, mm_pa_b, mm_caddr, mm_issue_req, mm_issue_req2,
mm_mreq, mm_page,
rf_cbr, rf_rreq_l,
ss_reset, ss_clock, ss_dclk, sp_sel, sp_sel_1, sp_sel_2, precharge_early_0,
precharge_early_1,
mm_rf_cntl_3, mm_issue_req_early,
sync_t0, p_reply, pcic_p_reply, mm_fb_req, mm_fb_size, mm_fb_page, mm_mem_dbg,
valid_l, cas_cyc, ab_in, am_gnt_l_oen
);
output [11:00] mc_memaddr
; /* to memory.*/
output [07:00] mc_ras_l
; /* to memory.*/
output [03:00] mc_cas_l
; /* to memory.*/
output mc_moe_l
; /* to memory.*/
output mc_mwe_l
; /* to memory.*/
output mc_mstb_l
; /* to MMU.*/
output mc_mbsy
; /* to MMU.*/
output mc_rack_l
; /* to RFR.*/
output [05:00] mc_dpct
; /* to DPC.*/
output [8:00] mc_curr_st
; /* to DPC.*/
output [06:00] mc_cyc_reg
; /* to DPC.*/
output mc_odat_hld
; /* to DPC.*/
output mc_caddr_hld
; /* to MMU.*/
output mc_refresh
; /* to MMU.*/
output pdm_ready
; /* to MMU.*/
output s_reply
; /* to MMU.*/
output aen
; /* to MMU.*/
output [14:12] ab
; /* to VRAM.*/
output [2:0] p_reply_dec
; /* to VRAM.*/
output afx_to
; /* to MMU.*/
output valid_l
; // To Falcon : data strobe
output cas_cyc
; // To Falcon : enable column address
output am_gnt_l_oen
; // To mem address : enable tri-state driver of mem address
input [14:12] ab_in
; // From Falcon : upper 3 bit of mem address.
input [11:0] mc_memaddr_in
;
output afx_rst_page_vld
; // to mmu
output am_gnt_l
;
input am_cstb_l
;
input am_read
;
input falcon_exists
;
input [1:0] am_wm
; // Falcon word mask bits
input mm_sbae_0
;
input [1:0] prom_p_reply
;
/* Split and remove unused bits of mm_pa */
input [28:12] mm_pa_a
;
input [02:00] mm_pa_b
;
input [11:03] mm_caddr
;
input mm_issue_req
; // Valid-request from MMU.
input mm_issue_req2
; // Valid-request from MMU.
input [03:00] mm_mreq
;
input mm_page
;
input rf_cbr
;
input rf_rreq_l
;
input ss_reset
;
input ss_clock
;
input ss_dclk
; // anti-phase (delayed) clock
input simm32_sel
; // for double density simm select.
input sp_sel
; // 40MHz ("0") or 50MHz ("1") select pin.
input sp_sel_1
; // MHz ("0") or MHz ("1") select pin.
input sp_sel_2
; // for 150Mhz - 200Mhz
input precharge_early_0
; // early precharge signal from mmu.
input precharge_early_1
; // early precharge signal from mmu.
// input power_down_mode;
input mm_rf_cntl_3
;
input mm_issue_req_early
;
input sync_t0
;
input [1:0] p_reply
;
input [1:0] pcic_p_reply
;
input mm_fb_req
;
input [1:0] mm_fb_size
;
input mm_fb_page
;
input [1:0] mm_mem_dbg
;
wire [1:0] mx_hld_mm_pa
;
assign mc_caddr_hld = mx_hld_mm_pa[0] ;
wire gaddr_hld
;
wire sel_hi_row
;
wire sel_row
;
wire sel_gr_page
;
wire sel_default
;
wire dly_bsy
;
// hld_mm_pa[0] is just 1 cycle earlier than hld_mm_pa[1]. Former is for caddr reg
// which is 1 cycle earlier than the latter; which is pa reg
// Now, col addr [11:3] sent out 2 cycle earlier than cas; while bit [21], [23] are
// 1 cycle earlier than cas
wire [28:12] mm_pa_a_new
;
assign mm_pa_a_new[28:24] =
am_gnt_l ? {(mm_pa_a[28] & falcon_exists), mm_pa_a[27:24
]} :
{1'b0, ab_in[14:12], mc_memaddr_in[10]} ;
assign mm_pa_a_new[20:14] = am_gnt_l ? mm_pa_a[20:14] :
mc_memaddr_in[8:2];
wire [2:0] mm_pa_b_new
=
(~am_gnt_l & cas_cyc) ? {mc_memaddr_in[11], 1'b0, 1'b0}
: mm_pa_b[2:0];
wire [11:3] mm_caddr_new
=
(~am_gnt_l & cas_cyc) ? mc_memaddr_in[8:0] : mm_caddr[11
:3];
assign mm_pa_a_new[21] =
(~am_gnt_l & cas_cyc) ? mc_memaddr_in[9] : mm_pa_a[21];
/*
assign mm_pa_a_new[23:22] =
(~am_gnt_l & cas_cyc) ? ab_in[14:13] :
(~am_gnt_l) ? mc_memaddr_in[10:9] :
mm_pa_a[23:22];
*/
assign mm_pa_a_new[23] =
(~am_gnt_l & cas_cyc) ? mc_memaddr_in[10] :
(~am_gnt_l) ? mc_memaddr_in[11] :
mm_pa_a[23];
assign mm_pa_a_new[22] = (~am_gnt_l) ? mc_memaddr_in[9] :
mm_pa_a[22];
assign mm_pa_a_new[13:12] =
(~am_gnt_l & cas_cyc) ? ab_in[13:12] :
(~am_gnt_l) ? mc_memaddr_in[1:0] :
mm_pa_a[13:12];
rl_mcb_lgc
mcb_lgc(
mc_cas_l, mc_ras_l, mc_moe_l, mc_mwe_l, simm32_sel,
mc_mstb_l, mc_mbsy,
mc_dpct, mc_curr_st, mc_cyc_reg, mc_odat_hld,
mx_hld_mm_pa, mx_col_en
,
mx_s_blk
,
mx_ld_ct
, mx_mode_ct
, mx_inc_ct
,
mc_rack_l, mc_refresh, pdm_ready, gaddr_hld, sel_hi_row, sel_row, sel_gr_page, sel_default,
gr_s_blk
, gr_mode_ct
, gr_inc_ct
,
s_reply, aen, p_reply_dec, afx_to, prom_p_reply, dly_bsy,
afx_rst_page_vld, am_gnt_l, am_cstb_l, am_read,
falcon_exists, am_wm, mm_sbae_0,
mm_issue_req, mm_issue_req2, mm_mreq, mm_page,
mm_pa_a_new[28], mm_pa_a_new[27], mm_pa_a_new[26], mm_pa_a_new[25],
mm_pa_b_new[00], mm_pa_b_new[01], mm_pa_b_new[02],
rf_rreq_l, rf_cbr,
ss_clock, ss_dclk, ss_reset, sp_sel, sp_sel_1, sp_sel_2, precharge_early_0,
precharge_early_1,
mm_rf_cntl_3, mm_issue_req_early,
sync_t0, p_reply, pcic_p_reply, mm_fb_req, mm_fb_page, valid_l, cas_cyc, am_gnt_l_oen);
rl_col_row_addr
cr_addr(
mc_memaddr, ab,
mm_pa_a_new[24:12], mm_caddr_new[11:03],
mx_hld_mm_pa[1], mx_col_en,
mx_s_blk,
mx_ld_ct, mx_mode_ct, mx_inc_ct,
ss_clock, gaddr_hld, sel_hi_row, sel_row, sel_gr_page, sel_default,
mm_pa_a_new[28], mm_pa_a_new[27], mm_pa_a_new[26], mm_pa_a_new[25],
mm_pa_b_new[00], mm_pa_b_new[01], mm_pa_b_new[02], mm_fb_size,
gr_s_blk, gr_mode_ct, gr_inc_ct, mc_odat_hld, mm_mem_dbg,
mm_issue_req, dly_bsy );
// Added spare cells
// spares rl_mcb_spares ();
/***********************************************************************
* The Memory Device_Operating_Environment, for test and debug use.
***********************************************************************/
//synopsys translate_off
MEM_Device_Operating_Environment mem ();
//synopsys translate_on
endmodule
This page: |
Created: | Thu Aug 19 12:01:06 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_mcb.v
|