always @(negedge `mc_ras_l[1] )begin
if (cas_bfr_ras_flag_bank1) begin
cas_bfr_ras_end_time_bank1 = $time ;
ras_refresh_start_time_bank1 = $time ;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // cas before ras refresh time 2.5 cycles
if ((cas_bfr_ras_end_time_bank1 - cas_bfr_ras_start_time) < (2.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank1 for less than 2.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank1 = %d\n", cas_bfr_ras_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // cas before ras refresh time 3.5 cycles
if ((cas_bfr_ras_end_time_bank1 - cas_bfr_ras_start_time) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank1 for less than 3.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank1 = %d\n", cas_bfr_ras_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // cas before ras refresh time 4.5 cycles
if ((cas_bfr_ras_end_time_bank1 - cas_bfr_ras_start_time) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank1 for less than 4.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank1 = %d\n", cas_bfr_ras_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // cas before ras refresh time 4.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank1 for less than 4.5 cycles at 150 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank1 = %d\n", cas_bfr_ras_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // cas before ras refresh time 5.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank1 for less than 5.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank1 = %d\n", cas_bfr_ras_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // cas before ras refresh time 6.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank1 for less than 6.5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank1 = %d\n", cas_bfr_ras_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // end of speed select
cas_bfr_ras_flag_bank1 = 1'b0 ; // reset the flag
end // for scan_operation
end // check for flag
end
// Check for ras active during refresh
//always @(posedge `mc_ras_l[7:0])begin
always @(posedge `mc_ras_l[0])
if (~ `rst) begin
if ((~cas_bfr_ras_flag_bank0) && (~cas_bfr_ras_flag_bank1) && ($time > 50)) begin
ras_refresh_end_time_bank0 = $time ;
ras_refresh_end_time_bank1 = $time ;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85, `SPEED100:begin // ras active for refresh 7.5 cycles for bank 0
// for bank zero it is one more cycle
if ((ras_refresh_end_time_bank0 - ras_refresh_start_time_bank0) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 7.5 cycles at 70MHz-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank0 = %d\n", ras_refresh_start_time_bank0);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank0 = %d\n", ras_refresh_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
// for bank one it is the minimum
if ((ras_refresh_end_time_bank1 - ras_refresh_start_time_bank1) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 6.5 cycles at 70MHz-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank1 = %d\n", ras_refresh_start_time_bank1);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank1 = %d\n", ras_refresh_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras active for refresh 9.5 cycles for bank 0
// for bank zero it is one more cycle
if ((ras_refresh_end_time_bank0 - ras_refresh_start_time_bank0) < (9.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 9.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank0 = %d\n", ras_refresh_start_time_bank0);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank0 = %d\n", ras_refresh_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
// for bank one it is the minimum
if ((ras_refresh_end_time_bank1 - ras_refresh_start_time_bank1) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank1 = %d\n", ras_refresh_start_time_bank1);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank1 = %d\n", ras_refresh_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras active for refresh 10.5 cycles for bank 0
// for bank zero it is one more cycle
if ((ras_refresh_end_time_bank0 - ras_refresh_start_time_bank0) < (10.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 10.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank0 = %d\n", ras_refresh_start_time_bank0);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank0 = %d\n", ras_refresh_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
// for bank one it is the minimum
if ((ras_refresh_end_time_bank1 - ras_refresh_start_time_bank1) < (9.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 9.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank1 = %d\n", ras_refresh_start_time_bank1);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank1 = %d\n", ras_refresh_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras active for refresh 11.5 cycles for bank 0
// for bank zero it is one more cycle
if ((ras_refresh_end_time_bank0 - ras_refresh_start_time_bank0) < (11.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 11.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank0 = %d\n", ras_refresh_start_time_bank0);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank0 = %d\n", ras_refresh_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
// for bank one it is the minimum
if ((ras_refresh_end_time_bank1 - ras_refresh_start_time_bank1) < (10.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 10.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank1 = %d\n", ras_refresh_start_time_bank1);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank1 = %d\n", ras_refresh_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras active for refresh 12.5 cycles for bank 0
// for bank zero it is one more cycle
if ((ras_refresh_end_time_bank0 - ras_refresh_start_time_bank0) < (12.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 12.5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank0 = %d\n", ras_refresh_start_time_bank0);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank0 = %d\n", ras_refresh_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
// for bank one it is the minimum
if ((ras_refresh_end_time_bank1 - ras_refresh_start_time_bank1) < (11.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_refresh for less than 11.5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_refresh_start_time_bank1 = %d\n", ras_refresh_start_time_bank1);
$write("\n ###! INFO: mem.v - ras_refresh_end_time_bank1 = %d\n", ras_refresh_end_time_bank1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // end of speed select
end // for scan_operation
end // check flag
end // ras is de-asserted
/* ----------------------------------------------
Check for RAS active low times
This will check only for the first access
The active low time is measured as
ras going low time to ras time when the
cas goes high.
----------------------------------------------
*/
integer ras_active_start_time_0
,
ras_active_end_time_0;
reg ras_active_flag_0;
reg write_flag ; // flag to check if it was a write or a read
initial begin
ras_active_flag_0 = 1'b0 ;
end
always @(negedge `mc_ras_l[6] or negedge `mc_ras_l[4] or negedge `mc_ras_l[2] or negedge `mc_ras_l[0] or
negedge `mc_ras_l[7] or negedge `mc_ras_l[5] or negedge `mc_ras_l[3] or negedge `mc_ras_l[1]
) begin
if ((`mc_cas_l[3:0] === 4'b1111) && (~ras_active_flag_0)) begin
ras_active_start_time_0 = $time;
ras_active_flag_0 = 1'b1;
end
end
always @(negedge `mc_cas_l[3] or negedge `mc_cas_l[2] or negedge `mc_cas_l[1] or negedge `mc_cas_l[0]) begin
if (ras_active_flag_0) begin
write_flag = `mc_mwe_l ;
end
end
always @(posedge `mc_cas_l[3] or posedge `mc_cas_l[2] or posedge `mc_cas_l[1] or posedge `mc_cas_l[0])
if (~ `rst) begin
if (ras_active_flag_0) begin
ras_active_end_time_0 = $time ;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70:begin // ras active for read 6.5 cycles for write 5.5 cycles
if (write_flag) begin
if ((ras_active_end_time_0 - ras_active_start_time_0) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_read for less than 6.5 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
else
if ((ras_active_end_time_0 - ras_active_start_time_0) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_write for less than 5.5 cycles at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end // write_flag
end // speed select
`SPEED85:begin // ras active for read 7.5 cycles for write 5.5 cycles
if (write_flag) begin
if ((ras_active_end_time_0 - ras_active_start_time_0) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_read for less than 7.5 cycles at 85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
else
if ((ras_active_end_time_0 - ras_active_start_time_0) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_write for less than 5.5 cycles at 85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end // write_flag
end // speed select
`SPEED100:begin // ras active for read 8.5 cycles for write 6.5 cycles
if (write_flag) begin
if ((ras_active_end_time_0 - ras_active_start_time_0) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_read for less than 8.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
else
if ((ras_active_end_time_0 - ras_active_start_time_0) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_write for less than 6.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end // write_flag
end // speed select
`SPEED125:begin // ras active for read 10.5 cycles for write 8.5 cycles
if (write_flag) begin
if ((ras_active_end_time_0 - ras_active_start_time_0) < (10.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_read for less than 10.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
else
if ((ras_active_end_time_0 - ras_active_start_time_0) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_write for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end // write_flag
end // speed select
`SPEED150:begin // ras active for read 13.5 cycles (use 12.5 for cas_l goes to high point) for write 12.5 (use 11.5) cycles
if (write_flag) begin
if ((ras_active_end_time_0 - ras_active_start_time_0) < (12.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_read for less than 13.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
else
if ((ras_active_end_time_0 - ras_active_start_time_0) < (11.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_write for less than 12.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end // write_flag
end // speed select
`SPEED175:begin // ras active for read 16.5 (use 15.5) cycles for write 14.5 (use 13.5) cycles
if (write_flag) begin
if ((ras_active_end_time_0 - ras_active_start_time_0) < (15.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_read for less than 16.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
else
if ((ras_active_end_time_0 - ras_active_start_time_0) < (13.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_write for less than 14.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end // write_flag
end // speed select
`SPEED200:begin // ras active for read 18.5 (use 17.5) cycles for write 15.5 (use 14.5) cycles
if (write_flag) begin
if ((ras_active_end_time_0 - ras_active_start_time_0) < (17.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_read for less than 18.5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
else
if ((ras_active_end_time_0 - ras_active_start_time_0) < (14.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v ras_active_for_write for less than 14.5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_active_start_time_0 = %d\n", ras_active_start_time_0);
$write("\n ###! INFO: mem.v - ras_active_end_time_0 = %d\n", ras_active_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end // write_flag
end // speed select
endcase
end // for scan_operation
ras_active_flag_0 = 1'b0 ; // reset the flag for next operation
end // check for ras_active_flag
end // always
/* ----------------------------------------------------
This is checking for refresh during standby
----------------------------------------------------
*/
integer standby_start_time,
standby_end_time;
always @(posedge Mtask.standby_dsbl_sysclk) begin
standby_start_time = $time;
// $write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
standby_asserted_flag = 1'b1 ;
cbr_refresh_standby_count = 32'b0;
end
always @(negedge Mtask.standby_dsbl_sysclk) begin
standby_end_time = $time;
// $write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
if (~Mclocks.scan_operation) begin
case (`mm_rf_cntl)
// Refresh is off
4'b0001:begin
$write("\n %0d: ### Warning! mem.v(2) REFRESH is OFF since PCR[13:10]=4'b0001 during standby {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// Refresh is on
4'b0000:begin
if (((((standby_end_time - standby_start_time)/`CYCLETIME)/(`RC_0000)) > cbr_refresh_standby_count) && (cbr_refresh_standby_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during standby REFRESH every 128 MCLKs since PCR[13:10]=4'b0000 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
$write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_standby_count = %d\n", cbr_refresh_standby_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0010:begin
if (((((standby_end_time - standby_start_time)/`CYCLETIME)/(`RC_0010)) > cbr_refresh_standby_count) && (cbr_refresh_standby_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during standby REFRESH every 704 MCLKs since PCR[13:10]=4'b0010 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
$write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_standby_count = %d\n", cbr_refresh_standby_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0011:begin
if (((((standby_end_time - standby_start_time)/`CYCLETIME)/(`RC_0011)) > cbr_refresh_standby_count) && (cbr_refresh_standby_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during standby REFRESH every 896 MCLKs since PCR[13:10]=4'b0011 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
$write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_standby_count = %d\n", cbr_refresh_standby_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0100:begin
if (((((standby_end_time - standby_start_time)/`CYCLETIME)/(`RC_0100)) > cbr_refresh_standby_count) && (cbr_refresh_standby_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during standby REFRESH every 1216 MCLKs since PCR[13:10]=4'b0100 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
$write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_standby_count = %d\n", cbr_refresh_standby_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0101:begin
if (((((standby_end_time - standby_start_time)/`CYCLETIME)/(`RC_0101)) > cbr_refresh_standby_count) && (cbr_refresh_standby_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during standby REFRESH every 5120 MCLKs since PCR[13:10]=4'b0101 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
$write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_standby_count = %d\n", cbr_refresh_standby_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0110:begin
if (((((standby_end_time - standby_start_time)/`CYCLETIME)/(`RC_0110)) > cbr_refresh_standby_count) && (cbr_refresh_standby_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during standby REFRESH every 1408 MCLKs since PCR[13:10]=4'b0110 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
$write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_standby_count = %d\n", cbr_refresh_standby_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0111:begin
if (((((standby_end_time - standby_start_time)/`CYCLETIME)/(`RC_0111)) > cbr_refresh_standby_count) && (cbr_refresh_standby_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during standby REFRESH every 1792 MCLKs since PCR[13:10]=4'b0111 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - standby_start_time = %d\n", standby_start_time);
$write("\n ###! INFO: mem.v - standby_end_time = %d\n", standby_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_standby_count = %d\n", cbr_refresh_standby_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
// Self Refresh Dram mode
4'b1???:$write("\n %0d: INFO! mem.v SELF REFRESH MODE since PCR[13:10]=4'b1xxx {%0t}\n",Mclocks.cycle_count,$stime);
endcase
standby_asserted_flag = 1'b0 ;
end // for scan_operation
end // always when standby clock is de-asserted
//
reg refresh_rate_flag ;
`define REFRESH_DELAY 32'd1000 // delay of 50 time units for gate level
initial begin
refresh_rate_flag = 1'b1;
refresh_change_flag = 1'b0;
end
always @( `mm_rf_cntl ) begin
/*
// This is for debug use
case (`mm_rf_cntl)
// Refresh is off
4'b0001:begin
$write("\n %0d: ### Warning! mem.v(3) REFRESH is OFF since PCR[13:10]=4'b0001 {%0t}\n",Mclocks.cycle_count,$stime);
refresh_rate = `RC_0001;
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// Refresh is on
4'b0000:begin
refresh_rate = `RC_0000;
$write("\n %0d: INFO! mem.v REFRESH every 128 MCLKs since PCR[13:10]=4'b0000 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0010:begin
refresh_rate = `RC_0010;
$write("\n %0d: INFO! mem.v REFRESH every 704 MCLKs since PCR[13:10]=4'b0010 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0011:begin
refresh_rate = `RC_0011;
$write("\n %0d: INFO! mem.v REFRESH every 896 MCLKs since PCR[13:10]=4'b0011 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0100:begin
refresh_rate = `RC_0100;
$write("\n %0d: INFO! mem.v REFRESH every 1216 MCLKs since PCR[13:10]=4'b0100 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0101:begin
refresh_rate = `RC_0101;
$write("\n %0d: INFO! mem.v REFRESH every 5120 MCLKs since PCR[13:10]=4'b0101 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0110:begin
refresh_rate = `RC_0110;
$write("\n %0d: INFO! mem.v REFRESH every 1408 MCLKS since PCR[13:10]=4'b0110 {%0t}\n",Mclocks.cycle_count,$stime);
end
4'b0111:begin
refresh_rate = `RC_0111;
$write("\n %0d: INFO! mem.v REFRESH every 1792 MCLKS since PCR[13:10]=4'b0111 {%0t}\n",Mclocks.cycle_count,$stime);
end
// Self Refresh Dram mode
4'b1???:begin
refresh_rate = `RC_1XXX;
$write("\n %0d: INFO! mem.v SELF REFRESH MODE since PCR[13:10]=4'b1xxx {%0t}\n",Mclocks.cycle_count,$stime);
end
endcase
*/
// Enable the refresh_rate_flag after time unit of 50 so as
// to ignore the transitions during reset from unknown to
// a known value
if (($time > `REFRESH_DELAY) && !`SS_SCOPE.ss_scan_mode && !Mclocks.scan_operation) begin
if (refresh_rate_flag) begin
refresh_change_flag = 1'b1;
cbr_refresh_count = 32'b0;
refresh_rate_flag = 1'b0;
end
else begin //
refresh_rate_end_time = $time ;
case (MM_RF_CNTL_0)
// Refresh is off
4'b0001:begin
$write("\n %0d: ### Warning! mem.v(4) REFRESH is OFF since PCR[13:10]=4'b0001 during normal operation {%0t}\n",Mclocks.cycle_count,$stime);
Mclocks.warning_count = Mclocks.warning_count + 1;
end
// Refresh is on
4'b0000:begin
if (((((refresh_rate_end_time - refresh_rate_start_time)/`CYCLETIME)/(`RC_0000)) > cbr_refresh_count) && (cbr_refresh_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during normal operation- REFRESH every 128 MCLKs since PCR[13:10]=4'b0000 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - refresh_rate_start_time = %d\n", refresh_rate_start_time);
$write("\n ###! INFO: mem.v - refresh_rate_end_time = %d\n", refresh_rate_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_count = %d\n", cbr_refresh_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0010:begin
if (((((refresh_rate_end_time - refresh_rate_start_time)/`CYCLETIME)/(`RC_0010)) > cbr_refresh_count) && (cbr_refresh_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during normal operation- REFRESH every 704 MCLKs since PCR[13:10]=4'b0010 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - refresh_rate_start_time = %d\n", refresh_rate_start_time);
$write("\n ###! INFO: mem.v - refresh_rate_end_time = %d\n", refresh_rate_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_count = %d\n", cbr_refresh_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0011:begin
if (((((refresh_rate_end_time - refresh_rate_start_time)/`CYCLETIME)/(`RC_0011)) > cbr_refresh_count) && (cbr_refresh_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during normal operation- REFRESH every 896 MCLKs since PCR[13:10]=4'b0011 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - refresh_rate_start_time = %d\n", refresh_rate_start_time);
$write("\n ###! INFO: mem.v - refresh_rate_end_time = %d\n", refresh_rate_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_count = %d\n", cbr_refresh_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0100:begin
if (((((refresh_rate_end_time - refresh_rate_start_time)/`CYCLETIME)/(`RC_0100)) > cbr_refresh_count) && (cbr_refresh_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during normal operation- REFRESH every 1216 MCLKs since PCR[13:10]=4'b0100 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - refresh_rate_start_time = %d\n", refresh_rate_start_time);
$write("\n ###! INFO: mem.v - refresh_rate_end_time = %d\n", refresh_rate_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_count = %d\n", cbr_refresh_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0101:begin
if (((((refresh_rate_end_time - refresh_rate_start_time)/`CYCLETIME)/(`RC_0101)) > cbr_refresh_count) && (cbr_refresh_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during normal operation- REFRESH every 5120 MCLKs since PCR[13:10]=4'b0101 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - refresh_rate_start_time = %d\n", refresh_rate_start_time);
$write("\n ###! INFO: mem.v - refresh_rate_end_time = %d\n", refresh_rate_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_count = %d\n", cbr_refresh_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0110:begin
if (((((refresh_rate_end_time - refresh_rate_start_time)/`CYCLETIME)/(`RC_0110)) > cbr_refresh_count) && (cbr_refresh_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during normal operation- REFRESH every 1408 MCLKs since PCR[13:10]=4'b0110 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - refresh_rate_start_time = %d\n", refresh_rate_start_time);
$write("\n ###! INFO: mem.v - refresh_rate_end_time = %d\n", refresh_rate_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_count = %d\n", cbr_refresh_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
4'b0111:begin
if (((((refresh_rate_end_time - refresh_rate_start_time)/`CYCLETIME)/(`RC_0111)) > cbr_refresh_count) && (cbr_refresh_count != 32'b0)
) begin
$display("\n %0d: *** Error! mem.v Refresh count is less than required during normal operation- REFRESH every 1792 MCLKs since PCR[13:10]=4'b0111 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - refresh_rate_start_time = %d\n", refresh_rate_start_time);
$write("\n ###! INFO: mem.v - refresh_rate_end_time = %d\n", refresh_rate_end_time);
$write("\n ###! INFO: mem.v - cbr_refresh_count = %d\n", cbr_refresh_count);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
// Self Refresh Dram mode
4'b1???:$write("\n %0d: INFO! mem.v SELF REFRESH MODE since PCR[13:10]=4'b1xxx {%0t}\n",Mclocks.cycle_count,$stime);
endcase
cbr_refresh_count = 32'b0; // reset the refresh count
refresh_rate_flag = 1'b1; // set the flag to one, refresh rate change is detected
refresh_change_flag = 1'b0;
end // else clause for refresh_flag
end // if time greater than 50
end
task count_refresh ;
parameter total_2k_refresh = 2048 ; // total of 2k refresh in 32msec
parameter total_2k_cycles = 1600000 ; // total of 2k refresh in 32msec
if ((Mclocks.cycle_count > total_2k_cycles) && ( cbr_refresh_total_count <= total_2k_refresh )) begin
$display("\n *** Error ! mem.v missing refresh in simulation, Total # of cycle in simulation = %d, Total # of refresh = %d",
Mclocks.cycle_count, cbr_refresh_total_count );
end
endtask
//
/******* Monitor/Event-Logger for MCB arbitration cases**********************
* A behavioural monitor, to detect the request sequences made to mcb from
* mmu, rfr or gcb and log the number of times each sequence occured,
* at the end of the test.
***************************************************************************/
reg [2:0] Mreq; // "n" bit register, state of MMU req, "n" clocks ago.
reg [2:0] Mreq_early; // "n" bit register, state of MMU req, "n" clocks ago.
reg [2:0] Mbsy; // "n" bit register, state of MBSY, "n" clocks ago.
reg [2:0] Rreq; // "n" bit register, state of RFR req, "n" clocks ago.
reg Mcyc; // Flag to indicate an mmu cycle is to begin next.
reg Mlate; // Flag to indicate a late mmu cycle is in progress.
reg Mearly; // Flag to indicate an early mmu cycle is in progress.
integer log_chan ; // The channel for "$fwrite" to use.
// and define the string for logfile to point to:
// $DESIGNDIR/ssparc/diag/results/<diag-name>/<diag-mode>/req_seq.log
// Note: The current directory is already the above, when using "run".
`define logfile_name "req_seq.log"
// define valid mmu-req state. This has to be modified to include only
// the valid ones, not just the non-zero case!
`define Valid_mm_req ((`mm_issue_req==1'b1) && (`mm_mreq != 4'h0))
initial begin
// Setup the access to logfile
log_chan = $fopen( `logfile_name );
if ( log_chan == 0 )
$display ("\n\nmem.v: !!!!! Can't open the file: ",
`logfile_name , " !!!!!\n\n");
else
$display ("\n\nmem.v: Output will be sent to: ",
`logfile_name , " \n\n");
Mcyc = 0;
Mlate = 0;
Mearly = 0;
end // initial
/* On posedge of clock, capture the driving signal states */
always @(posedge `SS_SCOPE.rfr_clock)
fork // capture the driving signal states
Mreq[0] = #1 `Valid_mm_req ; // set, if mm_mreq has valid request.
Mreq[1] = #1 Mreq[0] ;
Mreq[2] = #1 Mreq[1] ;
Mreq_early[0] = # 1 `mm_iss_req_early ;
Mreq_early[1] = #1 Mreq_early[0] ;
Mreq_early[2] = #1 Mreq_early[1] ;
Mbsy[0] = #1 `mc_mbsy ;
Mbsy[1] = #1 Mbsy[0] ;
Mbsy[2] = #1 Mbsy[1] ;
Rreq[0] = #1 `rf_rreq_l ;
Rreq[1] = #1 Rreq[0] ;
Rreq[2] = #1 Rreq[1] ;
join // capture the driving signal states
/* On negedge of clock, use the captured info to determine what is what.
* To maintain the required order, more than one always loop plus "intra-
* assignment delays" are used, so that a signal set in an earlier "if"
* won't be seen as valid by another "if" during the same pass of the
* always loop (an example is the "Mcyc").
*/
always @(negedge `SS_SCOPE.rfr_clock)
begin // MMU cycle detect
if ((Mreq[0]==1)&(Mreq[1]==0))
begin // A new request from MMU
if (Mbsy[0]==0)
begin // mcb was in IDLE, so mmu cyc is honored.
Mcyc = #1 1 ;
end // mcb was in IDLE, so mmu cyc is honored.
else
begin // else, either a fake req, or a late req.
if (Mbsy[1]==0)
begin // A late mmu-req, mmu cyc must be honored.
Mcyc = #1 1;
Mlate = #1 1;
end // A late mmu-req, mmu cyc must be honored.
else
begin // Check for early mmu_request
if ((Mbsy[1] === 1) && (Mreq_early[1] === 1))
begin // An early mmu_req, so it must be honored
Mcyc = #1 1;
Mearly = #1 1;
end
else
begin // MMU did a fake req, while mcb was busy
$fdisplay (log_chan,"001: MMU req while MCB was busy...",
"at cycle:%d",`cycle_count);
end // MMU did a fake req, while mcb was busy
end //Check for early mmu request
end // else, either a fake req, or a late req.
end // A new request from MMU
end // MMU cycle detect
always @(negedge `SS_SCOPE.rfr_clock)
if (Mcyc==1)
begin // now that an mmu-cyc is expected to start
if ((Mbsy[0]==0)&(Mbsy[1]==0))
begin // mbsy stayed low, after mmu-cyc detected!
$fdisplay (log_chan,"\n002: MBSY stayed low, after mmu-cyc ",
"detected...at cycle:%d",`cycle_count);
end // mbsy stayed low, after mmu-cyc detected!
if (Mlate==1)
begin // Record the late mmu-cyc
$fdisplay (log_chan,"901: Late MMU cycle granted...",
"at cycle:%d",`cycle_count);
end // Record the late mmu-cyc
else
begin
if (Mearly ==1)
begin
$fdisplay (log_chan,"905: Early MMU cycle requested...",
"at cycle:%d",`cycle_count);
end // Record the early mmu-cyc.
else begin // Record the normal mmu-cyc.
$fdisplay (log_chan,"900: Normal MMU cycle granted...",
"at cycle:%d",`cycle_count);
end // Record the normal mmu-cyc.
end
if ( (Rreq == 3'b000)&&(Mlate==0) )
begin // rfr and/or gcb request pending BEFORE mmu
$fdisplay (log_chan,"902: RFR req were pending",
" before MMU req...at cycle:%d",`cycle_count);
end // rfr request pending BEFORE mmu
if (Rreq == 3'b100)
begin // rfr request asserted SAME cycle as mmu
$fdisplay (log_chan,"903: RFR req were asserted",
" same cyc as MMU req...at cycle:%d",`cycle_count);
end // rfr asserted SAME cycle as mmu
if (Rreq == 3'b110)
begin // rfr request asserted AFTER mmu
$fdisplay (log_chan,"904: RFR req were asserted",
" after MMU req...at cycle:%d",`cycle_count);
end // rfr request asserted AFTER mmu
// Now clear the flags for next round.
Mcyc = #1 0 ;
Mlate = #1 0;
Mearly = #1 0;
end // now that an mmu-cyc is expected to start
/******* end of: Monitor/Event-Logger for MCB arbitration cases***********/
endmodule
| This page: |
Created: | Thu Aug 19 12:02:24 1999 |
| From: |
../../../sparc_v8/system/rtl/mem.v
|