end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_1 - ras_pre_start_time_1) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[1] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_1);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for RAS precharge times - RAS[2]
integer ras_pre_start_time_2
, ras_pre_end_time_2 ;
always @(posedge `mc_ras_l[2]) begin
ras_pre_start_time_2 = $time;
end
always @(negedge `mc_ras_l[2]) begin
ras_pre_end_time_2 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_2 - ras_pre_start_time_2) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[2] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_2);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_2 - ras_pre_start_time_2) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[2] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_2);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_2 - ras_pre_start_time_2) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[2] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_2);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_2 - ras_pre_start_time_2) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[2] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_2);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_2 - ras_pre_start_time_2) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[2] precharge for less than 7.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_2);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_2 - ras_pre_start_time_2) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[2] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_2);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for RAS precharge times - RAS[3]
integer ras_pre_start_time_3, ras_pre_end_time_3 ;
always @(posedge `mc_ras_l[3]) begin
ras_pre_start_time_3 = $time;
end
always @(negedge `mc_ras_l[3]) begin
ras_pre_end_time_3 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_3 - ras_pre_start_time_3) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[3] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_3);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_3 - ras_pre_start_time_3) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[3] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_3);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_3 - ras_pre_start_time_3) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[3] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_3);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_3 - ras_pre_start_time_3) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[3] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_3);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_3 - ras_pre_start_time_3) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[3] precharge for less than 7.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_3);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_3 - ras_pre_start_time_3) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[3] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_3);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for RAS precharge times - RAS[4]
integer ras_pre_start_time_4, ras_pre_end_time_4 ;
always @(posedge `mc_ras_l[4]) begin
ras_pre_start_time_4 = $time;
end
always @(negedge `mc_ras_l[4]) begin
ras_pre_end_time_4 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_4 - ras_pre_start_time_4) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[4] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_4);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_4);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_4 - ras_pre_start_time_4) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[4] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_4);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_4);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_4 - ras_pre_start_time_4) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[4] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_4);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_4);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_4 - ras_pre_start_time_4) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[4] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_4);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_4);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_4 - ras_pre_start_time_4) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[4] precharge for less than 7.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_4);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_4);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_4 - ras_pre_start_time_4) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[4] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_4);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_4);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for RAS precharge times - RAS[5]
integer ras_pre_start_time_5, ras_pre_end_time_5 ;
always @(posedge `mc_ras_l[5]) begin
ras_pre_start_time_5 = $time;
end
always @(negedge `mc_ras_l[5]) begin
ras_pre_end_time_5 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_5 - ras_pre_start_time_5) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[5] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_5);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_5);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_5 - ras_pre_start_time_5) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[5] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_5);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_5);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_5 - ras_pre_start_time_5) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[5] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_5);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_5);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_5 - ras_pre_start_time_5) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[5] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_5);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_5);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_5 - ras_pre_start_time_5) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[5] precharge for less than 7.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_5);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_5);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_5 - ras_pre_start_time_5) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[5] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_5);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_5);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for RAS precharge times - RAS[6]
integer ras_pre_start_time_6, ras_pre_end_time_6 ;
always @(posedge `mc_ras_l[6]) begin
ras_pre_start_time_6 = $time;
end
always @(negedge `mc_ras_l[6]) begin
ras_pre_end_time_6 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_6 - ras_pre_start_time_6) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[6] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_6);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_6);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_6 - ras_pre_start_time_6) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[6] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_6);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_6);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_6 - ras_pre_start_time_6) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[6] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_6);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_6);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_6 - ras_pre_start_time_6) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[6] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_6);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_6);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_6 - ras_pre_start_time_6) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[6] precharge for less than 7.5 cycle6 at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_6);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_6);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_6 - ras_pre_start_time_6) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[6] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_6);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_6);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for RAS precharge times - RAS[7]
integer ras_pre_start_time_7, ras_pre_end_time_7 ;
always @(posedge `mc_ras_l[7]) begin
ras_pre_start_time_7 = $time;
end
always @(negedge `mc_ras_l[7]) begin
ras_pre_end_time_7 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // ras precharge 3.5 cycles
if((ras_pre_end_time_7 - ras_pre_start_time_7) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[7] precharge for less than 3.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_7);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_7);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // ras precharge 4.5 cycles
if((ras_pre_end_time_7 - ras_pre_start_time_7) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[7] precharge for less than 4.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_7);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_7);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // ras precharge 5.5 cycles
if((ras_pre_end_time_7 - ras_pre_start_time_7) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[7] precharge for less than 5.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_7);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_7);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // ras precharge 6.5 cycles
if((ras_pre_end_time_7 - ras_pre_start_time_7) < (6.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[7] precharge for less than 6.5 cycles at 150MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_7);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_7);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // ras precharge 7.5 cycles
if((ras_pre_end_time_7 - ras_pre_start_time_7) < (7.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[7] precharge for less than 7.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_7);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_7);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // ras precharge 8.5 cycles
if((ras_pre_end_time_7 - ras_pre_start_time_7) < (8.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v READ:mc_ras_l[7] precharge for less than 8.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - ras_precharge_start_time = %d\n", ras_pre_start_time_7);
$write("\n ###! INFO: mem.v - ras_precharge_end_time = %d\n", ras_pre_end_time_7);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
/* ---------------------------------------------------------
Check for CAS precharge times
based on Table 5: Page 140 Swift Spec. Rev1.2
--------------------------------------------------------
*/
// Check for CAS precharge times - CAS[0]
integer cas_pre_start_time_0, cas_pre_end_time_0 ;
always @(posedge `mc_cas_l[0]) begin
cas_pre_start_time_0 = $time;
end
always @(negedge `mc_cas_l[0]) begin
cas_pre_end_time_0 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // cas precharge 1.0 cycles
if((cas_pre_end_time_0 - cas_pre_start_time_0) < (1.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[0] precharge for less than 1 cycle at 70-85 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_0);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100, `SPEED125:begin // cas precharge 2.0 cycles
if((cas_pre_end_time_0 - cas_pre_start_time_0) < (2.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[0] precharge for less than 2 cycles at 100-125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_0);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // cas precharge 2.0 cycles for read, should be 4 for write. YS
// if((cas_pre_end_time_0 - cas_pre_start_time_0) < (2.0*`CYCLETIME)
if((cas_pre_end_time_0 - cas_pre_start_time_0) < (1.9*`CYCLETIME) // YS for round error
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[0] precharge for less than 2 cycle at 150 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_0);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175, `SPEED200:begin // cas precharge 3.0 cycles for read, should be 4 for write. YS
if((cas_pre_end_time_0 - cas_pre_start_time_0) < (3.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[0] precharge for less than 3 cycles at 175-200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_0);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for CAS precharge times - CAS[1]
integer cas_pre_start_time_1, cas_pre_end_time_1 ;
always @(posedge `mc_cas_l[1]) begin
cas_pre_start_time_1 = $time;
end
always @(negedge `mc_cas_l[1]) begin
cas_pre_end_time_1 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // cas precharge 1.0 cycles
if((cas_pre_end_time_1 - cas_pre_start_time_1) < (1.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[1] precharge for less than 1 cycle at 70-85 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_1);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100, `SPEED125:begin // cas precharge 2.0 cycles
if((cas_pre_end_time_1 - cas_pre_start_time_1) < (2.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[1] precharge for less than 2 cycles at 100-125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_1);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // cas precharge 2.0 cycles for read, should be 4 for write. YS
// if((cas_pre_end_time_1 - cas_pre_start_time_1) < (2.0*`CYCLETIME)
if((cas_pre_end_time_1 - cas_pre_start_time_1) < (1.9*`CYCLETIME) // for round error YS
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[1] precharge for less than 2 cycle at 150 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_1);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175, `SPEED200:begin // cas precharge 3.0 cycles for read, should be 4 for write. YS
if((cas_pre_end_time_1 - cas_pre_start_time_1) < (3.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[1] precharge for less than 3 cycles at 175-200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_1);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_1);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for CAS precharge times - CAS[2]
integer cas_pre_start_time_2, cas_pre_end_time_2 ;
always @(posedge `mc_cas_l[2]) begin
cas_pre_start_time_2 = $time;
end
always @(negedge `mc_cas_l[2]) begin
cas_pre_end_time_2 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // cas precharge 1.0 cycles
if((cas_pre_end_time_2 - cas_pre_start_time_2) < (1.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[2] precharge for less than 1 cycle at 70-85 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_2);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100, `SPEED125:begin // cas precharge 2.0 cycles
if((cas_pre_end_time_2 - cas_pre_start_time_2) < (2.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[2] precharge for less than 2 cycles at 100-125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_2);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // cas precharge 2.0 cycles for read, should be 4 for write. YS
// if((cas_pre_end_time_2 - cas_pre_start_time_2) < (2.0*`CYCLETIME)
if((cas_pre_end_time_2 - cas_pre_start_time_2) < (1.9*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[2] precharge for less than 2 cycle at 150 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_2);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175, `SPEED200:begin // cas precharge 3.0 cycles for read, should be 4 for write. YS
if((cas_pre_end_time_2 - cas_pre_start_time_2) < (3.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[2] precharge for less than 3 cycles at 175-200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_2);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_2);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
// Check for CAS precharge times - CAS[3]
integer cas_pre_start_time_3, cas_pre_end_time_3 ;
always @(posedge `mc_cas_l[3]) begin
cas_pre_start_time_3 = $time;
end
always @(negedge `mc_cas_l[3]) begin
cas_pre_end_time_3 = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // cas precharge 1.0 cycles
if((cas_pre_end_time_3 - cas_pre_start_time_3) < (1.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[3] precharge for less than 1 cycle at 70-85 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_3);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100, `SPEED125:begin // cas precharge 2.0 cycles
if((cas_pre_end_time_3 - cas_pre_start_time_3) < (2.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[3] precharge for less than 2 cycles at 100-125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_3);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // cas precharge 2.0 cycles for read, should be 4 for write. YS
// if((cas_pre_end_time_3 - cas_pre_start_time_3) < (2.0*`CYCLETIME)
if((cas_pre_end_time_3 - cas_pre_start_time_3) < (1.9*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[3] precharge for less than 2 cycle at 150 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_3);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175, `SPEED200:begin // cas precharge 3.0 cycles for read, should be 4 for write. YS
if((cas_pre_end_time_3 - cas_pre_start_time_3) < (3.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v mc_cas_l[3] precharge for less than 3 cycles at 175-200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_precharge_start_time = %d\n", cas_pre_start_time_3);
$write("\n ###! INFO: mem.v - cas_precharge_end_time = %d\n", cas_pre_end_time_3);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // for speed_select
end // for scan_operation
end // check for ras precharge time
/* -------------------------------------------------------
Check for write enable (mwe_l) setup time before cas
going low
Check for hold time after cas going active
-------------------------------------------------------
*/
integer write_enable_bfr_cas_start_time,
write_enable_hold_cas_start_time,
write_enable_bfr_cas_end_time,
write_enable_hold_cas_end_time;
reg write_enable_flag ;
reg write_hold_flag ;
initial begin
write_enable_flag = 1'b0 ;
write_hold_flag = 1'b0;
end
always @(negedge `mc_mwe_l) begin
if ((`mc_cas_l[3:0] === 4'b1111) && (~write_enable_flag)) begin
write_enable_bfr_cas_start_time = $time ;
write_enable_flag = 1'b1;
end
end
always @(negedge `mc_cas_l[3] or negedge `mc_cas_l[2] or negedge `mc_cas_l[1] or negedge `mc_cas_l[0]) begin
if (write_enable_flag) begin
write_enable_bfr_cas_end_time = $time;
write_enable_hold_cas_start_time = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70:begin // Write enable before cas active time 1.0 cycle
if ((write_enable_bfr_cas_end_time - write_enable_bfr_cas_start_time) < (1.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v write enable before cas active for less than 1 cycle at 70MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - write_enable_bfr_cas_start_time = %d\n", write_enable_bfr_cas_start_time);
$write("\n ###! INFO: mem.v - write_enable_bfr_cas_end_time = %d\n", write_enable_bfr_cas_end_time);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED85,`SPEED100,`SPEED125:begin // Write enable before cas active time 2.0 cycles
if ((write_enable_bfr_cas_end_time - write_enable_bfr_cas_start_time) < (2.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v write enable before cas active for less than 2 cycles at 85-125 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - write_enable_bfr_cas_start_time = %d\n", write_enable_bfr_cas_start_time);
$write("\n ###! INFO: mem.v - write_enable_bfr_cas_end_time = %d\n", write_enable_bfr_cas_end_time);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150,`SPEED175,`SPEED200:begin // Write enable before cas active time 3.0 cycles
if ((write_enable_bfr_cas_end_time - write_enable_bfr_cas_start_time) < (3.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v write enable before cas active for less than 3 cycles at 150-200 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - write_enable_bfr_cas_start_time = %d\n", write_enable_bfr_cas_start_time);
$write("\n ###! INFO: mem.v - write_enable_bfr_cas_end_time = %d\n", write_enable_bfr_cas_end_time);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // end of speed select
write_enable_flag = 1'b0 ; // reset the flag
write_hold_flag = 1'b1; // set the hold flag
end // for scan_operation
end // check for flag
end
always @(posedge `mc_mwe_l) begin
if ( write_hold_flag) begin
write_enable_hold_cas_end_time = $time;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85, `SPEED100:begin // Write enable hold cas active time 2.0 cycles
if ((write_enable_hold_cas_end_time - write_enable_hold_cas_start_time) < (2.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v write enable hold cas active for less than 2 cycles at 70-100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_start_time = %d\n", write_enable_hold_cas_start_time);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_end_time = %d\n", write_enable_hold_cas_end_time);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // Write enable hold cas active time 3.0 cycles
if ((write_enable_hold_cas_end_time - write_enable_hold_cas_start_time) < (3.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v write enable hold cas active for less than 3 cycles at 125 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_start_time = %d\n", write_enable_hold_cas_start_time);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_end_time = %d\n", write_enable_hold_cas_end_time);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // Write enable hold cas active time 4.0 cycles
if ((write_enable_hold_cas_end_time - write_enable_hold_cas_start_time) < (4.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v write enable hold cas active for less than 4 cycles at 150 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_start_time = %d\n", write_enable_hold_cas_start_time);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_end_time = %d\n", write_enable_hold_cas_end_time);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175, `SPEED200:begin // Write enable hold cas active time 5.0 cycles
if ((write_enable_hold_cas_end_time - write_enable_hold_cas_start_time) < (5.0*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v write enable hold cas active for less than 5 cycles at 150 MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_start_time = %d\n", write_enable_hold_cas_start_time);
$write("\n ###! INFO: mem.v - write_enable_hold_cas_end_time = %d\n", write_enable_hold_cas_end_time);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // end of speed select
write_hold_flag = 1'b0; // reset the hold flag
end // for scan_operation
end // check for flag
end
// Check for cas before ras refresh
integer cas_bfr_ras_start_time,
cas_bfr_ras_end_time_bank0,
cas_bfr_ras_end_time_bank1;
integer ras_refresh_start_time_bank0,
ras_refresh_start_time_bank1,
ras_refresh_end_time_bank0,
ras_refresh_end_time_bank1;
integer cbr_refresh_count,
cbr_refresh_total_count,
cbr_refresh_standby_count ;
integer refresh_rate_start_time,
refresh_rate_end_time;
reg standby_asserted_flag ;
reg cas_bfr_ras_flag_bank0 ;
reg cas_bfr_ras_flag_bank1 ;
reg refresh_change_flag ;
initial begin
cas_bfr_ras_flag_bank0 = 1'b0 ;
cas_bfr_ras_flag_bank1 = 1'b0 ;
cbr_refresh_count = 32'b0 ;
cbr_refresh_total_count = 32'b0 ;
standby_asserted_flag = 1'b0 ;
ras_refresh_start_time_bank0 = 0 ;
ras_refresh_start_time_bank1 = 0 ;
ras_refresh_end_time_bank0 = 0 ;
ras_refresh_end_time_bank1 = 0 ;
end
//always @(negedge `mc_cas_l[3:0]) begin
always @(negedge `mc_cas_l[0]) begin
if ((`mc_ras_l[7:0] === 8'hFF) && (~cas_bfr_ras_flag_bank0) && (~cas_bfr_ras_flag_bank1)) begin
cas_bfr_ras_start_time = $time;
cas_bfr_ras_flag_bank0 = 1'b1 ;
cas_bfr_ras_flag_bank1 = 1'b1 ;
// $display("\n INFO: mem.v - cas_bfr_ras detected = %d\n", cas_bfr_ras_start_time);
if ((refresh_change_flag == 1'b1) && (cbr_refresh_count == 32'b1)) begin
refresh_rate_start_time = $time ;
end
cbr_refresh_count = cbr_refresh_count + 1 ;
cbr_refresh_total_count = cbr_refresh_total_count + 1 ;
if (standby_asserted_flag) begin // in standby mode refresh was detected)
// $display("\n INFO: mem.v - cas_bfr_ras detected during standby mode = %d\n", $time);
cbr_refresh_standby_count = cbr_refresh_standby_count + 1 ;
end
end
end // wait for ras to go low
// Check for bank 0
//always @(negedge {`mc_ras_l[6], `mc_ras_l[4], `mc_ras_l[2], `mc_ras_l[0]} )begin
always @(negedge `mc_ras_l[0] )begin
if (cas_bfr_ras_flag_bank0) begin
cas_bfr_ras_end_time_bank0 = $time ;
ras_refresh_start_time_bank0 = $time ;
if (~Mclocks.scan_operation) begin
case (Msystem.speed_select)
`SPEED70, `SPEED85:begin // cas before ras refresh time 1.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (1.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank0 for less than 1.5 cycles at 70-85MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank0 = %d\n", cas_bfr_ras_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED100:begin // cas before ras refresh time 2.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (2.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank0 for less than 2.5 cycles at 100MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank0 = %d\n", cas_bfr_ras_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED125:begin // cas before ras refresh time 3.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank0 for less than 3.5 cycles at 125MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank0 = %d\n", cas_bfr_ras_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED150:begin // cas before ras refresh time 3.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (3.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank0 for less than 3.5 cycles at 150 {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank0 = %d\n", cas_bfr_ras_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED175:begin // cas before ras refresh time 4.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (4.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank0 for less than 4.5 cycles at 175MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank0 = %d\n", cas_bfr_ras_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
`SPEED200:begin // cas before ras refresh time 5.5 cycles
if ((cas_bfr_ras_end_time_bank0 - cas_bfr_ras_start_time) < (5.5*`CYCLETIME)
) begin
$write("\n %0d: *** Error! mem.v cas_before_ras_refresh bank0 for less than 5.5 cycles at 200MHz {%0t}\n",Mclocks.cycle_count,$stime);
$write("\n ###! INFO: mem.v - cas_bfr_ras_start_time = %d\n", cas_bfr_ras_start_time);
$write("\n ###! INFO: mem.v - cas_bfr_ras_end_time_bank0 = %d\n", cas_bfr_ras_end_time_bank0);
Mclocks.error_count = Mclocks.error_count + 1;
end
end
endcase // end of speed select
cas_bfr_ras_flag_bank0 = 1'b0 ; // reset the flag
end // for scan_operation
end // check for flag
end
// Check for bank 1. Add one extra cycle for bank 1
//always @(negedge {`mc_ras_l[7], `mc_ras_l[5], `mc_ras_l[3], `mc_ras_l[1]} )begin
| This page: |
Created: | Thu Aug 19 12:02:22 1999 |
| From: |
../../../sparc_v8/system/rtl/mem.v
|