wire q;
Mflipflop_1 GReg_1_1(q,d,mclk,Gnd) ;
endmodule
//----------------------------------------------------------------------------
// "Half-clock Delay Register" module uses both ss_clock and anti-phase
// (1/2 period delayed) version of it. It hase one input (in) and generates
// 2 outputs:
// - ofb: 1 ss_clock period delayed, registered output to be
// used as feedback term for sync'd set/reset type use
// (Like that of module "S_sr_ff" above".
// - out: The ANDed result of 'ofb' and the output of the register
// clocked from anti-phase clock. The net effect is:
// 0->1 edge is 1.5 clocks delayed from "in".
// 1->0 edge is 1.0 clocks delayed from "in".
// This allows "High-asserted" signals to be "asserted" on a-phase
// clock (ie on neg-edge of ss_clock).
// To use with a "Low-asserted" signal like RAS, the "in" must be
// designed as a "High-asserted" signal, then the "out" should be
// inverted (or make a new module, where out = out_half & out_one ).
//
module HDReg
(out, ofb, in, ss_clock, ss_dclk);
output out
; // combo output
output ofb
; // 1 ss_clock delayed output
input in
;
input ss_clock
; // The ssparc system clock
input ss_dclk
; // 1/2 period delayed clock
wire out_half
; // 0.5 clk delayed from 'ofb' (1.5 clks from 'in')
wire Gnd
; assign Gnd
= 1'b0;
GReg1 InReg (ofb, in, ss_clock, Gnd);
GReg1 OReg_half (out_half, ofb, ss_dclk, Gnd);
assign out = ofb & out_half ;
endmodule
//----------------------------------------------------------------------------
// This is based on "HDReg", but mimics the "S_sr_ff" (see above for
// both of these modules). So, it has 2 inputs 'set' and 'res', acting
// as sync'd set & reset inputs with respect to ss_clock. The output
// 'out' behaves as follows:
// - Set to "1", 2 clocks after "set" is sampled asserted (hi) on
// a 0->1 transition of ss_clock.
// - Reset to "0", 1.5 clocks after "res" is sampled asserted (hi)
// on a 0->1 transition of ss_clock.
// Reset has priority over Set.
//
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module S_sr_HDff
(out, set, res, ss_clock, ss_dclk);
output out
;
input set
, res
; // High active set/reset inputs.
input ss_clock
; // The ssparc system clock
input ss_dclk
; // 1/2 period delayed clock
wire ofb
, in
;
wire Gnd
; assign Gnd
= 1'b0;
assign in = ((ofb|set)&(~res));
HDReg HDff(out, ofb, in, ss_clock, ss_dclk);
endmodule
This page: |
Created: | Thu Aug 19 12:00:19 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/mem_cells.v
|