/******************************************************************************/
/* */
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/******************************************************************************/
// @(#)rl_mcb_lgc.v 1.55 10/20/93
/****************************************************************************
* rl_mcb_lgc.v
*
* Description:
* This module contains the logic necessary to generate RAS/CAS and
* other memory signals in correct sequence plus the logic to control
* the RAM address muxes (defined in row_col_mux.v, module Col_Row_Addr)
* and the RAM to SingleSPARC internal data-bus datapath (defined
* in dpc.v, module DPC_Core).
* This module is mainly controlled by the outputs from the state-machine
* module (rl_mcb_sm).
*
* Refer to SingleSPARC Hardware Spec, section 2.7.3 for block diagram
* and more information.
*
* Dependencies:
* defines.v mem_cells.v
*
*
****************************************************************************/
![[Up: rl_mcb mcb_lgc]](v2html-up.gif)
module rl_mcb_lgc
(
mcas_l, mras_l, moen_l, mwen_l, simm32_sel,
mc_mstb_l, mc_mbsy,
mc_dpct, curr_st, cyc_reg, odat_hld, hld_mm_pa,
col_en, s_blk, ld_ct, mode_ct, inc_ct, rf_ack_l,
mc_refresh, pdm_ready,
gaddr_hld, sel_hi_row, sel_row, sel_gr_page, sel_default,
gr_s_blk, gr_mode_ct, gr_inc_ct,
s_reply, aen, incr_w_p_reply, afx_to, prom_p_reply, dly_bsy,
afx_rst_page_vld, am_gnt_l, am_cstb_l, am_read,
falcon_exists, am_wm, mm_sbae_0,
mm_issue_req, mm_issue_req2, mm_mreq, mm_page,
mm_pa28, mm_pa27, mm_pa26, mm_pa25, mm_pa00, mm_pa01, mm_pa02,
rf_rreq_l, rf_cbr,
ss_clock, ss_dclk, rst, sp_sel, sp_sel_1, sp_sel_2, precharge_early_0,
precharge_early_1,
mm_rf_cntl_3, mm_issue_req_early,
sync_t0, p_reply, pcic_p_reply, mm_fb_req, mm_fb_page, valid_l, cas_cyc,
am_gnt_l_oen
);
output [3:0] mcas_l;
output [7:0] mras_l; /* 4 DRAM bank.*/
output moen_l;
output mwen_l;
output mc_mstb_l, mc_mbsy;
output [5:0] mc_dpct; /* DPC control bus to DPC_Core (dpc.v). */
// IIe note : curr_st and cyc_reg are 9 bit and 7 bits. See below.
output [8:0] curr_st; /* From L_St storage flops.*/
output [6:0] cyc_reg; /* From cycle-type storage flops.*/
output odat_hld; /* Reg first 32bit of data to RAM.*/
output [1:0] hld_mm_pa; /* hold sigs for MMU addr regs.*/
output col_en;
output s_blk;
output ld_ct;
output mode_ct;
output inc_ct ;
output rf_ack_l ; /* Acknowledge to RFR. */
output mc_refresh; /* refresh signal to mmu. */
output pdm_ready; /* ready to stop clock. */
output gaddr_hld; /* gaddr hold signal. */
output sel_hi_row; /* gaddr hi-row sel . */
output sel_row; /* gaddr row sel. */
output sel_gr_page; /* gaddr gpage sel. */
output sel_default; /* DRAM row addr sel. */
output gr_s_blk; /* */
output gr_mode_ct; /* */
output gr_inc_ct; /* */
output s_reply; /* */
output aen; /* */
output [2:0] incr_w_p_reply; /* fifo info. to mmu */
output afx_to; /* */
output dly_bsy; /* to select reg. address */
output afx_rst_page_vld; // reset page valids in mmu
output am_gnt_l; // Falcon bus grant
output valid_l; // Falcon data valid strobe
output cas_cyc; // Falcon enable column address
output am_gnt_l_oen; // This is the address output enable
// for the IIe
input am_cstb_l; // Falcon bus request
input am_read; // Falcon requests read when high
input falcon_exists; // Falcon exists
input [1:0] am_wm; // Falcon word mask bits.
input mm_sbae_0;
input [1:0] prom_p_reply; // p_reply for PROM programming.
input mm_issue_req; // Valid-request from MMU.
input mm_issue_req2; // Valid-request from MMU.
input [3:0] mm_mreq;
input mm_page;
input mm_pa28, mm_pa27;
input mm_pa26, mm_pa25, mm_pa00, mm_pa01, mm_pa02;
/* MMU adress bits needed in MCB decodes.*/
input rf_rreq_l;
input rf_cbr;
input ss_clock; /* The 40MHz, system clock.*/
input ss_dclk; /* The anti-phase (1/2 per delayed) clock.*/
input rst; /* Main RESET input.*/
input simm32_sel; // if 1, for double density simm; else for single density simm.
input sp_sel; // 40MHz ("0") or 50MHz ("1") select pin.
input sp_sel_1; // MHz ("0") or MHz ("1") select pin.
input sp_sel_2; // for 150Mhz - 200Mhz
input precharge_early_0;
input precharge_early_1;
// input power_down_mode; //
input mm_rf_cntl_3; //
input mm_issue_req_early; //
input sync_t0;
input [1:0] p_reply;
input [1:0] pcic_p_reply;
input mm_fb_req;
input mm_fb_page;
// wire for graphics
wire sync_t1;
wire sync_t2;
wire fifo_full;
wire dead_cyc;
wire read_single;
// patch for warning
// assign mras_l[7:4] = 4'hf;
// assign mcas_l[3:2] = 2'h3;
wire Gnd = 1'b0;
// IIe note : The next_st and cyctype is increased by one bit to
// support the Falcon initiated cycles. next_st is now
// 9 bits and cyctype is 7 bits. All Falcon initiated
// cycles are indicated by the MSB of these two registers.
// The same apply to curr_st and cyc_reg.
wire [8:0] next_st; /* To L_St storage flops.*/
wire [6:0] cyctype; /* To cycle-type storage flops.*/
wire mbsy ; /* to the MBSY ff.*/
wire mstb_l ; /* to the MSTB ff.*/
wire qpa27, qpa26, qpa25, qpa02;
/* register outs of MMU address bits.*/
wire pa27, pa26, pa25, pa02;
/* static MMU address bits.*/
wire cas_en; /* enable from st_mach to CAS logic.*/
wire cas0_en; /* enable to CAS0 s_sr_ff.*/
wire cas1_en; /* enable to CAS1 s_sr_ff.*/
wire cas2_en; /* enable to CAS2 s_sr_ff.*/
wire cas3_en; /* enable to CAS3 s_sr_ff.*/
wire cas_dis; /* disable to CAS s_sr_ff.*/
wire [3:0] qcas; /* registered output from s_sr_ff.*/
wire oen_en; /* enable to OEN s_sr_ff.*/
wire oen_dis; /* disable to OEN s_sr_ff.*/
wire qoen; /* registered output from s_sr_ff.*/
wire wen_en; /* enable to WEN s_sr_ff.*/
wire wen_dis; /* disable to WEN s_sr_ff.*/
wire qwen; /* registered output from s_sr_ff.*/
wire ras0_en; /* enable to RAS0 s_sr_ff.*/
wire ras1_en; /* enable to RAS1 s_sr_ff.*/
wire ras2_en; /* enable to RAS2 s_sr_ff.*/
wire ras3_en; /* enable to RAS3 s_sr_ff.*/
wire ras4_en; /* enable to RAS4 s_sr_ff.*/
wire ras5_en; /* enable to RAS5 s_sr_ff.*/
wire ras6_en; /* enable to RAS6 s_sr_ff.*/
wire ras7_en; /* enable to RAS7 s_sr_ff.*/
wire ras_en_0; /* enable from st_mach to RAS logic.*/
wire ras_en_1; /* enable from st_mach to RAS logic.*/
wire ras_dis; // Indicates disable to RAS to page register.
wire ras0_dis; /* disable to RAS0,2,4,6 s_sr_ff.*/
wire ras1_dis; /* disable to RAS1,3,5,7 s_sr_ff.*/
wire [7:0] qras; /* registered output from s_sr_ff.*/
wire [7:0] qras_simm32; /* registered output from s_sr_ff.*/
wire is_page; /*The page-detect from 'ispage' in 'mcb_sm'.*/
wire pa25_flag;
//wire pa25_flag_delay;
//wire pa25_flag_input;
// IIe additions :
wire cas_cyc_en; // Enable the low address request.
wire cas_cyc_dis; // Disable low address request.
wire valid_l_en; // Enable data strobe.
wire valid_l_dis; // Disable data strobe.
wire precharge_p;
wire precharge_0_p;
wire precharge_1_p;
// wire precharge = PRECHARGE;
// remove hold
// GReg1 ffh_pre_0(precharge_0_p, precharge_early_0, ss_clock, Gnd );
// GReg1 ffh_pre_1(precharge_1_p, precharge_early_1, ss_clock, Gnd );
Mflipflop_noop_1 ffh_pre_0(precharge_0_p, precharge_early_0, ss_clock );
Mflipflop_noop_1 ffh_pre_1(precharge_1_p, precharge_early_1, ss_clock );
// assign precharge_p = (precharge_0_p & ~pa25) | (precharge_1_p & pa25);
assign precharge_p = (precharge_0_p ) | (precharge_1_p );
wire [1:0] cas_dec;
wire [1:0] wr5_dec;
wire [2:0] rmw_dec;
wire [2:0] bus_dec;
wire [2:0] p_reply_dec;
wire am_gnt;
wire afx_rst_page_vld;
wire am_req = (mm_sbae_0 & falcon_exists & ~am_cstb_l) ;
// wire am_gnt_l = ~am_gnt ;
Mflipflop_noop_1 ffh_amgntreg(am_gnt_l, ~am_gnt, ss_clock);
wire mm_afx_read; //
wire mm_lst_cyc_afx; // IIe note : The mm_lst_cyc_afx defines the last cycle
// was a Falcon request. The MCB arbiter uses this signal
// to determine granting the bus to MMU or Falcon.
// IIe note : The command strobe and am_read is sampled on ss_clock during the first
// two phases of g_clk
GRegr freql(mm_afx_req, am_req, ss_clock, sync_t2, rst);
GRegr frrdl(mm_afx_read, am_read, ss_clock, sync_t2, rst);
// IIe note : Register the Falcon grant for the next bus arbitration.
wire mm_not_fcyc = rst | ((cyc_reg[6] != 1'b1) & (cyc_reg!=`NONE));
S_sr_ff ffsr_fc_lst(mm_lst_cyc_afx, am_gnt, mm_not_fcyc, ss_clock);
// IIe note : The the internal tri-state enable for the memory address bus.
wire am_gnt_oen;
assign am_gnt_l_oen = ~am_gnt_oen;
S_sr_ff ffsr_am_gnt_l_oen(am_gnt_oen, am_gnt, cas_cyc_dis, ss_clock);
/* Instansiate the state machine module (rl_mcb_sm.v) */
/*=================================================================*/
rl_mcb_sm mcb_sm (curr_st, next_st, cyc_reg, cyctype, mbsy, mstb_l,
is_page,
cas_dec, wr5_dec, rmw_dec, bus_dec,
mm_issue_req, mm_issue_req2,
mm_mreq, mm_page, rf_rreq_l,
rf_cbr, ss_clock, rst, sp_sel, sp_sel_1,
sp_sel_2, precharge_p,
mm_rf_cntl_3, mm_issue_req_early,
sync_t0, sync_t1, sync_t2, fifo_full,
dead_cyc, read_single, mm_fb_req, mm_fb_page,
mm_afx_req, mm_afx_read, am_gnt,
afx_rst_page_vld, am_gnt_l, ras_dis,
prom_wr_bsy, mm_lst_cyc_afx, pa25_flag);
/* Assert "hold" pin of the GRegX parts that are used to hold the
MMU address or data (both in MCB & DPC) only when next cycle is
not "L1_CHECK". Otherwise "hold" is asserted to early if MMU request
was a "late-request" and addr/data is not captured.
( exhibited in bug 97/98, when MMU and RFR are both runing ). */
/*=================================================================*/
wire hld_mm ;
wire hld_mm_cas ;
assign hld_mm = mc_mbsy & (curr_st != `L1_CHECK ) & (curr_st != `L3_G_RAS02);
assign hld_mm_cas = mc_mbsy & (curr_st != `L1_CHECK ) & (curr_st != `L3_G_RAS04);
/* Produce latched version of the needed MMU address bits, using D-flops.
This is done by using the non-registered value while busy is low,
and the registered value after busy goes to 1.*/
/*==================================================================*/
GReg1 ffh_pa02(qpa02, mm_pa02, ss_clock, hld_mm_cas );
GReg1 ffh_pa25(qpa25, mm_pa25, ss_clock, hld_mm );
GReg1 ffh_pa26(qpa26, mm_pa26, ss_clock, hld_mm );
GReg1 ffh_pa27(qpa27, mm_pa27, ss_clock, hld_mm );
assign pa02 = (hld_mm ? qpa02 : mm_pa02);
assign pa25 = (hld_mm ? qpa25 : mm_pa25);
assign pa26 = (hld_mm ? qpa26 : mm_pa26);
assign pa27 = (hld_mm ? qpa27 : mm_pa27);
// generate aen & s_reply[1]
// ==================================================================
wire gwrt2;
wire gwrt1;
wire aen_en, aen_dis;
// wire s_reply_en, s_reply_dis;
// wire s_reply_0_en, s_reply_0_dis, s_reply_1_en, s_reply_1_dis;
wire grdtn;
assign gwrt2 = (curr_st==`L3_GWRT2);
assign gwrt1 = (curr_st==`L3_GWRT1);
// GReg1 ffh_gwrt2_reg(gwrt2_n, gwrt2, ss_clock, Gnd );
// remove hold
// GReg1 ffh_gwrt1_reg(gwrt1_n, gwrt1, ss_clock, Gnd );
// GReg1 ffh_gwrt1_n_reg(gwrt1_n_n, gwrt1_n, ss_clock, Gnd );
Mflipflop_noop_1 ffh_gwrt1_reg(gwrt1_n, gwrt1, ss_clock );
Mflipflop_noop_1 ffh_gwrt1_n_reg(gwrt1_n_n, gwrt1_n, ss_clock );
assign grdtn = (curr_st==`L3_GRDTN);
// GReg1 ffh_grdtn_reg(grdtn_n, grdtn, ss_clock, Gnd );
// following is changed to use GWRPX , GWRHX, GRDPX, GRDHX.
assign aen_en = (rst==1'b0) && (((`G_REQ) &&
~fifo_full && ~dead_cyc && sync_t0 &&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK))) ||
((curr_st==`L3_SYNC) &&
~fifo_full && ~dead_cyc && sync_t0 &&
(`GWRPX || `GWRHX || `GRDPX || `GRDHX))
||
(curr_st==`L3_GWRT3)||
(curr_st==`L3_GRDT6)||(curr_st==`L3_GRDTC)||
(curr_st==`L3_GRDTI));
assign aen_dis = (rst==1'b1) ||
(curr_st==`L3_GRDT3) || (gwrt1_n_n && ~aen_en)||
(curr_st==`L3_GWRT6) ||
(curr_st==`L3_GRDT9) || (curr_st==`L3_GRDTF) ||
(curr_st==`L3_GRDTL);
S_sr_ff ffsr_aensrff(aen, aen_en, aen_dis, ss_clock);
// II note : New signal for Falcon interface. This is the low address (column address) enable
// signal.
assign cas_cyc_en = (rst==1'b0) && (
((curr_st==`L3_G_RAS02) && (cyc_reg == `FDWR8N) && sync_t0 &&
(sp_sel_1 == 1'b0) && sp_sel_2 == 1'b0) ||
((curr_st==`L3_G_RAS03) && (cyc_reg == `FDWR8N) && sync_t0) ||
((curr_st==`L3_G_RAS04) && (cyc_reg == `FDRD8N) && sync_t0)
//((curr_st==`L3_G_RAS03) && (cyc_reg == `FDWR8N) && sync_t0 && (sp_sel_2 == 1'b0)) ||
//((curr_st==`L3_G_RAS04) && (cyc_reg == `FDWR8N) && sync_t0) ||
//((curr_st==`L3_G_RAS04) && (cyc_reg == `FDRD8N) && sync_t0 && (sp_sel_2 == 1'b0)) ||
//((curr_st==`L3_G_RAS05) && (cyc_reg == `FDRD8N) && sync_t0)
) ;
// L3_G_RAS01X is last precharge state, set lo_addr high on the next cycle.
assign cas_cyc_dis = (rst==1'b1) || (((curr_st==`L3_G_WAIT1) || (curr_st==`L3_G_WAIT2))
&& sync_t2);
S_sr_ff ffsr_casc_srff(cas_cyc, cas_cyc_en, cas_cyc_dis, ss_clock);
// s_reply[0] active during write, s_reply[1] active for both read and write.
// since read is 2 cycle, s_reply for read will not be enabled and disabled @ same time
// s_reply is alof simpler
/*************************************************************************************************
assign s_reply_0_en = (rst==1'b0) && (((`G_REQ)&& ~fifo_full && ~dead_cyc && sync_t0 &&
(`G_PAGE) && (`MM_RD8|`MM_RD16|`MM_RD32)&&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK))) ||
(((cyc_reg==`GRD8P)||(cyc_reg==`GRD16P)||
(cyc_reg==`GRD32P)) &&
~fifo_full && ~dead_cyc && sync_t0 &&
(curr_st==`L3_SYNC)) ||
(curr_st==`L3_GRDT6) || (curr_st==`L3_GRDTC) ||
(curr_st==`L3_GRDTI) ||
(((cyc_reg==`GRD8H)||(cyc_reg==`GRD16H)||
(cyc_reg==`GRD32H)) &&
(curr_st==`L3_GROT3))
);
assign s_reply_0_dis = (rst==1'b1) ||
(curr_st==`L3_GRDT3) || (curr_st==`L3_GRDT9) ||
(curr_st==`L3_GRDTF) || (curr_st==`L3_GRDTL);
S_sr_ff ffsr_sreply_0_srff(s_reply[0], s_reply_0_en, s_reply_0_dis, ss_clock);
assign s_reply_1_en = (rst==1'b0) && (((`G_REQ)&& ~fifo_full && ~dead_cyc && sync_t0 &&
(`G_PAGE) &&
(`MM_WR4|`MM_WR8|`MM_WR2|`MM_WR1|`MM_RD8|
`MM_WR16|`MM_RD16|`MM_RD32)&&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK))) ||
(((cyc_reg==`GWR8P)||(cyc_reg==`GWR4P)||
(cyc_reg==`GWR2P)||(cyc_reg==`GWR1P)||
(cyc_reg==`GRD8P)||(cyc_reg==`GWR16P)||
(cyc_reg==`GRD16P)||(cyc_reg==`GRD32P)) &&
~fifo_full && ~dead_cyc && sync_t0 &&
(curr_st==`L3_SYNC)) ||
(curr_st==`L3_GROT3) ||
(curr_st==`L3_GWRT3) || (curr_st==L3_GWRTC) ||
(curr_st==`L3_GRDT6)||(curr_st==`L3_GRDTC)||
(curr_st==`L3_GRDTI)
);
assign s_reply_1_dis = (rst==1'b1) || ((gwrt1_n_n ) && ~s_reply_1_en) ||
(curr_st==`L3_GRDT3) || (curr_st==`L3_GRDT9) ||
(curr_st==`L3_GRDTF) || (curr_st==`L3_GRDTL) ||
(curr_st==`L3_GWRT6) || (curr_st==L3_GWRTF);
S_sr_ff ffsr_sreply_1_srff(s_reply[1], s_reply_1_en, s_reply_1_dis, ss_clock);
*************************************************************************************************/
/* below is for AFX 1.0 *************************************************************************
assign s_reply_0_en = (rst==1'b0) && (((`G_REQ)&& ~fifo_full && ~dead_cyc && sync_t0 &&
(`G_PAGE) && (`MM_WR4|`MM_WR8|`MM_WR2|`MM_WR1|`MM_WR16)&&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK))) ||
(((cyc_reg==`GWR8P)||(cyc_reg==`GWR4P)||
(cyc_reg==`GWR2P)||(cyc_reg==`GWR1P)||
(cyc_reg==`GWR16P)) &&
~fifo_full && ~dead_cyc && sync_t0 &&
(curr_st==`L3_SYNC)) ||
(curr_st==`L3_GWRT3) || (curr_st==L3_GWRTC) ||
(((cyc_reg==`GWR8H)||(cyc_reg==`GWR4H)||
(cyc_reg==`GWR2H)||(cyc_reg==`GWR1H)||
(cyc_reg==`GWR16H)) &&
(curr_st==`L3_GROT3))
);
assign s_reply_0_dis = (rst==1'b1) || (gwrt1_n_n && ~s_reply_0_en) ||
(curr_st==L3_GWRTF) || (curr_st==`L3_GWRT6);
S_sr_ff ffsr_sreply_0_srff(s_reply[0], s_reply_0_en, s_reply_0_dis, ss_clock);
assign s_reply_1_en = (rst==1'b0) && (((`G_REQ)&& ~fifo_full && ~dead_cyc && sync_t0 &&
(`G_PAGE) &&
(`MM_WR4|`MM_WR8|`MM_WR2|`MM_WR1|`MM_RD8|
`MM_WR16|`MM_RD16|`MM_RD32)&&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK))) ||
(((cyc_reg==`GWR8P)||(cyc_reg==`GWR4P)||
(cyc_reg==`GWR2P)||(cyc_reg==`GWR1P)||
(cyc_reg==`GRD8P)||(cyc_reg==`GWR16P)||
(cyc_reg==`GRD16P)||(cyc_reg==`GRD32P)) &&
~fifo_full && ~dead_cyc && sync_t0 &&
(curr_st==`L3_SYNC)) ||
(curr_st==`L3_GROT3) ||
(curr_st==`L3_GWRT3) || (curr_st==L3_GWRTC) ||
(curr_st==`L3_GRDT6)||(curr_st==`L3_GRDTC)||
(curr_st==`L3_GRDTI)
);
assign s_reply_1_dis = (rst==1'b1) || ((gwrt1_n_n || grdtn_n) && ~s_reply_1_en) ||
(curr_st==`L3_GWRT6) || (curr_st==L3_GWRTF);
S_sr_ff ffsr_sreply_1_srff(s_reply[1], s_reply_1_en, s_reply_1_dis, ss_clock);
************************************************************************************************/
// IIe note : This is the data strobe (valid_l) when the Falcon is the AFX
// bus master. (valid_l is enabled when low)
assign valid_l_dis = (rst==1'b1) || sync_t0 && ((curr_st==`L3_G_RDP02A) ||
(curr_st==`L3_G_RDP02B) || (curr_st==`L3_G_RDM01));
//assign valid_l_en = (rst==1'b0) && sync_t0 && (curr_st==`L3_G_RDP01);
//assign valid_l_en = (rst==1'b0) && sync_t0 && ((curr_st==`L3_G_RDP01 && ({sp_sel_2,sp_sel_1} != 2'b11)) ||
//curr_st == `L3_G_CAS175 || curr_st == `L3_G_RDP175);
assign valid_l_en = (rst==1'b0) && sync_t0 && ((curr_st==`L3_G_RDP01 && (sp_sel_2 != 1'b1)) ||
curr_st == `L3_G_CAS175 || curr_st == `L3_G_RDP175);
S_sr_ff ffsr_valid_srff(valid_l, valid_l_dis, valid_l_en, ss_clock);
/* Decode and generate wen_en & wen_dis. */
/*==================================================================*/
// IIe note : The Falcon will make another request during the valid_l cycle. Therefore
// the a current cycle type must be used to ensure a successful completion of
// the current cycle while the cyc_reg is being changed.
wire [6:0] lst_afx_cyc_type;
Mflipflop_7 lst_cyc(lst_afx_cyc_type, cyc_reg, ss_clock, ~sync_t2);
assign wen_dis = (rst==1'b1) ||
(curr_st==`L3_WRP03A) || (curr_st==`L3_WRP03B) ||
(curr_st==`L3_WRP03C) ||
(gwrt1_n_n && ~wen_en) ||
(curr_st==`L3_GWRT6) ||
(((curr_st==`L3_G_RDP02A) || (curr_st==`L3_G_RDP02B)) && sync_t2) ||
//((curr_st==`L3_G_CAS175) && (cyc_reg==`FDRD8N) && sync_t0) ||
//((curr_st==`L3_G_RDM01) && (sp_sel_2 != 1'b1) && (cyc_reg==`FDRD8N) && sync_t0);
((curr_st==`L3_G_RDM01) && (cyc_reg==`FDRD8N) && sync_t0);
// add L3_RMWP02X to remove parity long path. This reg. control signal to mux_sel[3:0]
// now, wen for rmw asserted 1 cycle earlier.
// add graphics control
// following use GWRPX & GWRHX for timing.
assign wen_en = (rst==1'b0) && (
(((`MM_REQ)&&(`IS_PAGE)&&(`MM_WR4|`MM_WR8|`MM_WR16)&&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK)) && (bus_dec == 3'b000)) ||
((curr_st==`L3_WRP01) && (bus_dec == 3'b000)) || (curr_st==`L3_WRP04) ||
((curr_st==`L3_RMWP02X) && (rmw_dec== 3'b000)) ||
( (curr_st==`L3_RAS04)&&
((cyc_reg==`DWR8N)||(cyc_reg==`DWR4N)||(cyc_reg==`DWR16N)) ) ) ||
(((`G_REQ)&&(`G_PAGE)&& ~fifo_full && ~dead_cyc &&
~(`MM_RDX)&& sync_t0 &&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK)) ) ||
(((curr_st==`L3_SYNC)&&sync_t0&&~fifo_full&&~dead_cyc) &&
`GWRPX) ||
(curr_st==`L3_GWRT3) ||
((curr_st==`L3_GROT3) && `GWRHX)) ||
(sync_t0 && (curr_st==`L3_G_RAS01) && (cyc_reg==`FDWR8N)) ||
( sync_t0 && (cyc_reg==`FDWR8N) && (curr_st==`L3_G_RDM01))
//( sync_t0 && (cyc_reg==`FDWR8N) && (curr_st==`L3_G_RDM01) && ({sp_sel_2,sp_sel_1} != 2'b11)) ||
//( sync_t0 && (cyc_reg==`FDWR8N) && (curr_st==`L3_G_CAS175) && ({sp_sel_2,sp_sel_1} == 2'b11))
);
// IIe note : During a Falcon write cycle, the DRAM output is disabled.
/* Generate WEN from a sync'd Set/Reset FF. */
/*==================================================================*/
S_sr_ff ffsr_wensrff(qwen, wen_en, wen_dis, ss_clock);
assign mwen_l = ~qwen;
/* Decode and generate oen_en & oen_dis. */
assign oen_dis = (rst==1'b1) ||
(curr_st==`L3_RDP02A) || (curr_st==`L3_RDP02B) ||
(curr_st==`L3_RDM01) || (curr_st==`L3_RDM04) ||
(curr_st==`L3_RDM07) || (curr_st==`L3_RMWP01) ||
(curr_st==`L3_WRP03A) || (curr_st==`L3_WRP03B) ||
(curr_st==`L3_CBR05) || (curr_st==`L3_WRP03C) ||
// IIe additions :
( sync_t0 && (
(curr_st==`L3_G_RDP02A) || (curr_st==`L3_G_RDP02B) ||
(curr_st==`L3_G_RDM01))) ||
((curr_st==`L3_SRF01) && !mm_rf_cntl_3) ;
assign oen_en = (rst==1'b0) && (
((`MM_REQ)&&(`IS_PAGE) &&
(!(`MM_WR4|`MM_WR8|`MM_WR16))&& ~sp_sel_1 && ~sp_sel_2 && ~dead_cyc&&
( (curr_st==`L1_IDLE) || (curr_st==`L1_CHECK))) ||
((curr_st==`L3_RDP01S) && ~dead_cyc) ||
(((curr_st==`L3_RDM02)|| (curr_st==`L3_RDM05) ||
(curr_st==`L3_RDM08)) && (cas_dec== 2'b00)) ||
((cyc_reg!=`DWR8N)&&(cyc_reg!=`DWR4N)&&(cyc_reg!=`DWR16N)&&
(curr_st==`L3_RAS05)&& (sp_sel_1==1'b0) && (sp_sel_2 == 1'b0)) ||
// IIe additions :
(sync_t0 && (curr_st==`L3_G_RDM02) && (cyc_reg==`FDRD8N)) ||
((cyc_reg==`FDRD8N)&&(curr_st==`L3_G_RAS05)&&sync_t0) ||
(((cyc_reg==`FDRD8N)&&({sp_sel_2, sp_sel_1, sp_sel} == 3'b000)) &&
((curr_st==`L3_G_RDP01) && sync_t0))
) ;
/* Generate OEN from a sync'd Set/Reset FF. */
/*==================================================================*/
S_sr_ff ffsr_oensrff(qoen, oen_en, oen_dis, ss_clock);
assign moen_l = ~qoen;
/* Decode and generate cas_en & cas_dis. */
/*==================================================================*/
// IIe note : The cas disable now includes 6 Falcon states (L3_G's).
assign cas_dis = (rst==1'b1) ||
(curr_st==`L3_RDP02A) || (curr_st==`L3_RDP02B) ||
(curr_st==`L3_RDM01) || (curr_st==`L3_RDM04) ||
(curr_st==`L3_RDM07) || (curr_st==`L3_RMWP01) ||
(curr_st==`L3_WRP03A) || (curr_st==`L3_WRP03B) ||
(curr_st==`L3_CBR05) || (curr_st==`L3_WRP03C) ||
// IIe additions :
( sync_t0 && (
(curr_st==`L3_G_RDP02A) || (curr_st==`L3_G_RDP02B) ||
(curr_st==`L3_G_RDM01))) ||
((curr_st==`L3_SRF01) && !mm_rf_cntl_3) ;
// sub. previous logic with (curr_st==L3_RAS01X) && (rmw_dec== 3'b000) with
// (curr_st==L3_RAS01X) to send cas 1 cycle earlier in cbr.
assign cas_en = (rst==1'b0) && (
((`MM_REQ)&&(`IS_PAGE) &&
(!(`MM_WR4|`MM_WR8|`MM_WR16))&& ~sp_sel_1 && ~sp_sel_2 && ~dead_cyc&&
( (curr_st==`L1_IDLE) || (curr_st==`L1_CHECK))) ||
((curr_st==`L3_RDP01S) && ~dead_cyc) ||
(((curr_st==`L3_RDM02)|| (curr_st==`L3_RDM05) ||
(curr_st==`L3_RDM08)) && (cas_dec== 2'b00)) ||
(((curr_st==`L3_WRP02) || (curr_st==`L3_WRP05)) && (wr5_dec== 2'b00)) ||
(((cyc_reg==`CBR)||(cyc_reg==`SREF))&&
(curr_st==`L3_RAS01X) ) ||
((cyc_reg!=`DWR8N)&&(cyc_reg!=`DWR4N)&&(cyc_reg!=`DWR16N)&&
(curr_st==`L3_RAS05)&& (sp_sel_1==1'b0) && (sp_sel_2 == 1'b0)) ||
// IIe additions :
(sync_t0 && (curr_st==`L3_G_RDM02)) ||
//((cyc_reg==`FDRD8N)&&(curr_st==`L3_G_RAS05)&&({sp_sel_2,sp_sel_1}!=2'b11)&&sync_t0) ||
((cyc_reg==`FDRD8N)&&(curr_st==`L3_G_RAS05)&&sync_t0) ||
//((cyc_reg==`FDRD8N)&&(curr_st==`L3_G_RDP01)&&({sp_sel_2,sp_sel_1}==2'b11)&&sync_t0) ||
((((cyc_reg==`FDRD8N)&&({sp_sel_2, sp_sel_1, sp_sel} == 3'b000)) || (cyc_reg==`FDWR8N)) &&
((curr_st==`L3_G_RDP01) && sync_t0))
) ;
// Examine up to here,
/* Decode and generate CAS0 & CAS1.*/
/*==================================================================*/
// sub. previous logic with (curr_st==L3_RAS01X) && (rmw_dec== 3'b000) with
// (curr_st==L3_RAS01X) to send cas 1 cycle earlier in cbr.
assign
cas0_en = simm32_sel ? (
(cas_en == 1'b1) &
//(pa25 == 1'b0) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[1])
|(( pa02 == 1'b0) & (cyc_reg[6] == 1'b0)) /* or a cycle for lo-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
) : (
(cas_en == 1'b1) &
(pa25 == 1'b0) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[1])
|(( pa02 == 1'b0) & (cyc_reg[6] == 1'b0)) /* or a cycle for lo-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
);
assign
cas1_en = simm32_sel ? (
(cas_en == 1'b1) &
//(pa25 == 1'b0) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[0])
|(( pa02 == 1'b1) & (cyc_reg[6] == 1'b0)) /* or a cycle for Hi-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
) : (
(cas_en == 1'b1) &
(pa25 == 1'b0) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[0])
|(( pa02 == 1'b1) & (cyc_reg[6] == 1'b0)) /* or a cycle for Hi-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
);
assign
cas2_en = simm32_sel ? (
(cas_en == 1'b1) &
//(pa25 == 1'b1) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[1])
|(( pa02 == 1'b0) & (cyc_reg[6] == 1'b0)) /* or a cycle for lo-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
) : (
(cas_en == 1'b1) &
(pa25 == 1'b1) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[1])
|(( pa02 == 1'b0) & (cyc_reg[6] == 1'b0)) /* or a cycle for lo-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
);
assign
cas3_en = simm32_sel ? (
(cas_en == 1'b1) &
//(pa25 == 1'b1) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[0])
|(( pa02 == 1'b1) & (cyc_reg[6] == 1'b0)) /* or a cycle for Hi-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
) : (
(cas_en == 1'b1) &
(pa25 == 1'b1) &
( ( mwen_l == 1'b1) /* any non-write cycle.*/
|( cyc_reg == `DWR8N) /* or any 8byte write cycle.*/
|( cyc_reg == `DWR8P)
|( cyc_reg == `DWR16N) /* or any 16byte write cycle.*/
|( cyc_reg == `DWR16P)
|( cyc_reg == `FDRD8N) // Any Falcon request (8 byte)
|(( cyc_reg == `FDWR8N) & am_wm[0])
|(( pa02 == 1'b1) & (cyc_reg[6] == 1'b0)) /* or a cycle for Hi-word. */
) |
((rst==1'b0) && (((cyc_reg==`CBR)||(cyc_reg==`SREF))&&(curr_st==`L3_RAS01X)))
);
S_sr_ff ffsr_cas0srff(qcas[0], cas0_en, cas_dis, ss_clock);
assign mcas_l[0] = ~ qcas[0];
S_sr_ff ffsr_cas1srff(qcas[1], cas1_en, cas_dis, ss_clock);
assign mcas_l[1] = ~ qcas[1];
S_sr_ff ffsr_cas2srff(qcas[2], cas2_en, cas_dis, ss_clock);
assign mcas_l[2] = ~ qcas[2];
S_sr_ff ffsr_cas3srff(qcas[3], cas3_en, cas_dis, ss_clock);
assign mcas_l[3] = ~ qcas[3];
// up to here
// add mc_refresh signal to mmu for page mode detection.
wire ref_en;
wire ref_dis;
wire mc_refresh_virgin;
assign ref_en = ((rst==1'b1) || (curr_st==`L3_CBR01));
assign ref_dis = ((rst==1'b0)&& (curr_st==`L3_CBR07) );
S_sr_ff ffsr_ref_srff(mc_refresh_virgin, ref_en, ref_dis, ss_clock);
assign mc_refresh = mc_refresh_virgin | rst;
/* Decode and generate ras_en & ras_dis. */
/*==================================================================*/
// wire precharge = PRECHARGE;
// assign ras_dis = ((rst==1'b1) ||
// ((NO_PAGE)&&(MM_REQ)&&
// ((curr_st==L1_IDLE)||(curr_st==L1_CHECK))) ||
// ((curr_st==L1_CHECK)&&(!MM_REQ)) ||
// (curr_st==L3_CBR07) ||
// (curr_st==L3_SRF01) ||
// (curr_st==L2_CYCEND) ||
// ((curr_st==L1_IDLE) && (!MM_REQ) &&
// (!RF_REQ ) && (SREF_REQ))
// ||
// (((curr_st==L1_IDLE)||(curr_st==L3_RDP02B) ||
// (curr_st==L3_WRP03B)) && (precharge_early)) ) ;
//
wire pre_pa25;
MflipflopR ffpa25ysun (pre_pa25, mm_pa25, ss_clock, ~mm_issue_req, rst);
assign pa25_flag = simm32_sel ? ((pre_pa25 == mm_pa25) ? 0 : 1 ) : 0;
assign ras0_dis = ((rst==1'b1) ||
((`NO_PAGE)&&(`MM_REQ)&&(pa25 == 1'b0)&&
// changed to solve double ras to single ras pa25 change problem.
// ((`NO_PAGE || ((!`NO_PAGE) && (qpa25 != 1'b0)))&&(`MM_REQ)&&(pa25 == 1'b0)&&
//(((`NO_PAGE) || ((pa25_flag == 1'b1) || (pa25_flag_delay == 1'b1))) &&(`MM_REQ)&&(pa25 == 1'b0)&&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK))) ||
((curr_st==`L1_CHECK)&&(!`MM_REQ)&&
~mm_issue_req_early) ||
(curr_st==`L3_CBR07) ||
((curr_st==`L3_SRF01) && !mm_rf_cntl_3) ||
(curr_st==`L2_CYCEND) ||
((curr_st==`L1_IDLE) && (!`MM_REQ) &&
(!`RF_REQ ) && (`SREF_REQ)) ||
((((curr_st[7]==1'b1) &&
!(curr_st==`L1_CHECK))||(curr_st==`L3_RDP02B) ||
(curr_st==`L3_WRP03B) ) && (precharge_early_0)) ||
((curr_st==`L3_G_RDP02B) && sync_t0) ||
(((curr_st==`L3_G_SYNC) || (curr_st==`L3_G_RAS01)) &&
sync_t0)
) ;
assign ras1_dis = ((rst==1'b1) ||
((`NO_PAGE)&&(`MM_REQ)&&(pa25 == 1'b1)&&
// changed to solve double ras to single ras pa25 change problem.
// ((`NO_PAGE || ((!`NO_PAGE) && (qpa25 != 1'b1))) &&(`MM_REQ)&&(pa25 == 1'b1)&&
//(((`NO_PAGE) || ((pa25_flag == 1'b1) || (pa25_flag_delay == 1'b1)))&&(`MM_REQ)&&(pa25 == 1'b1)&&
((curr_st==`L1_IDLE)||(curr_st==`L1_CHECK))) ||
((curr_st==`L1_CHECK)&&(!`MM_REQ) &&
~mm_issue_req_early) ||
(curr_st==`L3_CBR07) ||
((curr_st==`L3_SRF01) && !mm_rf_cntl_3) ||
(curr_st==`L2_CYCEND) ||
((curr_st==`L1_IDLE) && (!`MM_REQ) &&
(!`RF_REQ ) && (`SREF_REQ))
||
((((curr_st[7]==1'b1) &&
!(curr_st==`L1_CHECK))||(curr_st==`L3_RDP02B) ||
(curr_st==`L3_WRP03B)) && (precharge_early_1)) ||
((curr_st==`L3_G_RDP02B) && sync_t0) ||
(((curr_st==`L3_G_SYNC) || (curr_st==`L3_G_RAS01)) &&
sync_t0)
) ;
// IIe addition :
assign ras_en_0 = ((rst==1'b0)&& ((curr_st==`L3_RAS02) || ((curr_st==`L3_G_RAS02) && sync_t0))) ;
assign ras_en_1 = ((rst==1'b0)&&
( (((curr_st==`L3_RAS02) || ((curr_st==`L3_G_RAS02) && sync_t0)) &&
(cyc_reg !=`CBR)) || (curr_st==`L3_RAS02X) )) ;
assign ras_dis = ras0_dis | ras1_dis;
// was this, changed to stagger refresh
// assign ras_en = ((rst==1'b0)&&
// (curr_st==`L3_RAS02)) ;
// interestingly, was this in tsunami
// ( ((curr_st==L3_RAS02) && (cyc_reg != CBR)) ||
// (curr_st==L3_CBR01))) ;
//
/* Decode and generate RAS[3:0]. */
/*==================================================================*/
assign
ras0_en = ras_en_0 & (
(cyc_reg == `CBR)|({pa27,pa26,pa25} == 3'b000));
assign
ras1_en = ras_en_1 & (
(cyc_reg == `CBR)|({pa27,pa26,pa25} == 3'b001));
assign
ras2_en = ras_en_0 & (
(cyc_reg == `CBR)|({pa27,pa26,pa25} == 3'b010));
assign
ras3_en = ras_en_1 & (
(cyc_reg == `CBR)|({pa27,pa26,pa25} == 3'b011));
assign ras4_en = ras_en_0 & ((cyc_reg == `CBR) |({pa27,pa26,pa25} == 3'b100));
assign ras5_en = ras_en_1 & ((cyc_reg == `CBR) |({pa27,pa26,pa25} == 3'b101));
assign ras6_en = ras_en_0 & ((cyc_reg == `CBR) |({pa27,pa26,pa25} == 3'b110));
assign ras7_en = ras_en_1 & ((cyc_reg == `CBR) |({pa27,pa26,pa25} == 3'b111));
// assign ras0_dis = (ras_dis & (pa25 == 1'b0)) || (rst==1'b1);
// assign ras1_dis = (ras_dis & (pa25 == 1'b1)) || (rst==1'b1);
S_sr_HDff ffhdsr_ras0srff(qras[0], ras0_en, ras0_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras0_simm32_srff(qras_simm32[0], ras0_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[0] = simm32_sel ? ~qras_simm32[0] : ~qras[0];
S_sr_HDff ffhdsr_ras1srff(qras[1], ras1_en, ras1_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras1_simm32_srff(qras_simm32[1], ras1_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[1] = simm32_sel ? ~qras_simm32[1] : ~qras[1];
S_sr_HDff ffhdsr_ras2srff(qras[2], ras2_en, ras0_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras2_simm32_srff(qras_simm32[2], ras2_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[2] = simm32_sel ? ~qras_simm32[2] : ~qras[2];
S_sr_HDff ffhdsr_ras3srff(qras[3], ras3_en, ras1_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras3_simm32_srff(qras_simm32[3], ras3_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[3] = simm32_sel ? ~qras_simm32[3] : ~qras[3];
S_sr_HDff ffhdsr_ras4srff(qras[4], ras4_en, ras0_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras4_simm32_srff(qras_simm32[4], ras4_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[4] = simm32_sel ? ~qras_simm32[4] : ~qras[4];
S_sr_HDff ffhdsr_ras5srff(qras[5], ras5_en, ras1_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras5_simm32_srff(qras_simm32[5], ras5_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[5] = simm32_sel ? ~qras_simm32[5] : ~qras[5];
S_sr_HDff ffhdsr_ras6srff(qras[6], ras6_en, ras0_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras6_simm32_srff(qras_simm32[6], ras6_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[6] = simm32_sel ? ~qras_simm32[6] : ~qras[6];
S_sr_HDff ffhdsr_ras7srff(qras[7], ras7_en, ras1_dis, ss_clock, ss_dclk);
S_sr_HDff ffhdsr_ras7_simm32_srff(qras_simm32[7], ras7_en, ras_dis, ss_clock, ss_dclk);
assign mras_l[7] = simm32_sel ? ~qras_simm32[7] : ~qras[7];
/* The hold signal going to the 32-bit data-registers in the DPC .*/
/*==================================================================*/
assign odat_hld = ~( (rst==1'b1) ||
(curr_st==`L1_RESET) ||
(curr_st==`L1_IDLE) ||
(curr_st==`L1_CHECK) ||
(cyc_reg == `CBR) ||
/* OR whenever were doing pci DMA, don't block lda instructions from
operating properly. All pci related transactions have
bit 8 on! */
curr_st[8] ||
(cyc_reg == `SREF) );
/* The MBUSY and MSTB_L registers .*/
/*==================================================================*/
//remove hold
// GReg1 ffh_mbsyreg(mc_mbsy, mbsy, ss_clock, Gnd);
// GReg1 ffh_mstbreg(mc_mstb_l, mstb_l, ss_clock, Gnd);
//
// GReg1 ffh_mbsydly(dly_bsy, mc_mbsy, ss_clock, Gnd);
Mflipflop_noop_1 ffh_mbsyreg(mc_mbsy, mbsy, ss_clock);
Mflipflop_noop_1 ffh_mstbreg(mc_mstb_l, mstb_l, ss_clock);
Mflipflop_noop_1 ffh_mbsydly(dly_bsy, mc_mbsy, ss_clock);
// for power down mode ready.
wire pdm_bsy;
assign pdm_bsy = (mc_mbsy & !(cyc_reg == `CBR) & !(curr_st==`L1_CHECK)) | ~(p_reply_dec == 3'b000);
//REGWIRE dly_bsy_6; //
//REGR(ffh_mbsydly_6,1,dly_bsy_6,dly_bsy_5,ss_clock,Gnd,rst)
GRegr ffh_mbsydly_1(dly_bsy_1, pdm_bsy, ss_clock, Gnd, rst);
GRegr ffh_mbsydly_2(dly_bsy_2, dly_bsy_1, ss_clock, Gnd, rst);
GRegr ffh_mbsydly_3(dly_bsy_3, dly_bsy_2, ss_clock, Gnd, rst);
GRegr ffh_mbsydly_4(dly_bsy_4, dly_bsy_3, ss_clock, Gnd, rst);
GRegr ffh_mbsydly_5(dly_bsy_5, dly_bsy_4, ss_clock, Gnd, rst);
GRegr ffh_mbsydly_6(dly_bsy_6, dly_bsy_5, ss_clock, Gnd, rst);
// need reset to clear them
//
// GReg1 ffh_mbsydly_1(dly_bsy_1, pdm_bsy, ss_clock, Gnd);
// GReg1 ffh_mbsydly_2(dly_bsy_2, dly_bsy_1, ss_clock, Gnd);
// GReg1 ffh_mbsydly_3(dly_bsy_3, dly_bsy_2, ss_clock, Gnd);
// GReg1 ffh_mbsydly_4(dly_bsy_4, dly_bsy_3, ss_clock, Gnd);
// GReg1 ffh_mbsydly_5(dly_bsy_5, dly_bsy_4, ss_clock, Gnd);
// GReg1 ffh_mbsydly_6(dly_bsy_6, dly_bsy_5, ss_clock, Gnd);
//
// GReg1 ffh_power_downdly_1(dly_pdm_1, power_down_mode, ss_clock, Gnd);
// GReg1 ffh_power_downdly_2(dly_pdm_2, dly_pdm_1, ss_clock, Gnd);
// GReg1 ffh_mm_rf_cntl_3_dly(mm_rf_cntl_3_dly, mm_rf_cntl_3, ss_clock, Gnd);
wire pdm_ready_d;
assign pdm_ready_d = ~(pdm_bsy | dly_bsy_1 | dly_bsy_2 | dly_bsy_3 | dly_bsy_4 |
dly_bsy_5 | dly_bsy_6);
assign pdm_ready = pdm_ready_d;
// assign pdm_err = ((dly_pdm_1 & power_down_mode) |
// (mm_rf_cntl_3_dly & mm_rf_cntl_3)) & mm_issue_req;
/* The signals for Col_Row_Addr module control. */
/*==================================================================*/
assign hld_mm_pa[0] = hld_mm | ( mc_mbsy | mm_issue_req );
assign hld_mm_pa[1] = hld_mm ;
// add graphics control and select.
assign gaddr_hld = hld_mm | gwrt1_n | grdtn;
// gaddr_hld could be replaced by odat_hld
// assign sel_row = (curr_st ==L3_GROT1)|(curr_st ==L3_GROT2)|(curr_st ==L3_GROT3);
assign sel_hi_row = (curr_st ==`L3_GHIT1)|(curr_st ==`L3_GHIT2)|(curr_st ==`L3_GROT3);
assign sel_gr_page = aen & ~sel_hi_row;
assign sel_default = ~sel_gr_page & ~sel_hi_row;
Mux2_1 mx_s_reply_1 (s_reply, 1'b0, 1'b1, sel_gr_page);
// add term aen to select graphics address @ aen
assign col_en = (curr_st != `L3_RAS01)&(curr_st != `L3_RAS02)&
(curr_st != `L3_RAS03)&(curr_st != `L3_RAS04)&
// added on 1-29-97, had to back out for 1.1 changes, now back in 2.0
(curr_st != `L3_RAS03X)&
(curr_st != `L3_RAS01X) & ~aen;
// (curr_st != L3_RAS01X)&(curr_st != L3_RAS04X)&
// (curr_st != L3_RAS04Y);
wire wrp06;
assign wrp06 = (curr_st == `L3_WRP06);
GReg1 ffh_wrp06n(wrp06n, wrp06, ss_clock, Gnd );
assign s_blk = ((curr_st >= `L3_RDM01)&(curr_st <= `L3_RDM09))|
((curr_st >= `L3_RDM03T)&(curr_st <= `L3_RDM09T))|
((curr_st >= `L3_WRP03C)&(curr_st <= `L3_WRP06)) | wrp06n;
// pg3 fix
// assign s_blk = ((curr_st >= `L3_RDM01)&(curr_st <= `L3_RDM09))|
// ((curr_st >= `L3_RDM03T)&(curr_st <= `L3_RDM09T))|
// ((curr_st >= `L3_WRP03C)&(curr_st <= `L3_WRP06)) ;
// what ?
// (((curr_st == L3_WRP03B)|(curr_st == L3_WRP03A))&
// (( cyc_reg == DWR16N)|( cyc_reg == DWR16P)));
| This page: |
Created: | Thu Aug 19 12:00:39 1999 |
| From: |
../../../sparc_v8/ssparc/memif/rtl/rl_mcb_lgc.v
|