/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)ssparc_core.v
***
****************************************************************************
****************************************************************************/
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module ssparc_core
(
// iiddtn goes to turn off caches and tags during iddq test
iiddtn,
// added 4 scan chains
csl_scan_in1,
csl_scan_in2,
csl_scan_in3,
csl_scan_in4,
csl_scan_out1,
csl_scan_out2,
csl_scan_out3,
csl_scan_out4,
tg_strobe,
ss_scan_mode,
csl_scan_mode, // input pin to control scan mode
logic_0,
ss_clock,
standby_req,
ic_standby_f,
dc_standby_w,
reset,
reset_iu,
iu_error,
iu_event,
w_mc_ras_l,
w_mc_cas_l,
w_s_reply,
w_mc_moe_l,
w_mc_mwe_l,
w_simm32_sel,
rl_memif_scan_out,
memif_idle,
w_aen,
w_b_mempar_in,
w_sp_sel,
rfr_clock,
rfr_late,
gclk_1st_phase,
w_p_reply,
mm_bp_dtct,
mm_hold_rst,
// mm_lvl15_int_l, // replaced with any_intrnl_int_l
any_intrnl_int_l, // any level 15 (unmasked)
w_bm_sel,
w_div_ctl,
standby_dsbl_tlb,
w_pci_req_l,
w_ext_int_,
w_ext_int_oe,
w_pci_gnt_l,
w_gclk, // timer clock (div by 4 rfr_clk)
tmr_clk,
w_b_memdata_in,
w_ab_out,
w_mc_memaddr,
ADEnable,
cbeEnable,
PAREnable,
frameEn,
trdyEn,
irdyEn,
stopEn,
devselEn,
perrEn,
serrEnable,
w_ad_out,
w_cbe_out,
w_par_out,
w_frame_l_out,
w_trdy_l_out,
w_irdy_l_out,
w_stop_l_out,
w_devsel_l_out,
w_serr_l_out,
w_perr_l_out,
w_ad_in,
w_cbe_in,
w_par_in,
w_frame_l_in,
w_irdy_l_in,
w_perr_l_in,
w_serr_l_in,
w_trdy_l_in,
w_stop_l_in,
w_devsel_l_in,
sw_rst,
en_sw_rst_nonwd,
en_pci_sw_rst,
pci_slave_mode,
input_reset_l,
pci_rst_pin_in_l,
pci_rst_int_l,
pci_clk,
pci_clk_sync,
pci_clk_sync_,
gclk_sync,
gclk_sync_,
pci_clk_,
b_mem_oen,
w_b_memdata_out,
w_b_mempar_out,
w_rom_addr,
w_rom_oe_l,
w_rom_we_l,
w_rom_cs_l,
pcic_idle, // internal pcic idle.
go_standby, // qualified OR of pin and programmable.
pin_go_standby, // pin from external monitor (if any is there?)
isr_tdi,
last_phi,
next2last_phi,
first_phi,
sboclk );
output [7:0] w_mc_ras_l;
output [3:0] w_mc_cas_l;
input [1:0] w_b_mempar_in;
input [7:0] w_ext_int_;
output [7:0] w_ext_int_oe;
output [1:0] w_b_mempar_out;
output [23:0] w_rom_addr;
input [1:0] w_bm_sel;
input [3:0] w_pci_req_l;
input [31:0] w_ad_in;
input [2:0] w_sp_sel;
input [1:0] w_div_ctl;
output [3:0] w_pci_gnt_l;
output [3:0] w_cbe_out;
output [31:0] w_ad_out;
input [1:0] w_p_reply;
output [11:0] w_mc_memaddr;
output [63:0] w_b_memdata_out;
input [63:0] w_b_memdata_in;
output [14:12] w_ab_out;
input [3:0] w_cbe_in;
output sw_rst;
output en_sw_rst_nonwd;
output en_pci_sw_rst;
input pci_slave_mode;
input input_reset_l;
input pci_rst_pin_in_l;
input csl_scan_in1;
input csl_scan_in2;
input csl_scan_in3;
input csl_scan_in4;
output csl_scan_out1;
output csl_scan_out2;
output csl_scan_out3;
output csl_scan_out4;
input iiddtn;
input tg_strobe;
input ss_scan_mode;
input csl_scan_mode;
input logic_0;
input ss_clock;
input standby_req;
input reset;
input reset_iu;
input rfr_clock;
input rfr_late;
input gclk_1st_phase;
input standby_dsbl_tlb;
input w_gclk;
input tmr_clk;
input w_par_in;
input w_frame_l_in;
input w_irdy_l_in;
input w_perr_l_in;
input w_serr_l_in;
input w_trdy_l_in;
input w_stop_l_in;
input w_devsel_l_in;
input pci_clk;
input pci_clk_sync;
input pci_clk_sync_;
input gclk_sync;
input gclk_sync_;
input pci_clk_;
input isr_tdi;
input last_phi;
input next2last_phi;
input first_phi;
input sboclk;
output ic_standby_f;
output dc_standby_w;
output iu_error;
output iu_event;
output w_s_reply;
output w_mc_moe_l;
output w_mc_mwe_l;
input w_simm32_sel;
output rl_memif_scan_out;
output memif_idle;
output w_aen;
output mm_bp_dtct;
output mm_hold_rst;
output any_intrnl_int_l; // add any_intrnl_int_l replacing mm_lvl15_int_l
output ADEnable;
output cbeEnable;
output PAREnable;
output frameEn;
output trdyEn;
output irdyEn;
output stopEn;
output devselEn;
output perrEn;
output serrEnable;
output w_par_out;
output w_frame_l_out;
output w_trdy_l_out;
output w_irdy_l_out;
output w_stop_l_out;
output w_devsel_l_out;
output w_serr_l_out;
output w_perr_l_out;
input pci_rst_int_l;
output b_mem_oen;
output w_rom_oe_l;
output w_rom_we_l;
output w_rom_cs_l;
output pcic_idle;
output go_standby;
input pin_go_standby;
wire logic_0, logic_1 ; // Constants, driven by cells in misc block
wire afx_rst_page_vld; // reset the page valid bits in the mmu
wire [1:0] w_bm_sel;
// wire falcon_exists = 1'b1;
// Active in the ref_clk cycles when ss_clock is disabled, but not in the
// last sbclk cycle of this period.
wire standby_dsbl_tlb ;
wire mm_lvl15_int_l;
wire any_intrnl_int_l; // from pcic, or's any unmasked level 15
wire enbl_br_fold;
wire sb_ioreq_vld ; // Will be connect to MMU;
wire [31:0] misc; // Data-IN, from pads to DPC
wire [63:0] cache_fill; // Data-IN, from MEMIF to cache
wire [1:0] wb_valid; // Write Buffer valid bits
wire [1:0] mm_fb_size; // MMU Frame buffer size field
wire [7:0] cxr ; // Context from mmu -> caches
/* pcic wires ****************/
wire pci_rst_int_l; // pci reset, synch to pci_clk
wire [3:0] falcon_int; // Interrupt request level (irl) to processor
// include this temporarily for the afx_mon from phoenix
wire am_cstb_l; // transfer request to afx master
wire am_read; // r/w indicator on Falcon transfers
wire [1:0] am_wm; // afx master word mask
wire w_aen; // aen for falcon
wire w_valid_l;
wire w_cas_cyc;
wire w_am_gnt_l;
wire [1:0] pcic_p_reply; // port reply
wire reset;
wire pcic_ifetch;
wire pin_go_standby ; // standby pin to pcic
wire go_standby ; // standby OR to generate standby_req
wire pcic_idle ; // pcic now idle, ok to go into standby
// wires for the IO connections
wire mas_req_out;
// end Ravicad declarations from Ravicad's system.v
wire [63:0] db_out1;
wire [63:0] db_out2;
wire [14:0] pcic_ab_out;
wire pcic_ab_oen;
wire pcic_db_oen;
wire [14:12] memif_ab_out;
wire [1:0] pad_mempar_in;
wire [1:0] memif_mempar, mpar_out1, mpar_out2;
wire [0:11] memif_memaddr_out ;
/* scan connection nets declared here - defines scan chain too*/
wire isr_tdi ;
//wire promif_scan_out ;
//wire m_mmu_cache_scan_out ; // internally connects to tlb->dp_mmu->m_mmu_cache
//wire dccntl_scan_out ;
//wire iccntl_scan_out ;
//wire fprf_scan_out ; // Dan to fill out here
//wire dc_scan_out ;
//wire Miu_scan_out ; // Arthur to fill out here
//wire ic_scan_out ;
//wire rl_memif_scan_out ;
/* */
/***************** IU model ********************************************************/
wire [31:2] iu_epc ;
//wire [31:0] ir_d ;
wire [1:0] size_e;
wire [5:0] iu_asi_e;
// wire [5:0] iu_asi_w ;
wire [31:0] iu_dva_e ;
wire [31:0] iu_dva_e_dc;
wire [31:2] iu_iva_g ;
wire [31:3] icache_adr;
wire [31:14] icache_tag_in;
wire [3:0] iu_bytemarks ;
wire [1:0] fp_fcc ;
wire [63:0] fp_dout_e ;
wire [63:0] ld_fpu_w ;
wire [63:0] dc_do ;
wire [31:0] ld_iu ;
wire [63:0] ic_ibus;
wire [31:0] inst_for_int;
wire [4:3] i_nfillp ;
wire fold_annul_e; // tell FPU that inst in E is to be annuled
wire [1:0] mm_fs_lvl ;
wire [1:0] mm_fs_perr ;
wire [1:0] ic_lvl_f ;
wire [1:0] it_lvl_out ;
wire [1:0] it_lvl_in ;
wire [1:0] iu_sfs_perr;
wire [1:0] iu_sfs_lvl;
wire [2:0] pipe_hold4fpc;
wire pipe_hold4fprf;
wire pipe_hold4mmu_cntl;
wire pipe_hold4mmu_dp;
wire pipe_hold4dc;
wire [1:0] pipe_hold4dc_l;
wire fast_hld_terms;
wire pipe_hold4ic;
wire i_dva_req; // dva -> iva signal for IU
/* synopsys translate_off */
/* synopsys translate_on */
wire dwait_w;
wire dwait_w_for_flush;
wire little_endian;
wire [1:0] ic_perr_f ;
wire [31:0] iu_store_data;
Miu iu(
/******************* IU -> FPU interface signals ******************/
.IU_in_trap4fpu (iu_in_trap4fpu), // Tell FP that IU is trapping
.valid_decode (valid_d), // inst in decode is valid
.fold_annul (fold_annul_e),
.FXACK (fxack), // ack FP exception for FPU
.iu_epc (iu_epc), // D-stage pc
// .in_dec (ir_d), // instruction in D-stage
.hld_dirreg (hld_dirreg), // hold dir reg
.inst_for_fpc (inst_for_int[31:0]), //Input to D stage instruction register
/******************* IU -> MMU interface signals ******************/
// .iu_asi_w (iu_asi_w), // ASI field of instr. in the W-stage
.iu_asi_e (iu_asi_e), // ASI field of instr. in the E-stage
// .iu_sup_inst_f (iu_sup_inst_f), // indicates if Ifetch in supervisor mode
.iu_dva_e (iu_dva_e), // 32-bit virtual addr. bus for data refs
.iu_dva_e_dc (iu_dva_e_dc), // D$'s own copy
.iu_iva_g (iu_iva_g[31:2]), // 30-bit virtual addr. bus for instr. refs
.icache_adr (icache_adr[13:3]), //I cache addr direct to SRAMS
.icache_tag_in (icache_tag_in[31:14]), // I$ for tag compare
.error_mode (iu_error), // a trap occured when traps were disabled
.ld_op_e (ld_op_e), // to dcache,e stage load (exclude ldst and swap)
.ld_op_e_mmu (ld_op_e_mmu), // to mmu,e stage load (exclude ldst and swap)
.ld_op_d (ld_op_d), // to dcache,d stage load (exclude ldst and swap)
.sgnd_ld_e (sgnd_ld_e),
.st_op_e (st_op_e), // to dcache,e stage store
.st_op_e_mmu (st_op_e_mmu), // to mmu,e stage store
.st_op_d (st_op_d), // to dcache,d stage store
.fpu_mem_e (fpu_mem_e), // to fpu,dc, ldf,stf,lddf,stdf,stfsr,&stfq in e stage
.size_e (size_e), // to mmu and dcache, size of mem op in e stage
.iu_sfs_sup (iu_sfs_sup),
.iu_sfs_perr (iu_sfs_perr),
.iu_sfs_xerr (iu_sfs_xerr),
.iu_sfs_mmiss (iu_sfs_mmiss),
.iu_sfs_iae (iu_sfs_iae),
.iu_sfs_sbe (iu_sfs_sbe),
.iu_sfs_sto (iu_sfs_sto),
.iu_sfs_prtct (iu_sfs_prtct),
.iu_sfs_priv (iu_sfs_priv),
.iu_sfs_lvl (iu_sfs_lvl),
// .it_hit_f_mmu (it_hit_f_mmu), // MMU's copy buffered in IU
// moved this signal to ic_cntl
.iu_mm_iacc_wp_exc_d (iu_mm_iacc_wp_exc_d),
/******************* IU -> DC interface signals ******************/
.src3 (iu_store_data[31:0]),
.select_IU_DOUT (select_IU_DOUT),
.select_FP_DOUT (select_FP_DOUT),
.sel_ldstb_1 (sel_ldstb_1),
.byte_mark0_e (iu_bytemarks[0]), // 4-bit field indicating byte written
.byte_mark1_e (iu_bytemarks[1]),
.byte_mark2_e (iu_bytemarks[2]),
.byte_mark3_e (iu_bytemarks[3]),
.IU_in_trap (iu_in_trap),
.IU_in_trap4dc (IU_in_trap4dc),
.little_endian (little_endian), // to rl_cc block
/******************* IU -> IC interface signals ******************/
.sel_last_gen (sel_last_gen),
.sel_recirc (sel_recirc),
.iu_iflush_e (iu_iflush_e), // a FLUSH instr. in the W-stage
.force_dva (nforce_dva_f),
.enbl_fetch (enbl_fetch),
/******************* FPU -> IU interface signals ******************/
.FHOLD (fp_fhold), // fpu hold input
.FEXC (fp_fexc), // fpu exception
.pfcc (fp_fcc), // fpu condition codes (2-bits)
.pfccv (fp_fccv), // fpu CC's are valid
/******************* MMU -> IU interface signals ******************/
.ic_mem_par (ic_perr_f), // from ic, fault status:memory parity error
.mm_fs_perr (mm_fs_perr), // from mmu - xlate perr
.mm_fs_iae (mm_fs_iae), // from mmu, fault status:invalid address error
.mm_fs_xerr (mm_fs_xerr), // from mmu, fault status:xlation error
.mm_fs_mmiss (mm_fs_mmiss), // from mmu, fault status:mmu miss exec
.mm_fs_sbe (mm_fs_sbe), // from mmu, fault status:sbus error
.mm_fs_sto (mm_fs_sto), // from mmu, fault status:sbus timeout error
.mm_fs_sptct (mm_fs_sptct), // from mmu, fault status:protection violation
.enbl_br_fold (enbl_br_fold),
.mm_dacc_err_w (mm_dacc_err), // from mmu,w cycle a parity error on data memory access
.mm_dacc_exc_w (mm_dacc_exc), // from mmu,w cycle a data access exception
.mm_dacc_mmu_miss_w (mm_dacc_mmu_miss), // from mmu, data access MMU miss
.mm_dacc_wp_w (mm_dacc_wp_w),
.ic_force_ifill_g (ic_force_ifill_g), // from ic, assert stb_en for ic to do non mem xaxtion
.mm_istat_avail (mm_istat_avail),//from mmu, xlation done, cache state available.ack icache miss
.mm_icache_enbl (mm_icache_enbl),
/******************* DC -> IU interface signals ******************/
.ld_iu (ld_iu[31:0]), // 64-bit data load bus from herbulator to IU
.dc_shold (dc_shold), // Ic asserts to hold to iu pipe, when wb full
.dt_hit_w (dt_hit_w), // dtag hit in w stage
.enbl_dtag_match_w (enbl_dtag_match_w),//qualify dt_hit_w,asserted in ld_op_w & st_op_w
.dwait_w (dwait_w), //dc request iu to wait in W stage for cache filled
.dwait_w_for_flush (dwait_w_for_flush),
.i_dva_req (i_dva_req),
/******************* IC -> IU interface signals ******************/
.mm_fs_lvl (ic_lvl_f[1:0]),
.ic_idle (ic_idle),
.ic_ibus (ic_ibus[63:0]), // 64-bit instr. bus from I-cache to IU
.it_hit_f (it_hit_f), // from icache, tag hit in f stage
.enbl_itag_match_f (enbl_itag_match_f),//qualify it_hit_f
.ic_sup_only (ic_sup_only_f), // supervisory execute only
.iwait_f (iwait_f), // no icache data is available in this cycle
.imiss_in_progress (imiss_in_progress),//asserted in the 2nd cycle of a ic miss,till the last
.start_itag_inv (start_itag_inv),
// fill write cycle( for cached filled) or the bypass cycle
// (for noncache)
.i_nfillp (i_nfillp[4:3]),// from ic, address for fill write
// Input to be added to IU (or spec change?):
// .ic_rl_pipe (ic_rl_pipe), // release pipeline (valid when IC_MHOLD active)
/******************* pins -> IU interface signals ******************/
.IRL (falcon_int), // 4-bit interrupt request lines
/****************/
// .BOOT (logic_0),
/******************* IU interface signals ******************/
.pipe_hold4fpc (pipe_hold4fpc),
.pipe_hold4fprf (pipe_hold4fprf),
.pipe_hold4mmu_cntl (pipe_hold4mmu_cntl),
.pipe_hold4mmu_dp (pipe_hold4mmu_dp),
.pipe_hold4dc (pipe_hold4dc),
.pipe_hold4dc_l (pipe_hold4dc_l),
.fast_hld_terms (fast_hld_terms),
.pipe_hold4ic (pipe_hold4ic),
.ihold_d1 (ihold_d1), // for MMU perf counters
.dhold_d1 (dhold_d1),
.did_fetch (did_fetch),
.ss_scan_mode (ss_scan_mode), // indicates scan mode
// .SCANDIN (iu_scandin), // scan data input
.ss_clock (ss_clock), // removing buffered clock bus
.ss_reset (reset_iu), // active HIGH reset
/***** more miscellaneous stuff *****/
.iu_event (iu_event), // IU special event to clock controller
.iu_sup_mode (iu_sup_mode),
// .input_clock (input_clock),
// .input_clock_buf (input_clock_buf),
.Miu_scan_in (),
.Miu_scan_out ()
);
/* */
/***************** FPU model *********************************************/
fpufpc ssparc_fpu(
.ss_clock (ss_clock), // removed ss_clock bus to fpu
.ss_reset (reset),
.ld_fpu_w (ld_fpu_w[63:0]), // D-cache data output bus
.inst_for_int (inst_for_int[31:0]), // Input to D-stage instr. register
.iu_epc (iu_epc), // tap from IU E-stage pc (30-bits)
.hld_dirreg (hld_dirreg), // decode load control signal
.ext_valid_decode (valid_d), // from IU, valid instr in D_IR
.fold_annul_e(fold_annul_e), // inst in E is annuled
.ext_flush (iu_in_trap4fpu), // IU in trap
.ext_hold (pipe_hold4fpc[2:0]), // same as iu_pipe_hold
.ext_hold1 (pipe_hold4fprf), // duplicate of ext_hold
.ext_fxack (fxack), // from IU, ack FP exception for FPU
.ext_fhold (fp_fhold), // to iu, FHOLD
.ext_fexc (fp_fexc), // to iu, fp exceptions
.ext_fcc (fp_fcc), // to iu, 2 bit fpu conditions code
.ext_fccv (fp_fccv), // to iu, fcc are valided. deasserted with fcmp
.fhold_d1(fhold_d1), // delayed ext_fhold used by perf counter
.fhold_fqfull_d1(fhold_fqfull_d1), // delayed fq_full used by perf counter
.fload_wait_w(fload_wait_w), // FPop is currently executing, and might trap
.fp_dout_e (fp_dout_e[63:0]), // to iu, fp data out, at e stage of fpst
.ss_scan_mode (ss_scan_mode),
.fprf_scan_out (),
.fp_fpc_scan_in ()
);
/* */
/***************** Cache RAM models ****************************************/
// These 2 don't go any where presently. They are needed for asi tag reads.
// Remember to connect them to rl_dc_cntl.
wire [`dt_msb:0] dt_dout_w;
wire [`it_msb:0] it_dout_f;
wire [`dc_msb:3] dc_dva_e ; // Address out of the D$ cntl
wire [`dc_dblksize_msb:2] dc_adr_in;
wire [7:0] dc_be;
wire [1:0] dp_perr ;
wire [1:0] dp_perr_buf ;
wire [7:0] it_cntx_out, dt_cntx_out ;
wire [7:0] dt_cntx_in, it_cntx_in ;
wire [4:0] dt_acc_in, dt_acc_out ;
wire [63:0] dc_di, ic_di ;
wire [4:0] dt_at ;
wire it_acc_out;
wire [31:`log2_icachesize] it_din ;
wire [31:`log2_dcachesize] dt_din ;
wire [1:0] dc_hld ; // Hold for {LSW,MSW} (sic) of DCache data-in reg
wire [1:0] ic_hld ; // Hold for {LSW,MSW} (sic) of ICache data-in reg
wire [1:0] ic_be ;
// TEMPORARY
assign icache_adr[31:14] =
icache_tag_in[31:14];
mr_caches caches(
.logic_0 (logic_0),
.dc_hld (dc_hld[1:0]),
.it_hit_f (it_hit_f), // to iu, itag hit in f stage
.ic_hld (ic_hld[1:0]),
.dt_hit_w (dt_hit_w), // to iu, dtag hit in w stage
.it_index3 (it_index3), // iu_asi_e is context_flush or user flush
.it_index2 (it_index2), // iu_asi_e is region, context or user flush
.it_index1 (it_index1), // iu_asi_e is segment, region, context, or user flush
.it_flush (it_flush), // iu_asi_e is page, seg,region,context,or user flush
.it_flush_user (it_flush_user),// iu_asi_e is user flush
.it_flush_user_cntx (it_flush_user_cntx),//iu_asi_e is user or context flush
.dt_index3 (dt_index3), // iu_asi_e is context_flush or user flush
.dt_index2 (dt_index2), // iu_asi_e is region, context or user flush
.dt_index1 (dt_index1), // iu_asi_e is segment, region, context, or user flush
.dt_flush (dt_flush), // iu_asi_e is page, seg,region,context,or user flush
.dt_flush_user (dt_flush_user),// iu_asi_e is user flush
.dt_flush_user_cntx (dt_flush_user_cntx), //iu_asi_e is user or context flush
.ic_adr_in (icache_adr[`ic_msb:3]),
.ic_power_down (ic_power_down),// icache power down
.dc_power_down (dc_power_down),// dcache power down
.iiddtn (iiddtn), // turn off the caches and tags during iddq test
.it_cntx_in (it_cntx_in[7:0]),
.it_cntx_out (it_cntx_out[7:0]),
.dc_do (dc_do[63:0]), // to herbulator, dcache data out
.dc_di (dc_di[63:0]), // from cc, dcache data in
.dt_at (dt_at[4:0]), // dtag, access tag? supervisor, read/write/execute
.dt_acc_in (dt_acc_in[4:0]),
.dt_acc_out (dt_acc_out[4:0]),
.it_acc_in (it_acc_in),
.it_acc_out (it_acc_out),
.it_lvl_out (it_lvl_out[1:0]),
.it_lvl_in (it_lvl_in[1:0]),
.dt_cntx_in (dt_cntx_in[7:0]),
.dt_cntx_out (dt_cntx_out[7:0]),
.ic_wle (ic_wle), // from cc, icache word line enable
.ic_be (ic_be[1:0]), // from cc, icache bypass enable
.it_din (it_din[31:`log2_icachesize]),// itag data in
.dt_din (dt_din[31:`log2_dcachesize]),// dtag data in
.it_be_vb (it_be_vb),
.it_be (it_be),
.it_val_in (it_val_in),
.ic_do (ic_ibus[63:0]),// to iu, instruction
.ic_di (cache_fill[63:0]),
.it_dout_f (it_dout_f), // for asi tag read, itag data out in f stage
.it_val_f (it_val_f), // itag valid bit
.tg_strobe (tg_strobe), // ram test itag strobe
.ic_scan_in (),
.scan_mode (ss_scan_mode),
.dt_dout_w (dt_dout_w), // for asi read, dtag data out in w
.dt_val_w (dt_val_w), // dtag valid bit
.dc_scan_out (),
.dt_be (dt_be), // dtag data write enable for dt_din
.dt_be_vb (dt_be_vb), // dtag write valid bit
.dc_dtv_din (dc_dtv_din),
.dc_adr_in (dc_dva_e[`dc_msb:3]), // Insert iu_dva_e[3].
.dc_wle (dc_wle), // dcache write enable
.dc_be (dc_be[7:0]), // dcache bypass enable
.clkl_i (ss_clock), // supply main ss_clock
.clkr_i (ss_clock),
.clkl_d (ss_clock),
.clkr_d (ss_clock)
) ;
/********* MMU model ********************************************************/
wire [30:0] mm_pa ;
wire [30:0] mm_sb_pa ;
wire [11:3] mm_caddr ;
wire [3:0] mm_mreq ;
wire [31:0] sb_ioa ;
wire [3:0] mm_rfr_cntl ;
wire [1:0] mm_sbsize ;
wire [2:0] sb_sbslot ;
wire [3:0] sb_ioreq ;
wire [2:0] sb_errsize ;
wire mm_sbae_0 ;
//
// PROM speed signal- new
wire [3:0] mm_rom_module_speed ;
wire mm_go_standby ; // programmable standby
wire turn_off_standby ; // reset to programmable standby
wire [4:0] mm_sscr_ba8 ;
wire [1:0] sb_err_type;
wire [1:0] mm_mem_dbg ; // memory access debug signals
wire [2:0] p_reply_dec; // fifo decrementer output
// i've connected pipe_hold4mmu_cntl to the iu_pipe_hold port
// here. i also have one ready for the DP. (pipe_hold4mmu_dp).
// -- arthur
mmu ssparc_mmu(
// .mm_ifetch (mm_ifetch), // ifetch from sbus (EPROM)
.enbl_br_fold (enbl_br_fold), // enable for branch folding
.mm_misc2cf (mm_misc2cf), // misc to cfb for pio/asi etc..
.mm_issue_req_early (mm_issue_req_early), // signal to memif of pending issue_req
.mm_misc2cf_2nd (mm_2nd_wd), // misc to cfb for pio/asi etc..
.mm_mdata_en0 (mc_mdata_en0), // to memif,tri-state enable for DPC word 0
.mm_dacc_err (mm_dacc_err), // to IU data access parity error
.mm_dacc_exc (mm_dacc_exc), // to IU data access exception
.mm_dacc_miss (mm_dacc_mmu_miss), // to IU,data access MMU miss
.mm_dacc_wp (mm_dacc_wp_w), // to IU,data access watchpoint
.mm_bp_dtct (mm_bp_dtct), // to Misc, MMU breakpoint detect
.mm_hold_rst (mm_hold_rst), // to misc,hold watchdog reset
.mm_pa (mm_pa), // to memif only ,output of Physical Address
.cxr (cxr), // to d$,i$,output of current context
.mm_caddr (mm_caddr), // to memif,cas address (virtual)
.mm_mreq (mm_mreq), // to memif,memory request type to mcb
.mm_fb_req (mm_fb_req), // to memif,FB memory request
.mm_fb_size (mm_fb_size), // to memif,FB request size
.mm_fb_page (mm_fb_page), // to memif,FB request pg_md
.mm_page (mm_page), // to memif,dram page mode indicator
// .mm_slock (mm_slock), // iu requires exclusive use of sbus
.mm_oddpar (mm_oddpar), // reflects PCR control, select odd/even parity
.mm_parity_en (mm_parity_en), // reflects PCR control, select parity enabled
.mm_rfr_cntl (mm_rfr_cntl), // reflects PCT control, select refresh rate
// .mm_sb_pa (mm_sb_pa), // to sbc, give the translated address PA to sbc
// .mm_iodaten (mm_iodaten), // to sbc,indicates data to be driven from sbc
// .mm_iostben (mm_iostben), // to sbc,assert stb_en for sbc
// .mm_pa_valid (mm_pa_valid), // to sbc,PA valid
// .mm_sbsize (mm_sbsize), // to sbc, size field indicating operation size
// .mm_cpcyc_stb_l (mm_cpcyc_stb_l), // to sbc,output indicating that data & addr. valid
// .mm_cpsb_wrt (mm_cpsb_wrt), // to sbc,output indicating CP to SB write.
// .mm_sb_pe (mm_sb_pe), // to sbc,indicates a parity error during an IO DMA
// .mm_sbae (mm_sbae), // to sbc, reflects PCR sbus arbitration enable
.mm_sbae_0 (mm_sbae_0), // to sbc, reflects PCR sbus arbitration enable
.mm_rom_module_speed (mm_rom_module_speed),
// .mm_sscr_ba8 (mm_sscr_ba8), // to sbc, indicates which slot support 8 byte transfer
.mm_lvl15_int_l (mm_lvl15_int_l), // Level-15 interrupt output
.mm_issue_req (mm_issue_req), // to memif, issue memory request
.mm_issue_req2 (mm_issue_req2), // to memif, issue memory request
.misc (misc[31:0]), // bidir mdata bus
.precharge_early_0(precharge_early_0), // to memif, early precharge for bank0
.precharge_early_1(precharge_early_1), // to memif, early precharge for bank1
.mm_istat_avail (mm_istat_avail), // to ic,acknowledge the imiss
.mm_dstat_avail (mm_dstat_avail), // to dc,acknowlege to dmiss
.mm_dcdaten_in (mm_dcdaten_in), // to memif & dc, strobe of 0 word of write buffer to misc
.mm_icdaten (mm_icdaten), // to dc, enable IC to misc bus
.mm_dct_daten (mm_dct_daten), // to dc, enable DC Tag to misc bus
.mm_wbstb (mm_wbstb), // to memif & dc, strobe of 0 word of write buffer to misc
.mm_wbsel1 (mm_wbsel1), // to memif & dc, strobe of 1 word of write buffer to misc
.mm_mem_dbg (mm_mem_dbg), // to memif, memory debug signals
.pcic_ifetch (pcic_ifetch), // to pcic, boot control if correct bm_sel
.mm_go_standby (mm_go_standby), // to pcic, allows automatic standby
/***** Inputs *****************************************************************/
// Keep these two signals at the top level for more flexibility
// for now tie falcon_exists to active and boot_mode to 0
// .falcon_exists (1'b1),
.afx_rst_page_vld (afx_rst_page_vld),
.bm_sel (w_bm_sel),
.turn_off_standby (turn_off_standby), // turns off automatic standby: JKocol
.w_sp_sel (w_sp_sel), // Speed select (for mmu status)
.w_div_ctl (w_div_ctl[1:0]), // Divide by cntl (mmu status)
.ic_idle (ic_idle), // tell mmu ic is in idle state
.mc_refresh (mc_refresh), // from memif,D ram refresh on
.ic_miss_sustain (ic_miss_sustain), // active 1 cycle after ic_miss
.it_hit_f (it_hit_f_mmu), //itag hit in f stage
.ic_miss_or_part (ic_miss_or_part),
.ic_miss_and_part (ic_miss_and_part),
.dc_miss_or_part (dc_miss_or_part), // as above, for dc
.dc_miss_and_part (dc_miss_and_part), // as above, for dc
.dt_hit_w (dt_hit_w), // as above, for dc
.dc_miss_sustain (dc_miss_sustain), // active 1 cycle after dc_miss
// .sb_ioreq_vld (sb_ioreq_vld), // from sbc,IO request valid
.invalid_wb_entry (invalid_wb_entry), // from dc, st trap
.wb_valid (wb_valid), // from dc, write buffer valid
.wb0_hold_lo (wb0_hold_lo), // from dc write buffer cntl,
.wb1_hold_lo (wb1_hold_lo), // from dc write buffer cntl
.wb2_hold_lo (wb2_hold_lo), // from dc write buffer cntl
.wb3_hold_lo (wb3_hold_lo), // from dc write buffer cntl
.wb_1_sel (wb_1_sel), // from dc write buffer cntl
.wb_2_sel (wb_2_sel), // from dc write buffer cntl
.wb_3_sel (wb_3_sel), // from dc write buffer cntl
.misc_in (misc[31:0]),
.iu_pipe_hold (pipe_hold4mmu_cntl), // IU pipe is being held this cycle
.pipe_hold4mmu_dp (pipe_hold4mmu_dp), // IU pipe hold for dp_mmu block
.iu_size_e (size_e[1:0]), // of size of iu mem op in e stage
.iu_asi_e (iu_asi_e), // of asi in e stage
.ld_op_e (ld_op_e_mmu), // indicates read req pending
.st_op_e (st_op_e_mmu), // indicates write req pending
.fpu_mem_e (fpu_mem_e), //from iu,fp mem op in E-stage
.fp_trap_fix (fload_wait_w), //from fpu, fix for FP traps
.iu_iva_g (iu_iva_g), // instruction virtual address g stage
.iu_dva_e (iu_dva_e), // data virtual address e stage
.mc_mstb_l (mc_mstb_l), // from memif, input mdata strobe from mcb
.mc_mbsy (mc_mbsy), // from memif, input mcb busy indicator
.dp_perr (dp_perr), // from memif, indicates parity error
// .sb_ioa (sb_ioa), // from sbc, IO address input bus, used for virtual address
// error check
// .sb_cyc_pnd (sb_cyc_pnd), // input indicating an SB cycle pending
// .sb_sbslot (sb_sbslot), // Sbus slot ID for current SB cycle
// .sb_ioreq (sb_ioreq), // encoded IO request
// .sb_errsize (sb_errsize), // size of op in which error occrd
// .sb_err_type (sb_err_type), // SB error type (2-bit field)
// .sb_write_error (sb_write_error), // CPU write error to SBC
// .sb_va_val_l (sb_va_val_l), // Hold enable for io_addr reg.
.iu_in_trap (iu_in_trap), // iu trapped, abort any write op
.mc_caddr_hld(mc_caddr_hld), // hold low addr bit to MMU
.iu_sfs_sup (iu_sfs_sup),
.iu_sfs_perr (iu_sfs_perr),
.iu_sfs_xerr (iu_sfs_xerr),
.iu_sfs_mmiss (iu_sfs_mmiss),
.iu_sfs_iae (iu_sfs_iae),
.iu_sfs_sbe (iu_sfs_sbe),
.iu_sfs_sto (iu_sfs_sto),
.iu_sfs_prtct (iu_sfs_prtct),
.iu_sfs_priv (iu_sfs_priv),
.iu_sfs_lvl (iu_sfs_lvl),
.iu_mm_iacc_wp_exc_d (iu_mm_iacc_wp_exc_d),
.mm_tg_strobe (tg_strobe), // from jtag cntl
.mm_dabort (mm_dabort), // abort the d cache mem op
.mm_dcstben (mm_dcstben), // to dc, assert stb_en
.mm_icstben (mm_icstben), // to ic,iu.assert stb_en for ic to do non mem xaxtion
.mm_iabort (mm_iabort), // to ic, memory op abort
.icstben_asi (icstben_asi), // to ic, icstben is for asi operation
.mm_fs_lvl (mm_fs_lvl),
.mm_fs_perr (mm_fs_perr),
.mm_fs_iae (mm_fs_iae),
.mm_fs_xerr (mm_fs_xerr),
.mm_fs_mmiss (mm_fs_mmiss),
.mm_fs_sbe (mm_fs_sbe),
.mm_fs_sto (mm_fs_sto),
.mm_fs_sptct (mm_fs_sptct),
.ss_reset (reset),
.ss_reset_any (reset_iu),
.ss_scan_mode (ss_scan_mode),
.mc_tlb_scan_in (),
.m_mmu_cache_scan_out (),
.mm_icache_enbl (mm_icache_enbl),
.mm_dcache_enbl (mm_dcache_enbl),
.mm_cache_stat (mm_cache_stat),
.dcc_idle (dcc_idle), // from D$ -SM is idle
.ihold_d1 (ihold_d1), // for MMU perf counter trigger
.dhold_d1 (dhold_d1), // for MMU perf counter trigger
.dc_shold (dc_shold), // to iu, wrbuffer full
.did_fetch (did_fetch), // for MMU perf counter trigger
.fhold_d1(fhold_d1), // reg'd ext_fhold for perf cntr
.fhold_fqfull_d1(fhold_fqfull_d1), // reg'd fq_full for perf cntr
.iu_sup_mode (iu_sup_mode), // for MMU perf counter trigger
.standby_dsbl_tlb (standby_dsbl_tlb), // for tlb power down mode input
.mem_idle (standby_req), // mem idle sig just before standby mode
.hold_fetch_f_l (hold_fetch_f_l),
.p_reply_dec (p_reply_dec), // input from fb
.mc_afx_to (mc_afx_to), // AFX timeout signal
.ss_clock (ss_clock) // remove buffered ss_clock bus
);
/* ^L */
/***************** PROMIF model **************************************/
wire [1:0] prom_p_reply ;
wire [63:0] b_memdata_out, b_memdata_in ;
promif ssparc_promif(
.ss_scan_mode (ss_scan_mode),
.promif_scan_in (),
.promif_scan_out (),
.bm_sel (w_bm_sel), // Added for 8-bit prom
.gclk_1st_phase (gclk_1st_phase),
.ss_reset (reset),
//there is no ss_clock, so I hooked it up to memif's clk
.ss_clock (ss_clock),
.aen_in (w_aen),
// tie this to 1 for now
// .falcon_exists (1'b1),
.rom_speed (mm_rom_module_speed),
.mc_mwe_l (w_mc_mwe_l),
.s_reply (w_s_reply),
.ab ({memif_ab_out,memif_memaddr_out}),
.dbus_out (b_memdata_out),
.dbus_in (b_memdata_in),
.dbus_oe (memif_mem_oen),
.dbus_oe_standby(standby_dsbl_tlb),
.dbus2pad_eo (b_mem_oen),
.dbus2pad_out (w_b_memdata_out),
.dbus2pad_in (w_b_memdata_in),
.pcic_afxs_dbout(db_out1), // receive this
.pcic_afxm_dbout(db_out2), // drive this
.pcic_db_oen (pcic_db_oen), // select pcic
.pcic_afxm_db_oen(pcic_afxm_db_oen),
.memif_mempar (memif_mempar), // memif mpar drive
.mpar_out1 (mpar_out1), // pcic afxs (receive)
.mpar_out2 (mpar_out2), // pcic afxm drive
.w_b_mempar_out (w_b_mempar_out), // to pads
.pad_mempar_in (pad_mempar_in), // from pads (receive)
.w_b_mempar_in (w_b_mempar_in), // after mux (receive)
.memif_ab_out (memif_ab_out),
.memif_memaddr_out(memif_memaddr_out),
.pcic_ab_out (pcic_ab_out),
.pcic_ab_oen (pcic_ab_oen), // select pcic ab,
.w_ab_out (w_ab_out), // out ab to pads
.w_mc_memaddr (w_mc_memaddr), // out memaddr to pads
.prom_p_reply (prom_p_reply),
.rom_addr (w_rom_addr),
.rom_oe_l (w_rom_oe_l),
.rom_we_l (w_rom_we_l),
.rom_cs_l (w_rom_cs_l)
) ;
/***************** PCI CONTROLLER model **************************************/
pcic ssparc_pcic (
.pcic_scan_in (),
.pcic_scan_out (),
.little_endian (little_endian),
// Misc unidrectional
.ext_req_l (w_pci_req_l),
.ext_int_ (w_ext_int_),
.ext_int_oe (w_ext_int_oe),
.ext_gnt_l (w_pci_gnt_l),
.falcon_int (falcon_int),
// AFX Drive enables
.pcic_ab_oen (pcic_ab_oen),
.pcic_db_oen (pcic_db_oen),
.pcic_afxm_db_oen (pcic_afxm_db_oen),
// falcon drive to IAFX
.ab_out (pcic_ab_out),
.db_out1 (db_out1),
.db_out2 (db_out2),
.mpar_out1 (mpar_out1),
.mpar_out2 (mpar_out2),
// falcon unidirectional
.am_cstb_l (am_cstb_l),
.am_read (am_read),
.am_wm (am_wm),
.aen (w_aen),
.write_l (w_mc_mwe_l),
.lo_addr (w_s_reply),
.valid_l (w_valid_l),
.cas_cyc (w_cas_cyc),
.am_gnt_l (w_am_gnt_l),
.mm_oddpar (mm_oddpar),
.dp_perr (dp_perr),
.gclk (w_gclk),
.s_reply ({w_s_reply,w_mc_mwe_l}),
.p_reply (pcic_p_reply),
.db (w_b_memdata_in),
.ab ({w_ab_out,w_mc_memaddr}),
.mpar (w_b_mempar_in),
.reset (reset),
// pci Drive enables
.top_ADEnable (ADEnable),
.cbeEnable (cbeEnable),
.PAREnable (PAREnable),
.frameEn (frameEn),
.trdyEn (trdyEn),
.irdyEn (irdyEn),
.stopEn (stopEn),
.devselEn (devselEn),
.perrEn (perrEn),
.serrEnable (serrEnable),
// pci from the core to io pad
.AD_out (w_ad_out),
.CBEnnout (w_cbe_out),
.PAR_out (w_par_out),
.mas_framen_out (w_frame_l_out),
.tar_trdyout (w_trdy_l_out),
.mas_irdyn_out (w_irdy_l_out),
.tar_stopout (w_stop_l_out),
.tar_devselout (w_devsel_l_out),
.mas_req_out (mas_req_out),
.serro_ (w_serr_l_out),
.perro_ (w_perr_l_out),
// pci Drive from io_pad to core
.ad_bus_i (w_ad_in),
.cben_bus_i (w_cbe_in),
.par_i (w_par_in),
._frame_i (w_frame_l_in),
._frame_ia (w_frame_l_in),
._frame_ib (w_frame_l_in),
._irdy_i (w_irdy_l_in),
._irdy_ia (w_irdy_l_in),
._irdy_ib (w_irdy_l_in),
._irdy_ic (w_irdy_l_in),
._perr_i (w_perr_l_in),
._serr_i (w_serr_l_in),
._trdy_i (w_trdy_l_in),
._trdy_ia (w_trdy_l_in),
._trdy_ib (w_trdy_l_in),
._stop_i (w_stop_l_in),
._devsel_i (w_devsel_l_in),
.PCI_rstn_in (pci_rst_int_l),
.pci_clk (pci_clk),
// scan inputs / output
// worry about this later, tie off for now how to gate off
// async resets, sync cell scan
.csl_scan_mode (csl_scan_mode),
.pci_clk_sync (pci_clk_sync),
.pci_clk_sync_ (pci_clk_sync_),
.gclk_sync (gclk_sync),
.gclk_sync_ (gclk_sync_),
.tmr_clk (tmr_clk),
.pci_clk_ (pci_clk_),
.boot_mode (pcic_ifetch),
.mm_go_standby (mm_go_standby),
.turn_off_standby (turn_off_standby),
| This page: |
Created: | Thu Aug 19 12:03:40 1999 |
| From: |
../../../sparc_v8/ssparc/rtl/ssparc_core.v
|