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/*
	@(#)par_tree.v	1.1 11/2/92
	parity tree generated in gates 
 */

[Up: rl_dpc_logic par_lo_gen][Up: rl_dpc_logic par_hi_gen][Up: rl_dpc_logic par_lo_chk][Up: rl_dpc_logic par_hi_chk]
module parity_tree (
	parity_error,
	data,
	parity_bit,
	odd_parity,
	enable
	);

output parity_error;
input [31:0] data;
input parity_bit;
input odd_parity;
input enable;

wire	lev1_0, lev1_1, lev1_2, lev1_3, lev1_4;
wire	lev1_5, lev1_6, lev1_7, lev1_8, lev1_9;
wire	lev1_10;

JXOR3B LEVEL1_U0 ( .A1(data[0]), .A2(data[1]), .A3(data[2]), .O(lev1_0) );
JXOR3B LEVEL1_U1 ( .A1(data[3]), .A2(data[4]), .A3(data[5]), .O(lev1_1) );
JXOR3B LEVEL1_U2 ( .A1(data[6]), .A2(data[7]), .A3(data[8]), .O(lev1_2) );
JXOR3B LEVEL1_U3 ( .A1(data[9]), .A2(data[10]), .A3(data[11]), .O(lev1_3) );
JXOR3B LEVEL1_U4 ( .A1(data[12]), .A2(data[13]), .A3(data[14]), .O(lev1_4) );
JXOR3B LEVEL1_U5 ( .A1(data[15]), .A2(data[16]), .A3(data[17]), .O(lev1_5) );
JXOR3B LEVEL1_U6 ( .A1(data[18]), .A2(data[19]), .A3(data[20]), .O(lev1_6) );
JXOR3B LEVEL1_U7 ( .A1(data[21]), .A2(data[22]), .A3(data[23]), .O(lev1_7) );
JXOR3B LEVEL1_U8 ( .A1(data[24]), .A2(data[25]), .A3(data[26]), .O(lev1_8) );
JXOR3B LEVEL1_U9 ( .A1(data[27]), .A2(data[28]), .A3(data[29]), .O(lev1_9) );
JXOR3B LEVEL1_U10 ( .A1(data[30]), .A2(data[31]), .A3(parity_bit), .O(lev1_10) );

wire	lev2_0, lev2_1, lev2_2, lev2_3;

JXOR3B LEVEL2_U0 ( .A1(lev1_0), .A2(lev1_1), .A3(lev1_2), .O(lev2_0) );
JXOR3B LEVEL2_U1 ( .A1(lev1_3), .A2(lev1_4), .A3(lev1_5), .O(lev2_1) );
JXOR3B LEVEL2_U2 ( .A1(lev1_6), .A2(lev1_7), .A3(lev1_8), .O(lev2_2) );
JXOR3B LEVEL2_U3 ( .A1(lev1_9), .A2(lev1_10), .A3(odd_parity), .O(lev2_3) );

wire	lev3_0, lev3_1;

JXOR2B LEVEL3_U0 ( .A1(lev2_0), .A2(lev2_1), .O(lev3_0) );
JXOR2B LEVEL3_U2 ( .A1(lev2_2), .A2(lev2_3), .O(lev3_1) );

wire	lev4;

JXOR2B LEVEL4_U0 ( .A1(lev3_0), .A2(lev3_1), .O(lev4) );

wire	parity_error_l;

JNAND2B LEVEL5_U0 ( .A1(enable), .A2(lev4), .O(parity_error_l) );

wire	parity_error;

JINVD LEVEL6_U0 ( .A(parity_error_l), .O(parity_error) );

endmodule
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This page: Created:Thu Aug 19 11:59:18 1999
From: ../../../sparc_v8/ssparc/memif/rtl/par_tree.v

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