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/**************************************************************************
 * @(#)rl_dpc_logic.v	1.22 10/13/93
 * rl_dpc_logic.v
 *
 *  Description:
 *      The control and random logic section of the DPC block of memory
 *		subsystem in SingleSPARC.
 *      Refer to SingleSPARC Hardware Spec, section 2.7.4 for block diagram
 *      and more information.
 *
 *
 *  Dependencies:
 *      mem_cells.vpp defines.v dpc_cont.v dpc_par.v
 *
 *
 ***************************************************************************/

/**************************************************************************
 * This module contains all the control logic and the parity generation logic
 * for the DPC block. This should be synopsyzed as a "random logic block".
 */

module rl_dpc_logic (
			paro, dp_perr, 
			out_hld, in_hld, dp_buf0_en_dly, dp_ben, mux_sel,

            pod, rid, pari, mc_dpct, mc_curr_st, mc_odat_hld,
            mm_oddmpar, mm_parity_en, pcic_afxm_db_oen, 
	    ss_scan_mode, ss_clock,
			quad_sel, 
			mm_issue_req, mm_mreq, mm_2nd_wd, mc_mbsy,
			quad_sel_dwd, gr_hld, gr_out_sel, mm_fb_req,
			am_gnt_l, valid_l, am_read, sync_t0);

    output  [1:0]   paro;         // Parity out to the Parity pads.
    output  [1:0]   dp_perr;      // Parity-Error condition bits.
//    output  [1:0]   dp_perr_reg;      // Parity-Error condition bits, registered.
    output  [1:0]   in_hld ;
    output  [3:0]   out_hld ;
    output  [3:0]   mux_sel;
//	output			dp_buf0_en;
	output			dp_buf0_en_dly;
	output			dp_ben;			// External Tri-enable control to IO-pads.
	output	    quad_sel;
	output	    quad_sel_dwd;
    output  [1:0]   gr_hld ;
	output	    gr_out_sel;

    input   [63:0]  pod ;         // Data for the Parity generation logic.
    input   [63:0]  rid ;         // Data for the Parity  checking logic.
    input   [1:0]   pari;         // Parity in from to the Parity pads.
    input   [8:0]   mc_curr_st;  // MCB current state.
                                 // IIe change : Increased to 9 bits.
    input           mc_odat_hld; // MCB in Idle when 0.
    input   [5:0]   mc_dpct;     // DPC control bus from MCB. See table below:
//	input			mdata_en1 ;
    input           mm_oddmpar;   // Selects odd/even parity.
    input           mm_parity_en;   // Selects enable parity.
        input  pcic_afxm_db_oen;                //IIep 2.0: dma_rd par c
	input			ss_scan_mode;
    input           ss_clock;         // Free running system clock.
        input       mm_issue_req;        // 
        input  [3:0]   mm_mreq;        // 
	input	    mm_2nd_wd;
	input	    mc_mbsy;
	input	    mm_fb_req;
 
        input       am_gnt_l;   // IIe signal : DRAM bus granted to Falcon.
	//2.0:  add valid_l, am_read for dma read par chk 
        input       valid_l;    // IIe signal : DMA r/w data valid
        input       am_read;    // IIe signal : DMA r/~w direction
	input	    sync_t0;    //IIep 2.0: for dma read par chk

    wire	[1:0]	par_en;
//	wire	in_dly1;		// Use as "par_hld" in module "rl_par_genchk32".
//	wire	in_dly2;		// Use as "sel_src" in module "rl_par_genchk32".
//	wire	lw_perr	;		// LongWord Parity error detect.
//	wire	lw_perr_reg ;		// Registered version of above for 2nd word
    wire                        Gnd = 1'b0;
    wire                        Vdd = 1'b1;
	
//wire [1:0] dp_perr_old;
//    rl_par_genchk32    par_lo  (paro[0], dp_perr_old[0] ,
//                             mm_oddmpar, par_en[0], pari[0], pod[31:0] ,
//							 in_dly1, in_dly2, ss_clock );
//    rl_par_genchk32    par_hi  (paro[1], dp_perr_old[1] ,
//                             mm_oddmpar, par_en[1], pari[1], pod[63:32] ,
//							 in_dly1, in_dly2, ss_clock );

// remove hold
//        GReg1           ffh_mm_oddmpar(mm_oddmpar_reg, mm_oddmpar, ss_clock, Gnd);
        Mflipflop_noop_1           ffh_mm_oddmpar(mm_oddmpar_reg, mm_oddmpar, ss_clock);

    parity_tree    par_lo_gen  (paro[0] , pod[31:0], Gnd,
                             mm_oddmpar_reg, Vdd);
    parity_tree    par_hi_gen  (paro[1] , pod[63:32], Gnd, 
                             mm_oddmpar_reg, Vdd);

// new parity generation path.
 
    parity_tree    par_lo_chk  (dp_perr[0] , rid[31:0], pari[0], 
                             mm_oddmpar_reg, par_en[0]); 
    parity_tree    par_hi_chk  (dp_perr[1] , rid[63:32], pari[1],
                             mm_oddmpar_reg, par_en[1]);


    rl_dpc_cont        ctrl    (out_hld, in_hld, dp_buf0_en_dly, par_en, dp_ben,
						 mux_sel,  
                             mc_dpct, mc_curr_st, mc_odat_hld,
						 ss_scan_mode, ss_clock,
					quad_sel, 
					mm_issue_req, mm_mreq, mm_2nd_wd, mc_mbsy,
					quad_sel_dwd, gr_hld, gr_out_sel, mm_fb_req,
					mm_parity_en, pcic_afxm_db_oen, am_gnt_l,
					valid_l, am_read, sync_t0);

/* Generate registered version of parity error bits to mmu.
Pre-registered version go to IU only. Cache do not need it at all. */
//	GReg1		ffh_dp_perr_reg_0(dp_perr_reg[0], dp_perr[0], ss_clock, Gnd);
//	GReg1		ffh_dp_perr_reg_1(dp_perr_reg[1], dp_perr[1], ss_clock, Gnd);



	/* Generate a 3rd parity error bit. This is the longword parity-error
	   bit and if one of the two words read from memory, contains a parity
	   error, this bit will be set for both of the cycles that data is valid
	   on internal mc_mdata bus.
	 ---------------------------------------------------------------------*/
/* not needed anymore 
	GReg1		ffh_lw_perr_reg(lw_perr_reg, lw_perr, ss_clock, in_dly1);
	Mux2_1		mux_par(dp_perr[2], lw_perr_reg, lw_perr, in_dly2);

	assign lw_perr =( (paro[1]^pari[1])|(paro[0]^pari[0]) ) &
					( par_en[0]|par_en[1] );
*/

endmodule