endmodule
// Double Power 8-Input NAND Gate
![[Up: ME_NAND8_B i]](v2html-up.gif)
module JNAND8C
(A1, A2, A3, A4, A5, A6, A7, A8, O);
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
input A8;
output O;
nand g0(O, A1, A2, A3, A4, A5, A6, A7, A8);
endmodule
// 2-Input NAND Gate with 1-inverting input
module ANANDI2C(A1, A2, O);
input A1;
input A2;
output O;
not g0(w1, A2);
nand g1(O, A1, w1);
endmodule
// 2-Input NAND Gate with 1-inverting input
module ANANDI2D(A1, A2, O);
input A1;
input A2;
output O;
not g0(w1, A2);
nand g1(O, A1, w1);
endmodule
// 2-Input NAND Gate
module ANAND2D(A1, A2, O);
input A1;
input A2;
output O;
nand g0(O, A1, A2);
endmodule
// Power 2-Input OR Gate
module JOR2B(A1, A2, O);
input A1;
input A2;
output O;
or g0(O, A1, A2);
endmodule
// Power 3-Input OR Gate
module JOR3B(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
or g0(O, A1, A2, A3);
endmodule
// Power 4-Input OR Gate
module JOR4B(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
or g0(O, A1, A2, A3, A4);
endmodule
// Double Power 6-Input OR Gate
module JOR6B(A1, A2, A3, A4, A5, A6, O);
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
output O;
or g0(O, A1, A2, A3, A4, A5, A6);
endmodule
// Double Power 8-Input OR Gate
module JOR8B(A1, A2, A3, A4, A5, A6, A7, A8, O);
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
input A8;
output O;
or g0(O, A1, A2, A3, A4, A5, A6, A7, A8);
endmodule
// 2-Input NOR Gate
module JNOR2A(A1, A2, O);
input A1;
input A2;
output O;
nor g0(O, A1, A2);
endmodule
// Power 2-Input NOR Gate
module JNOR2B(A1, A2, O);
input A1;
input A2;
output O;
nor g0(O, A1, A2);
endmodule
// 3-Input NOR Gate
module JNOR3A(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
nor g0(O, A1, A2, A3);
endmodule
// Power 3-Input NOR Gate
module JNOR3B(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
nor g0(O, A1, A2, A3);
endmodule
// 4-Input NOR Gate
module JNOR4A(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
nor g0(O, A1, A2, A3, A4);
endmodule
// Power 4-Input NOR Gate
module JNOR4B(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
nor g0(O, A1, A2, A3, A4);
endmodule
// Double Power 2-Input NOR Gate
module JNOR2C(A1, A2, O);
input A1;
input A2;
output O;
nor g0(O, A1, A2);
endmodule
// Tripple Power 2-Input NOR Gate
module JNOR2D(A1, A2, O);
input A1;
input A2;
output O;
nor g0(O, A1, A2);
endmodule
// Double Power 3-Input NOR Gate
module JNOR3C(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
nor g0(O, A1, A2, A3);
endmodule
// Tripple Power 3-Input NOR Gate
module JNOR3D(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
nor g0(O, A1, A2, A3);
endmodule
// Double Power 4-Input NOR Gate
module JNOR4C(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
nor g0(O, A1, A2, A3, A4);
endmodule
// Tripple Power 4-Input NOR Gate
module JNOR4D(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
nor g0(O, A1, A2, A3, A4);
endmodule
// Quadruple Power 4-Input NOR Gate
module JNOR4E(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
nor g0(O, A1, A2, A3, A4);
endmodule
// Double Power 6-Input NOR Gate
module JNOR6C(A1, A2, A3, A4, A5, A6, O);
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
output O;
nor g0(O, A1, A2, A3, A4, A5, A6);
endmodule
// Double Power 8-Input NOR Gate
module JNOR8C(A1, A2, A3, A4, A5, A6, A7, A8, O);
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
input A8;
output O;
nor g0(O, A1, A2, A3, A4, A5, A6, A7, A8);
endmodule
// 2-Input NOR Gate with 1 inverting-input
module ANORI2C(A1, A2, O);
input A1;
input A2;
output O;
not g0(w1, A2);
nor g1(O, A1, w1);
endmodule
// 2-Input NOR Gate with 1 inverting-input
module ANORI2D(A1, A2, O);
input A1;
input A2;
output O;
not g0(w1, A2);
nor g1(O, A1, w1);
endmodule
// Double Power 6-Input NOR Gate
module ANOR6D(A1, A2, A3, A4, A5, A6, O);
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
output O;
nor g0(O, A1, A2, A3, A4, A5, A6);
endmodule
// 2:1 Selector
module JMUX2A(A, B, S, O);
input A;
input B;
input S;
output O;
UDP_MUX21 udp_mux(O, A,B, S);
endmodule
// 4:1 Selector
module AMUX4A(I1, I2, I3, I4, S0, S1, O);
input I1;
input I2;
input I3;
input I4;
input S0;
input S1;
output O;
not g0(w2, S0);
not g1(w3, S1);
and g2(w0, I1, w2, w3);
not g3(w7, S1);
and g4(w4, I2, S0, w7);
not g5(w10, S0);
and g6(w8, I3, w10, S1);
and g7(w12, I4, S0, S1);
or g8(O, w0, w4, w8, w12);
endmodule
// 3:1 Selector
module AMUX3A(I0, I1, I2, S0, S1, O);
input I0;
input I1;
input I2;
input S0;
input S1;
output O;
not g0(w2, S0);
not g1(w3, S1);
and g2(w0, I0, w2, w3);
not g3(w7, S1);
and g4(w4, I1, S0, w7);
and g5(w8, I2, S1);
or g6(O, w0, w4, w8);
endmodule
// Non-inverting 2:1 Mux
module AMUX2A(A, B, S, O);
input A;
input B;
input S;
output O;
wire w1_;
UDP_MUX21 udp_mux(w1_, A,B, S);
not g1(O, w1_);
endmodule
// 2-input Exclusive OR
module JXOR2A(A1, A2, O);
input A1;
input A2;
output O;
xor g0(O, A1, A2);
endmodule
// Power 2-input Exclusive OR
module JXOR2B(A1, A2, O);
input A1;
input A2;
output O;
xor g0(O, A1, A2);
endmodule
// 3-input Exclusive OR
module JXOR3A(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
xor g0(O, A1, A2, A3);
endmodule
// Power 3-input Exclusive OR
module JXOR3B(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
xor g0(O, A1, A2, A3);
endmodule
// 2-input Exclusive NOR
module JXNOR2A(A1, A2, O);
input A1;
input A2;
output O;
xnor g0(O, A1, A2);
endmodule
// Power 2-input Exclusive NOR
module JXNOR2B(A1, A2, O);
input A1;
input A2;
output O;
xnor g0(O, A1, A2);
endmodule
// 3-input Exclusive NOR
module JXNOR3A(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
xnor g0(O, A1, A2, A3);
endmodule
// Power 3-input Exclusive NOR
module JXNOR3B(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
xnor g0(O, A1, A2, A3);
endmodule
// 1-bit D Flip-Flop with reset and hold
module ADFFRHA(D, CK, R, H, Q, XQ);
input D;
input CK;
input R; // active low
input H;
output Q;
output XQ;
not g0(w3, H);
and g1(w1, R, w3, D);
and g2(w5, R, H, IQ);
or g3(w0, w1, w5);
fj_dff_e g4(IQ, w0, CK);
buf g5(Q, IQ);
not g6(XQ, IQ);
endmodule
// 1-bit D Flip-Flop with reset
module ADFFRA(D, CK, R, Q, XQ);
input D;
input CK;
input R; // active low
output Q;
output XQ;
and g0(w0, R, D);
fj_dff_e g1(IQ, w0, CK);
buf g2(Q, IQ);
not g3(XQ, IQ);
endmodule
// 1-bit D Flip-Flop with scan
module ASFFA(D, CK, SM, SI, Q, XQ, SO);
input D;
input CK;
input SM;
input SI;
output Q;
output XQ;
output SO;
fj_dff_e_muxscan g0(IQ, D, SI, SM, CK);
buf g1(Q, IQ);
not g2(XQ, IQ);
buf g3(SO, IQ);
endmodule
// 1-bit D Flip-Flop with scan and hold
module ASFFHA(D, CK, H, SM, SI, Q, XQ, SO);
input D;
input CK;
input H;
input SM;
input SI;
output Q;
output XQ;
output SO;
and g0(w1, H, IQ);
not g1(w5, H);
and g2(w4, w5, D);
or g3(w0, w1, w4);
fj_dff_e_muxscan g4(IQ, w0, SI, SM, CK);
buf g5(Q, IQ);
not g6(XQ, IQ);
buf g7(SO, IQ);
endmodule
// 1-bit D Flip-Flop with scan and reset and hold
module ASFFRHA(D, CK, R, H, SM, SI, Q, XQ, SO);
input D;
input CK;
input R; // active low
input H;
input SM;
input SI;
output Q;
output XQ;
output SO;
not g0(w4, H);
and g1(w3, w4, D);
and g2(w6, H, IQ);
or g3(w2, w3, w6);
and g4(w0, R, w2);
fj_dff_e_muxscan g5(IQ, w0, SI, SM, CK);
buf g6(Q, IQ);
not g7(XQ, IQ);
buf g8(SO, IQ);
endmodule
// 1-bit D Flip-Flop with scan and reset
module ASFFRA(D, CK, R, SM, SI, Q, XQ, SO);
input D;
input CK;
input R; // active low
input SM;
input SI;
output Q;
output XQ;
output SO;
and g0(w0, R, D);
fj_dff_e_muxscan g1(IQ, w0, SI, SM, CK);
buf g2(Q, IQ);
not g3(XQ, IQ);
buf g4(SO, IQ);
endmodule
// 4-bit 2-input mux Flip-Flop with scan and hold
module AMUXFFA(DA0, DA1, DA2, DA3, DB0, DB1, DB2, DB3, CK,
HLD, SM, SI, S, DO0, DO1, DO2, DO3, SO);
input DA0;
input DA1;
input DA2;
input DA3;
input DB0;
input DB1;
input DB2;
input DB3;
input CK;
input HLD; // hold data, active high
input SM; // scan mode, active high
input SI; // scan data in
input S; // select, 0-DAx, 1-DBx
output DO0;
output DO1;
output DO2;
output DO3;
output SO;
and g0(w1, HLD, IQ3);
not g1(w5, HLD);
and g2(w7, S, DB3);
not g3(w11, S);
and g4(w10, w11, DA3);
or g5(w6, w7, w10);
and g6(w4, w5, w6);
or g7(w0, w1, w4);
fj_dff_e_muxscan g8(IQ3, w0, IQ2, SM, CK);
and g9(w17, HLD, IQ2);
not g10(w21, HLD);
and g11(w23, S, DB2);
not g12(w27, S);
and g13(w26, w27, DA2);
or g14(w22, w23, w26);
and g15(w20, w21, w22);
or g16(w16, w17, w20);
fj_dff_e_muxscan g17(IQ2, w16, IQ1, SM, CK);
and g18(w33, HLD, IQ1);
not g19(w37, HLD);
and g20(w39, S, DB1);
not g21(w43, S);
and g22(w42, w43, DA1);
or g23(w38, w39, w42);
and g24(w36, w37, w38);
or g25(w32, w33, w36);
fj_dff_e_muxscan g26(IQ1, w32, IQ0, SM, CK);
and g27(w49, HLD, IQ0);
not g28(w53, HLD);
and g29(w55, S, DB0);
not g30(w59, S);
and g31(w58, w59, DA0);
or g32(w54, w55, w58);
and g33(w52, w53, w54);
or g34(w48, w49, w52);
fj_dff_e_muxscan g35(IQ0, w48, SI, SM, CK);
buf g36(DO0, IQ0);
buf g37(DO1, IQ1);
buf g38(DO2, IQ2);
buf g39(DO3, IQ3);
buf g40(SO, IQ3);
endmodule
// 8-input Comparator
module ACOMP8A(A0, A1, A2, A3, A4, A5, A6, A7, B0, B1, B2,
B3, B4, B5, B6, B7, O);
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
input B0;
input B1;
input B2;
input B3;
input B4;
input B5;
input B6;
input B7;
output O;
xor g0(w0, A0, B0);
xor g1(w3, A1, B1);
xor g2(w6, A2, B2);
xor g3(w9, A3, B3);
xor g4(w12, A4, B4);
xor g5(w15, A5, B5);
xor g6(w18, A6, B6);
xor g7(w21, A7, B7);
nor g8(O, w0, w3, w6, w9, w12, w15, w18, w21);
endmodule
// 3-input Comparator
module ACOMP3A(A0, A1, A2, B0, B1, B2, O);
input A0;
input A1;
input A2;
input B0;
input B1;
input B2;
output O;
xor g0(w0, A0, B0);
xor g1(w3, A1, B1);
xor g2(w6, A2, B2);
nor g3(O, w0, w3, w6);
endmodule
// 4-input Comparator
module ACOMP4A(A0, A1, A2, A3, B0, B1, B2, B3, O);
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
input B3;
output O;
xor g0(w0, A0, B0);
xor g1(w3, A1, B1);
xor g2(w6, A2, B2);
xor g3(w9, A3, B3);
nor g4(O, w0, w3, w6, w9);
endmodule
// 5-input Comparator
module ACOMP5A(A0, A1, A2, A3, A4, B0, B1, B2, B3, B4, O);
input A0;
input A1;
input A2;
input A3;
input A4;
input B0;
input B1;
input B2;
input B3;
input B4;
output O;
xor g0(w0, A0, B0);
xor g1(w3, A1, B1);
xor g2(w6, A2, B2);
xor g3(w9, A3, B3);
xor g4(w12, A4, B4);
nor g5(O, w0, w3, w6, w9, w12);
endmodule
// Tri-state buffer
module ATSBUFD(I1, I2, I3, I4, I5, I6, I7, I8, CK, SI, SM,
OE_, RESET, O1, O2, O3, O4, O5, O6, O7, O8,
SO);
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
input CK;
input SI;
input SM;
input OE_;
input RESET;
output O1;
output O2;
output O3;
output O4;
output O5;
output O6;
output O7;
output O8;
output SO;
not g0(w5, SM);
not g1(w6, RESET);
and g2(w4, w5, w6);
fj_dff_es_muxscan g3(IQ, OE_, SI, SM, CK, w4);
or g4(w8, IQ, SM);
bufif0 g5(O1, I1, w8);
or g6(w12, IQ, SM);
bufif0 g7(O2, I2, w12);
or g8(w16, IQ, SM);
bufif0 g9(O3, I3, w16);
or g10(w20, IQ, SM);
bufif0 g11(O4, I4, w20);
or g12(w24, IQ, SM);
bufif0 g13(O5, I5, w24);
or g14(w28, IQ, SM);
bufif0 g15(O6, I6, w28);
or g16(w32, IQ, SM);
bufif0 g17(O7, I7, w32);
or g18(w36, IQ, SM);
bufif0 g19(O8, I8, w36);
buf g20(SO, IQ);
endmodule
// Power Clock Buffer
module JCBUFB1(A, O);
input A;
output O;
buf g0(O, A);
endmodule
// Power Clock Buffer
module JCBUFC1(A, O);
input A;
output O;
buf g0(O, A);
endmodule
// Power Clock Multiplexer
module JCMUX2B1(A1, A2, B1, B2, O);
input A1;
input A2;
input B1;
input B2;
output O;
and g0(w0, A1, A2);
and g1(w3, B1, B2);
nor g2(O, w0, w3);
endmodule
// Power Clock Inverter
module JCINVA1(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Double Power Clock Inverter
module JCINVB1(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Quadruple Power Clock Inverter
module JCINVC1(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Tripple Power Clock Inverter
module JCINVD1(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Quadruple Power Clock Inverter
module JCINVE1(A, O);
input A;
output O;
not g0(O, A);
endmodule
// Double Power Gated Clock NAND Buffer
module JCNAN2B1(A1, A2, O);
input A1;
input A2;
output O;
nand g0(O, A1, A2);
endmodule
// Double Power Gated Clock NAND Buffer
module JCNAN2C1(A1, A2, O);
input A1;
input A2;
output O;
nand g0(O, A1, A2);
endmodule
// Power Gated Clock OR Buffer
module JCOR2B1(A1, A2, O);
input A1;
input A2;
output O;
or g0(O, A1, A2);
endmodule
// 2-Input NOR Gate
module JNOR2A1(A1, A2, O);
input A1;
input A2;
output O;
nor g0(O, A1, A2);
endmodule
// Power 2-Input NOR Gate
module JNOR2B1(A1, A2, O);
input A1;
input A2;
output O;
nor g0(O, A1, A2);
endmodule
// 3-Input NOR Gate
module JNOR3A1(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
nor g0(O, A1, A2, A3);
endmodule
// Power 3-Input NOR Gate
module JNOR3B1(A1, A2, A3, O);
input A1;
input A2;
input A3;
output O;
nor g0(O, A1, A2, A3);
endmodule
// 4-Input NOR Gate
module JNOR4A1(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
nor g0(O, A1, A2, A3, A4);
endmodule
// Power 4-Input NOR Gate
module JNOR4B1(A1, A2, A3, A4, O);
input A1;
input A2;
input A3;
input A4;
output O;
nor g0(O, A1, A2, A3, A4);
endmodule
// JTAG Output Enable Control Cell
module JJOED(XSM_, EN, SI, CK, UP, ACK, XBCK, MD1, ENC_,
ENO, SO);
input XSM_; // scan-mode
input EN; // bidir i/o jtag_ff: 1-sel_OT_data, 0-sel_PAD_data
input SI; // scan-data in
input CK; // clk for normal operation, hold high
input UP; // xfer reg. data to latch
input ACK; // scan data-in strobe, active high
input XBCK; // enb. slave latch
input MD1; // 0-normal operation, 1-use scanned state
output ENC_; // tri-state enable, 1-tristate, 0-bistate
output ENO; // bidir i/o jtag_ff: 1-sel_OT_data, 0-sel_PAD_data
output SO; // scan-data out
// Verilog body for JJOED
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire si_ ;
wire en_ ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire x ;
wire y ;
not g1(bck, XBCK) ;
not g2(xack, ACK) ;
not g3(xclk, CK) ;
not g4(clk, xclk) ;
not g5(xupd, UP) ;
not g6(upd, xupd) ;
not g7(si_, SI) ;
not g8(en_, EN) ;
UDP_LATCH1 g9(jtag_latch1_out, xclk, ACK, en_, si_) ;
UDP_LATCH2 g10(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
not g11(SO, jtag_latch2_out) ;
UDP_LATCH g12(jtag_latch3_out, xupd, jtag_latch2_out) ;
UDP_MUX21 g13(x, en_, jtag_latch3_out, MD1) ;
buf g14(ENO, x) ;
nand g15(y, XSM_, x) ;
buf g16(ENC_, y) ;
endmodule
// AB Clock Generator
module ACABGEN(CLK, ENB, CLK_A, CLK_B);
input CLK;
input ENB; // typically SM, assert while CLK=1!
output CLK_A; // A strobe
output CLK_B; // B strobe
wire pulse, dly_pulse;
not g1(enb_, ENB);
nor g2(pulse, enb_,CLK);
buf #5 g3(dly_pulse, pulse);
nand g5(clka_, pulse,dly_pulse);
not g6(CLK_A, clka_);
nor g8(clkb_, pulse,dly_pulse);
not g9(CLK_B, clkb_);
endmodule
// JTAG Bidirectional Cell
module JBS11SN(ENC_, OT, ENO, SI, CK, UP, ACK, XBCK, MD1,
MD2, SO, IT, X);
input ENC_; // tri-state enable, 0-tristate, 1-bistate
input OT; // outgoing data from core
input ENO; // jtag_ff: 1-sel_OT_data, 0-sel_PAD_data
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD1; // 0-sel_pad_data, 1-sel_jtag_ff
input MD2; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
output IT; // incomming data to core
inout X;
// Verilog body for JBS11SN
wire MD1_ ;
wire MD2_ ;
wire OT_ ;
wire ENO_ ;
wire tmg1m1_out ;
wire jtag_q ;
wire tmg2m1_b ;
wire ENC ;
wire tmg1m1_out_ ;
wire bscn_xd0 ;
wire bscn_d0 ;
wire bscn_xd1 ;
wire bscn_d1 ;
wire bck ;
wire xack ;
wire clk ;
wire xclk ;
wire upd ;
wire xupd ;
wire jtag_x1 ;
wire jtag_x2 ;
wire jtag_x ;
wire jtag_latch1_out ;
wire jtag_latch2_out ;
wire jtag_latch3_out ;
wire out_buf_a ;
wire out_buf_b ;
wire out_buf_en ;
not g1(MD1_, MD1) ;
not g2(MD2_, MD2) ;
not g3(OT_, OT) ;
not g4(ENO_, ENO) ;
UDP_MUX21 g5(tmg1m1_out, jtag_q, OT_, MD1_) ;
not g6(ENC, ENC_) ;
not g7(tmg1m1_out_, tmg1m1_out) ;
and g8(bscn_xd0, ENC, tmg1m1_out) ;
or g9(bscn_d0, ENC_, tmg1m1_out_) ;
or g10(bscn_xd1, ENC_, tmg1m1_out) ;
and g11(bscn_d1, ENC, tmg1m1_out_) ;
not g12(tmg2m1_b, X) ;
UDP_MUX21 g13(IT, jtag_q, tmg2m1_b, MD2_) ;
not g14(bck, XBCK) ;
not g15(xack, ACK) ;
not g16(xclk, CK) ;
not g17(clk, xclk) ;
not g18(xupd, UP) ;
not g19(upd, xupd) ;
and g20(jtag_x1, OT_, ENO) ;
and g21(jtag_x2, ENO_, tmg2m1_b) ;
nor g22(jtag_x, jtag_x1, jtag_x2) ;
UDP_LATCH1 g23(jtag_latch1_out, xclk, ACK, jtag_x, SI) ;
UDP_LATCH2 g24(jtag_latch2_out, bck, clk, jtag_latch1_out) ;
buf g25(SO, jtag_latch2_out) ;
UDP_LATCH g26(jtag_latch3_out, xupd, jtag_latch2_out) ;
not g27(jtag_q, jtag_latch3_out) ;
not g28(out_buf_a, bscn_xd0) ;
not g29(out_buf_b, bscn_xd1) ;
xor g30(out_buf_en, out_buf_a, out_buf_b) ;
notif0 g31(X, out_buf_a, out_buf_en) ;
endmodule
// JTAG Bidirectional Cell
module JBS13SN(ENC_, OT, ENO, SI, CK, UP, ACK, XBCK, MD1,
MD2, SO, IT, X);
input ENC_; // tri-state enable, 0-tristate, 1-bistate
input OT; // outgoing data from core
input ENO; // jtag_ff: 1-sel_OT_data, 0-sel_PAD_data
input SI; // scan-in data
input CK; // register pad-data on rising edge
input UP; // latch data from jtag ff
input ACK; // enb. master latch for scan-in data
input XBCK; // enb. slave latch
input MD1; // 0-sel_pad_data, 1-sel_jtag_ff
input MD2; // 0-sel_pad_data, 1-sel_jtag_ff
output SO; // scan-out data
| This page: |
Created: | Thu Aug 19 12:01:14 1999 |
| From: |
../../../sparc_v8/lib/rtl/sc.v
|