//
// Copyright Notice and Proprietary Information
//
// Copyright (C) 1992 - 1995 Synopsys, Inc. All rights reserved. This Software
// and manual are owned by Synopsys, Inc., and may be used only as authorized
// in the license agreement controlling such use. No part of this publication
// may be reproduced, transmitted, or translated, in any form or by any means,
// electronic, mechanical, manual, optical, or otherwise, without prior written
// permission of Synopsys, Inc., or as expressly provided by the license agreement.
//
// Destination Control Statement
//
// All technical data contained in this publication is subject to the export
// control laws of the United States of America. Disclosure to nationals of other
// countries contrary to United States law is prohibited. It is the reader's
// responsibility to determine the applicable regulations and to comply with them.
//
// Disclaimer
//
// Synopsys, Inc., makes no warranty of any kind, express or implied, with regard
// to this material, including, but not limited to, the implied warranties of
// merchantability and fitness for a particular purpose.
//
// Synopsys, Inc., reserves the right to make changes without further notice to
// the products described herein. Synopsys, Inc. does not assume any liability
// arising out of the application or use of any product or circuit described
// herein. The Synopsys products described herein are not authorized for use as
// components in life-support devices.
//
`lmv_timescale
![[Up: Msystem lmc_master1]](v2html-up.gif)
module pcimaster
(pad,pcxbenn,ppar,pframenn,ptrdynn,pirdynn,pstopnn,pdevselnn,pidsel,preqnn
,pgntnn,pclk,pclkrunnn,prstnn,pd,pbenn,ppar64,preq64nn,pack64nn,plocknn
,pperrnn,pserrnn,psbonn,psdone,syncin,syncout);
inout [31:0] pad;
inout [3:0] pcxbenn;
inout ppar;
inout pframenn;
inout ptrdynn;
inout pirdynn;
input pstopnn;
inout pdevselnn;
input pidsel;
inout preqnn;
input pgntnn;
input pclk;
inout pclkrunnn;
input prstnn;
inout [63:32] pd;
inout [7:4] pbenn;
inout ppar64;
inout preq64nn;
input pack64nn;
inout plocknn;
inout pperrnn;
input pserrnn;
input psbonn;
input psdone;
input [7:0] syncin;
output [7:0] syncout;
parameter gen_debug_level = 0; // debug level: 0 = no debugging
pcimaster_fm fm
(pad,pcxbenn,ppar,pframenn,ptrdynn,pirdynn,pstopnn,pdevselnn,pidsel,preqnn
,pgntnn,pclk,pclkrunnn,prstnn,pd,pbenn,ppar64,preq64nn,pack64nn,plocknn
,pperrnn,pserrnn,psbonn,psdone,syncin,syncout);
//---------------------------------
//---------------------------------
//-- User variable declarations --
//-- are to be entered here --
//---------------------------------
//---------------------------------
//--**--**--**--**--**--**--**--**-- USER DECLARATION BEGIN
//type object_name_types is :
parameter pad_bus = 0;
parameter pad_0 = 1;
parameter pad_1 = 2;
parameter pad_2 = 3;
parameter pad_3 = 4;
parameter pad_4 = 5;
parameter pad_5 = 6;
parameter pad_6 = 7;
parameter pad_7 = 8;
parameter pad_8 = 9;
parameter pad_9 = 10;
parameter pad_10 = 11;
parameter pad_11 = 12;
parameter pad_12 = 13;
parameter pad_13 = 14;
parameter pad_14 = 15;
parameter pad_15 = 16;
parameter pad_16 = 17;
parameter pad_17 = 18;
parameter pad_18 = 19;
parameter pad_19 = 20;
parameter pad_20 = 21;
parameter pad_21 = 22;
parameter pad_22 = 23;
parameter pad_23 = 24;
parameter pad_24 = 25;
parameter pad_25 = 26;
parameter pad_26 = 27;
parameter pad_27 = 28;
parameter pad_28 = 29;
parameter pad_29 = 30;
parameter pad_30 = 31;
parameter pad_31 = 32;
parameter pcxbenn_bus = 33;
parameter pcxbenn_0 = 34;
parameter pcxbenn_1 = 35;
parameter pcxbenn_2 = 36;
parameter pcxbenn_3 = 37;
parameter ppar_pin = 38;
parameter pframenn_pin = 39;
parameter ptrdynn_pin = 40;
parameter pirdynn_pin = 41;
parameter pstopnn_pin = 42;
parameter pdevselnn_pin = 43;
parameter pidsel_pin = 44;
parameter preqnn_pin = 45;
parameter pgntnn_pin = 46;
parameter pclk_pin = 47;
parameter pclkrunnn_pin = 48;
parameter prstnn_pin = 49;
parameter pd_bus = 50;
parameter pd_32 = 51;
parameter pd_33 = 52;
parameter pd_34 = 53;
parameter pd_35 = 54;
parameter pd_36 = 55;
parameter pd_37 = 56;
parameter pd_38 = 57;
parameter pd_39 = 58;
parameter pd_40 = 59;
parameter pd_41 = 60;
parameter pd_42 = 61;
parameter pd_43 = 62;
parameter pd_44 = 63;
parameter pd_45 = 64;
parameter pd_46 = 65;
parameter pd_47 = 66;
parameter pd_48 = 67;
parameter pd_49 = 68;
parameter pd_50 = 69;
parameter pd_51 = 70;
parameter pd_52 = 71;
parameter pd_53 = 72;
parameter pd_54 = 73;
parameter pd_55 = 74;
parameter pd_56 = 75;
parameter pd_57 = 76;
parameter pd_58 = 77;
parameter pd_59 = 78;
parameter pd_60 = 79;
parameter pd_61 = 80;
parameter pd_62 = 81;
parameter pd_63 = 82;
parameter pbenn_bus = 83;
parameter pbenn_4 = 84;
parameter pbenn_5 = 85;
parameter pbenn_6 = 86;
parameter pbenn_7 = 87;
parameter ppar64_pin = 88;
parameter preq64nn_pin = 89;
parameter pack64nn_pin = 90;
parameter plocknn_pin = 91;
parameter pperrnn_pin = 92;
parameter pserrnn_pin = 93;
parameter psbonn_pin = 94;
parameter psdone_pin = 95;
//type set_types is :
parameter mpin = 96;
parameter mbus = 97;
parameter mregister = 98;
//type address_mode is :
parameter linear = 99;
parameter wrap = 101;
parameter reserved = 102;
//type read_types is :
parameter intr_ack = 103;
parameter io_read = 104;
parameter rsvd4 = 105;
parameter mem_read = 106;
parameter rsvd8 = 107;
parameter config_read = 108;
parameter mem_read_mul = 109;
parameter mem_read_line = 110;
parameter mem_read64 = 136;
parameter mem_read_mul64 = 137;
parameter mem_read_line64 = 138;
//type write_types is :
parameter special_cyc = 111;
parameter io_write = 112;
parameter rsvd5 = 113;
parameter mem_write = 114;
parameter rsvd9 = 115;
parameter config_write = 116;
parameter mem_write_inv = 117;
parameter mem_write64 = 139;
parameter mem_write_inv64 = 140;
//type config_types is :
parameter dual_ad = 118;
parameter pci_error = 119;
parameter cdelay = 120;
parameter step = 121;
parameter same = 122;
parameter back = 123;
parameter mode = 124;
parameter dummy_cfg = 125;
parameter x_trans = 126;
parameter dev_id = 127;
parameter ven_id = 128;
parameter rev_id = 129;
parameter cls_code = 130;
parameter c_line_size = 131;
parameter max_clk_p = 132;
parameter rl = 133;
parameter tl = 134;
parameter cl = 135;
parameter z_adbus = (32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz);
parameter x_adbus = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
parameter l_ddbus = (32'b00000000000000000000000000000000);
reg strobe ; initial strobe = 1'b0;
reg [31 : 0] rdata ;
reg [63 : 0] rdata64 ;
// responses/status
reg dual_addr;
integer i, src, endfile;
integer endfile_int; initial endfile_int = 1;
integer cmmd, cmmd_code, tc, tc_count, delay;
reg [31:0] addr;
reg [7:0] byten;
reg [63:0] data;
reg [63:0] cdata;
integer number;
//--**--**--**--**--**--**--**--**-- USER DECLARATION END
reg init ; initial init = `true;
integer msg_level ; initial msg_level = 0;
reg valid_f ; initial valid_f = `false;
task vfy_rdy;
begin
if (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe);
while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe);
end
end // if
end
endtask // vfy_rdy
task read_intr_ack;
input [`slv_size-1 : 0] byten;
input [`slv_size-1 : 0] expected_data;
input [31 : 0] delay;
begin
if (!((msg_level < `debug_3))) begin
$display("NOTE at %0t from %m", $time);
$write(" \"pcimaster.v read_intr_ack");
$display("\"");
end // if
vfy_rdy;
fm.timing.read_intr_ack(intr_ack, byten, expected_data, delay);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin @(fm.fm_rsp.strobe); end
check_int;
end
endtask // read_intr_ack
task read_cycle;
input [31 : 0] rtype; // enum type read_types
input [31 : 0] addr;
input [31 : 0] tc;
input [`slv_size-1 : 0] byten;
input [`slv_size-1 : 0] expected_data;
input [31 : 0] delay;
input lock;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v read_cycle");
end // if
vfy_rdy;
fm.timing.read_cycle(rtype, addr, tc, byten, expected_data, delay, lock);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // read_cycle
task read_continue;
input [`slv_size-1 : 0] byten;
input [`slv_size-1 : 0] expected_data;
input [31 : 0] delay;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v read_continue");
end // if
vfy_rdy;
fm.timing.read_continue(byten, expected_data, delay);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // read_continue
task write_cycle;
input [31 : 0] wtype; // enum type write_types
input [31 : 0] addr;
input [31 : 0] tc;
input [`slv_size-1 : 0] byten;
input [`slv_size-1 : 0] data;
input [31 : 0] delay;
input lock;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v write_cycle");
end // if
vfy_rdy;
fm.timing.write_cycle(wtype, addr, tc, byten, data, delay, lock);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // write_cycle
task write_special_cyc;
input [`slv_size-1 : 0] byten;
input [`slv_size-1 : 0] data;
input [31 : 0] delay;
input lock;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v write_special_cyc");
end // if
vfy_rdy;
fm.timing.write_special_cyc(special_cyc, byten, data, delay, lock);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // write_special_cyc
task write_continue;
input [`slv_size-1 : 0] byten;
input [`slv_size-1 : 0] data;
input [31 : 0] delay;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v write_continue");
end // if
vfy_rdy;
fm.timing.write_continue(byten, data, delay);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // write_continue
task configure;
input [31:0] ctype;
input [64:1] generic_value;
begin
if (!((msg_level < `debug_3))) begin
$display("NOTE at %0t from %m", $time);
$write(" \"pcimaster.v configure");
$display("\"");
end // if
vfy_rdy;
fm.timing.configure(ctype, generic_value);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin @(fm.fm_rsp.strobe); end
check_int;
end
endtask // configure
task idle;
input [31 : 0] cycles;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v idle");
end // if
vfy_rdy;
fm.timing.idle(cycles);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // idle
task trigger;
input [31 : 0] tvalue;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v trigger");
end // if
vfy_rdy;
fm.timing.trigger(tvalue);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // trigger
task wait_on;
input [31 : 0] tvalue;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v wait_on");
end // if
vfy_rdy;
fm.timing.wait_on(tvalue);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // wait_on
task print_msg;
input [1 : `token_size*8] message;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v print_msg");
end // if
vfy_rdy;
fm.timing.print_msg(message);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // print_msg
task set_msg_level;
input [31:0] mlevel;
begin
if (!((msg_level < `debug_3))) begin
$display("NOTE at %0t from %m", $time);
$write(" \"pcimaster.v set_msg_level");
$display("\"");
end // if
vfy_rdy;
fm.timing.set_msg_level(mlevel);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin @(fm.fm_rsp.strobe); end
check_int;
end
endtask // set_msg_level
task call;
input [1 : `token_size*8] function_name;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v call");
end // if
vfy_rdy;
fm.timing.call(function_name);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // call
task func_beg;
input [1 : `token_size*8] function_name;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v func_beg");
end // if
vfy_rdy;
fm.timing.func_beg(function_name);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // func_beg
task func_end;
input [1 : `token_size*8] function_name;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v func_end");
end // if
vfy_rdy;
fm.timing.func_end(function_name);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // func_end
task sequential;
begin
if (!((msg_level < `debug_3))) begin
$display("NOTE at %0t from %m", $time);
$write(" \"pcimaster.v sequential");
$display("\"");
end // if
vfy_rdy;
fm.timing.sequential;
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin @(fm.fm_rsp.strobe); end
check_int;
end
endtask // sequential
task stop_sim;
begin
if (!((msg_level < `debug_3))) begin
$display("NOTE at %0t from %m", $time);
$write(" \"pcimaster.v stop_sim");
$display("\"");
end // if
vfy_rdy;
fm.timing.stop_sim;
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin @(fm.fm_rsp.strobe); end
check_int;
end
endtask // stop_sim
task wait_on_node;
input [1:`token_size*8] node_name;
input [1:`token_size] node_value;
input [1:`token_size] node_mask;
begin
if (!((msg_level < `debug_3))) begin
$display("NOTE at %0t from %m", $time);
$write(" \"pcimaster.v wait_on_node");
$display("\"");
end // if
vfy_rdy;
fm.timing.wait_on_node(node_name,node_value,node_mask);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin @(fm.fm_rsp.strobe); end
check_int;
end
endtask // wait_on_node
task open_buffer;
input [1 : `token_size*8] function_name;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v open_buffer");
end // if
vfy_rdy;
fm.timing.open_buffer(function_name);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // open_buffer
task close_buffer;
input [1 : `token_size*8] function_name;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v close_buffer");
end // if
vfy_rdy;
fm.timing.close_buffer(function_name);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // close_buffer
task set;
input [31:0] stype;
input [31:0] object_name;
input [`slv_size-1:0] object_value;
input [31:0] delay_val;
begin
if (!((msg_level < `debug_3))) begin
$display("NOTE at %0t from %m", $time);
$write(" \"pcimaster.v set");
$display("\"");
end // if
vfy_rdy;
fm.timing.set(stype, object_name, object_value, delay_val);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin @(fm.fm_rsp.strobe); end
check_int;
end
endtask // set
task get;
input [31 : 0] stype; // enum type set_types
input [31 : 0] object_name; // enum type object_name_types
input [`slv_size-1 : 0] expected_data;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v get");
end // if
vfy_rdy;
fm.timing.get(stype, object_name, expected_data);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // get
task remote;
input [31 : 0] target_id; // enum type natural
input [1 : `token_size*8] msg;
input buffer_f;
input notify_f;
input return_data_f;
begin
if (msg_level >= `debug_3) begin
$display("NOTE at %0t from %m", $time);
$display(" pcimaster.v remote");
end // if
vfy_rdy;
fm.timing.remote(target_id, msg, buffer_f, notify_f, return_data_f);
fm.fm_cmd <= #(0) fm.timing.wk_cmd;
@(fm.fm_rsp.strobe); while (!(fm.fm_rsp.ready)) begin
@(fm.fm_rsp.strobe); end
check_int;
end
endtask // remote
task check_int;
begin
if (msg_level >= `debug_3) begin
$display("check_int : enter");
end //if
end
endtask // check_int
//----------------------------------
//----------------------------------
//-- This block terminates the --
//-- code which will be replaced --
//-- by VGEN on future reruns --
//-- Enter USER code only after --
//-- this comment block --
//----------------------------------
//--**--**--**--**--**--**--**--**--
//**--**--**--**--**--**--**--**-- USER DECLARATION BEGIN
integer local_debug_level ; initial local_debug_level = 3;
reg dual_ad_cycle ; initial dual_ad_cycle = `false;
parameter no_compare = "%b----------------------------------------------------------------";
reg [1 : 20*8] message ;
reg [1 : 64*8] msg ;
reg [1 : 4*8] request_value ;
//**--**--**--**--**--**--**--**-- USER DECLARATION END
task reset_seq;
begin
if (!((local_debug_level<2))) begin
$display("NOTE at %0t from %m",$time);
$write(" \"pcimaster.v reset_seq ");
$display("\"");
end
@(posedge ( (prstnn === 1'b1) || (prstnn === 1'b1 /* 'H' */)));
end
endtask // ;
//----------------------------------------------------------------------------------
// END COMMAND TRANSLATION --
//----------------------------------------------------------------------------------
always begin : model
if ( init ) begin
init = `false;
end else begin
//-------------------------------
//-------------------------------
// User model code goes here ----
// replacing the following wait -
//-------------------------------
//-------------------------------
//-----------------------------------------------------------------------------
// Bus control commands are inserted between the following comment lines.
// Any commands include in this section are provide as part of the LMG
// delivered test bench and as examples. These commands may be modified
// or deleted. Note, a single call("<subroutine>") command is all that is
// required to executed commands from an external command file referenced by
// the parameter/generic cmd_file.
// Once the called <subroutine> completes command execution switches back to
// the embedded mode. Thus, command sequences may include commands from an
// external command file and embedded commands. Multiple "call" commands may
// be executed.
//
//-----------------------------------------------------------------------------
// ==== EMBEDDED COMMANDS BEGIN ==== --
call("main");
// ==== EMBEDDED COMMANDS END ==== --
// The "wait" statement below should not be removed
wait (`false); // wait forever
end // if
end //;
endmodule // behav;
| This page: |
Created: | Thu Aug 19 12:00:43 1999 |
| From: |
../../../sparc_v8/system/lmc/rtl/pcimaster.v
|