/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
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/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// following is defined for lmc stuff
`define true 1'b1
`define false 1'b0
`timescale 1 ns / 100 ps
`define time_scale_multiplier 1
`define lmv_timescale `timescale 1 ns / 100 ps
`define lmv_minimum 0
`define lmv_typical 1
`define lmv_maximum 2
`define lmv_gen 3
// This module specifies the board-level interconnect.
module Msystem
;
// Board-level nets
reg jtag_ck;
initial jtag_ck = 1 ;
reg jtag_ms;
initial jtag_ms = 1 ;
reg jtag_tdi;
initial jtag_tdi = 1 ;
reg jtag_trst_l;
initial jtag_trst_l = 0 ; // Tied active for normal operation
// Low-power-mode request pin
reg standby;
initial standby = 0 ;
reg ext_event_l ;
initial ext_event_l = 1 ;
reg vss;
reg vdd;
// wire sb_lerr_l;
wire sb_reset_l ; // SBus reset
// jp changed to 3 bits, ms bit is always 0 for now
reg [1:0] div_ctl ;
initial begin
$GetEnv("div_ctl",div_ctl);
end
// Bus definitions
wire [11:00] mem_addr; // memory address lines
wire [23:0] rom_addr;
wire rom_oe_l;
wire rom_we_l;
wire rom_cs_l;
wire [07:00] ras_l; // 4 RAS lines for DRAM
wire [03:00] cas_l; // CAS outputs (word select)
// wire [04:00] slvsel_l; // SBus slave selects (1/slave)
// wire [27:00] sbaddr; // SBus physical address output
// wire [05:00] sb_bg_l; // SBus bus grants (1/slave)
wire [01:00] p_rev; // p_rev not connected for swift -afx
// wire [1:0] cp_stat_l;
wire [63:00] b_memdata ; // memory data bus (Bi_directional).
wire [01:00] b_mempar ; // memory word parity bits
// wire [31:00] sbdata; // Sbus data
// wire [02:00] sb_size; // SBus transfer size
// wire [02:00] sb_ack_l; // SBus transfer acknowledgement
// wire [05:00] sb_br_l; // SBus bus requests (1/slave)
// Interrupt request lines - set by code in Mtask
// NO it's not - JP
// wire [03:00] irl = 4'h0;
// wire [3:0] irlpci;
wire [7:0] irlpci;
pullup //jkocol (weak1)
(irlpci[7]), (irlpci[6]), (irlpci[5]), (irlpci[4]),
(irlpci[3]), (irlpci[2]), (irlpci[1]), (irlpci[0]);
// Wires for pci
wire pciClk0, pciClk1, pciClk2, pciClk3;
wire RSTnn;
wire req0_,req1_,req2_,req3_;
wire req1_new_;
wire gnt0_,gnt1_,gnt2_,gnt3_;
wire [31:0] ad;
wire [3:0 ] cbe_;
wire devsel_, frame_, irdy_, par, perr_,
serr_, stop_, trdy_;
wire lock_ ;
reg input_reset_l ;
wire reset = ~input_reset_l ;
wire reset_l = ~reset ;
wire ss_scan_mode = `rl_jtag_cntl.sys_sen ;
// Tsunami reference clock output
wire ref_clk ;
wire SYS_CLK = ref_clk ;
// Clock, disabled during scan
wire clock = ref_clk | ss_scan_mode | Mclocks.scan_operation ;
// When pll_byp_l is not asserted, the internal PLL will
// frequency-multiply this by 4 to make input_clock.
reg pll_clk ;
initial begin
pll_clk = 0 ;
#1 forever @(posedge Mclocks.clock) begin
pll_clk = ~pll_clk ;
end
end
// When pll_byp_l is asserted, this will be input_clock.
// Note: this was moved earlier by #2, to compensate for the #2 added to
// the clock distribution paths for the Bug 597 fix.
parameter NEGEDGE = ((`CYCLETIME/4) - 3),
POSEDGE = ((`CYCLETIME/2) - 3) ;
reg byp_clk ;
initial begin
byp_clk = 0 ;
#1 forever @Mclocks.clock fork
#NEGEDGE byp_clk = 0 ;
#POSEDGE byp_clk = 1 ;
join
end
// By default, use the PLL. You may switch this anytime before the
// first posedge Mclocks.clock ($time==3) without affecting the
// simulation.
reg pll_byp_l ;
reg ext_clk2 ;
// add this so that req1 is idsel in slave mode - JP
assign req1_new_ = (ext_clk2 & pll_byp_l) ? ad[15] : req1_;
initial begin
$GetEnv("pll_byp_l", pll_byp_l);
$GetEnv("ext_clk2", ext_clk2);
end
// This is used, by misc_tasks, to do a clk_rst
reg dsbl_ext_clk ; initial dsbl_ext_clk = 0 ;
// Select the proper clock, based on the pll_byp_l input. Both choices
// should give identical waveforms.
wire ext_clk = (~pll_byp_l ? byp_clk : pll_clk) ;
wire ext_clk1 = ext_clk | dsbl_ext_clk ;
// Sbus output signals for debugging purposes
// wire sb_cg_l ;
// wire sb_cr_l ;
reg [2:0] speed_select ;
reg [1:0] boot_select ;
reg simm32_sel;
initial begin
// just add this until boot select is supported in the run script - John Petry
// now supported - Sandeep 7/31/96
//boot_select = 2'h0;
$GetEnv("boot",boot_select);
$GetEnv("speed",speed_select);
$GetEnv("simm32_sel",simm32_sel);
end
// >>>> lmc master
reg lmc_mst ;
wire vc_gnt3_, vc_req3_, lmc_gnt_, lmc_req_;
initial begin
lmc_mst = 0 ;
$GetEnv("lmc_mst", lmc_mst);
end
assign vc_gnt3_ = (gnt3_ | lmc_mst) ;
assign lmc_gnt_ = (gnt3_ | ~lmc_mst) ;
assign req3_ = ( (lmc_req_ === 1'bz ) ? 1'b1 : (vc_req3_ & ~lmc_mst) | (lmc_req_ & lmc_mst) ) ;
// end of >>>> lmc master
// start bbb : added these for external arbiter
reg ext_arbit ;
initial begin
$GetEnv("ext_arbit", ext_arbit);
end
wire arbi_clk ;
wire [7:0] gntnn;
wire gnt7_ , gnt6_ , gnt5_, gnt4_ ;
reg er_req0_, rgnt0_ ;
wire e_req0_ , e_gnt0_ , e_gnt1_ , e_gnt2_ , e_gnt3_ ;
wire r_gnt0_ , r_gnt1_ , r_gnt2_ , r_gnt3_ , r_gnt4_ ;
assign arbi_clk = pciClk3 & ext_arbit ;
assign gnt0_ = rgnt0_ ;
assign e_req0_ = er_req0_ ;
assign gnt3_ = (e_gnt3_ & ~ext_arbit) | (r_gnt3_ & ext_arbit);
assign gnt2_ = (e_gnt2_ & ~ext_arbit) | (r_gnt2_ & ext_arbit);
assign gnt1_ = (e_gnt1_ & ~ext_arbit) | (r_gnt1_ & ext_arbit);
arbiter_vc arbiter_VC(
.grant_out ({gnt7_, gnt6_, gnt5_, r_gnt4_, r_gnt3_, r_gnt2_, r_gnt1_, r_gnt0_ }),
.req_ ({1'b1, 1'b1, 1'b1, e_gnt0_, req3_, req2_, req1_, req0_ }),
.frame_ (frame_ ), // PCI Bus frame, indicates
.irdy_ (irdy_ ), // PCI Bus master ready
.reset (ext_arbit) ,
.clock (arbi_clk)
);
always @(e_gnt0_ or req0_ or r_gnt0_ or r_gnt4_ or ext_arbit)
begin
if (ext_arbit == 0)
rgnt0_ = e_gnt0_ ; // gnt0_ from eagle
else rgnt0_ = r_gnt0_ ; // gnt0_ from ext pci arbitor
if (ext_arbit == 0)
er_req0_ = req0_ ; // eagle as pci arbitor
else er_req0_ = r_gnt4_ ; // eagle use ext pci arbitor
end
// end bbb
ssparc_chip ssparc (
// .standby (standby),
.mc_memaddr (mem_addr), // memory address lines
.mc_ras_l (ras_l), // 4 RAS lines for DRAM
.mc_cas_l (cas_l), // CAS outputs (word select)
.mc_moe_l (moe_l), // memory output enable
.mc_mwe_l (mwe_l), // memory write enable
.simm32_sel (simm32_sel), // double density simm select YS
.pci_clk0 (pciClk0), // PCI reference clock
.pci_clk1 (pciClk1), // PCI reference clock
.pci_clk2 (pciClk2), // PCI reference clock
.pci_clk3 (pciClk3), // PCI reference clock
.frame_l (frame_), // PCI FRAME#
.trdy_l (trdy_), // PCI TRDY#
.irdy_l (irdy_), // PCI IRDY#
.stop_l (stop_), // PCI STOP#
.devsel_l (devsel_), // PCI DEVSEL#
.pci_req_l ({req3_,req2_,req1_new_, e_req0_}), // PCI bus requests
.pci_gnt_l ({e_gnt3_,e_gnt2_,e_gnt1_, e_gnt0_}), // PCI bus grants
.ad (ad), // PCI AD bus
.cbe_l (cbe_), // PCI CBE# bus
.par (par), // PCI PAR bus
// pci_int_l should not be used - Sandeep 10/10/96
//.pci_int_l (irlpci), // PCI interrupt request lines
.inta_ (irlpci[0]), // PCI interrupt request lines
.intb_ (irlpci[1]),
.intc_ (irlpci[2]),
.intd_ (irlpci[3]),
// add the following 4 interrupt pins in 2.0,
// replacing cp_stat_l[1:0], standby and spare pin
.inte_ (irlpci[4]),
.intf_ (irlpci[5]),
.intg_ (irlpci[6]),
.inth_ (irlpci[7]),
.perr_l (perr_), // PCI PERR#
.serr_l (serr_), // PCI SERR#
// .slvsel_l (slvsel_l), // SBus slave selects (1/slave)
// .sbclk0 (sbclk),
// .sbaddr (sbaddr), // SBus physical address output
// .sb_as_l (sb_as_l), // SBus address strobe
// .sb_bg_l (sb_bg_l), // SBus bus grants (1/slave)
// .cp_stat_l (cp_stat_l), // level_15 interrupt/watchdog reset status
.pci_rst_l (RSTnn), // reset synch to pci clock
.jtag_tdo (jtag_tdo), // JTAG test data out
.b_memdata(b_memdata), // memory data bus (bi-dir)
.b_mempar(b_mempar), // memory parity bus (bi-dir)
// .sbdata (sbdata), // Sbus data
// .sb_size (sb_size), // SBus transfer size
// .sb_read (sb_read), // SBus transfer direction
// .sb_ack_l (sb_ack_l), // SBus transfer acknowledgement
// .sb_lerr_l (sb_lerr_l), // SBus late error
.div_ctl (div_ctl), // SBus clock control
// .sb_br_l (sb_br_l), // SBus bus requests (1/slave)
.sp_sel (speed_select), // 70/85/100/125Mhz select (Lo/Hi)
.bm_sel (boot_select), // afx / pci boot select
// .irl (irl), // interrupt request lines
.jtag_ck (jtag_ck), // JTAG clock
.jtag_ms (jtag_ms), // JTAG mode select
.jtag_tdi (jtag_tdi), // JTAG test data in
.jtag_trst_l (jtag_trst_l), // JTAG reset
.ext_clk1 (ext_clk1),
.ext_clk2 (ext_clk2),
.pll_byp_l (pll_byp_l),
.input_reset_l (reset_l),
.int_event_l (int_event_l),
.ext_event_l (ext_event_l),
.ref_clk (ref_clk),
// .sb_cg_l (sb_cg_l),
// .sb_cr_l (sb_cr_l),
.rom_addr (rom_addr[23:0]),
.rom_oe_l (rom_oe_l),
.rom_we_l (rom_we_l),
.rom_cs_l (rom_cs_l),
.iiddtn (1'b0),
.csl_scan_mode (1'b0),
.pll_vdd (1'b1),
.pll_vss (1'b0),
.pll_rst (1'b0),
.procmon (procmon),
// Added tn and thermal diode pins - Sandeep
.tn (1'b1),
.therm_d (1'b0)
) ;
/***********************************************************************************/
/** Add the flash_prom32 model **/
// add boot_select port to the flash prom - Sandeep 7/29/96
// also changed the addr bits from 22 to 24 since the 2 lsb's are used to decode
// addresses in 8-bit prom access
// added for Flash Prom Programming Model - Sandeep
reg flash_pm ;
initial
begin
$GetEnv("flash_pm",flash_pm);
end
flash_prom32 flashProm(
//.addr (rom_addr[23:2]),
.addr (rom_addr[23:0]),
.data (b_memdata[31:0]),
.oe_l (rom_oe_l),
.we_l (rom_we_l),
.ce_l (1'b1),
.cs_l (rom_cs_l),
.b_sel (boot_select),
.flash_pm (flash_pm)
);
/***********************************************************************************/
/** Add wire statements to support RAM model. **/
/** The RAM64 module lives in "dram.v",which should be included at the top level. **/
wire [63:0] mem_size;
RAM64 TheRam(
.mem_size (mem_size), // 64-bit memory size
.b_memdata (b_memdata), // 64-bit bi-dir data bus
.b_mempar (b_mempar), // 2-bit bi-dir parity bus
.memaddr (mem_addr[10:0]), // 11-bit memory address
.ras_l (ras_l[7:0]), // 4 RAS lines for the DRAM, changed to 8
.cas_l (cas_l), // 2 CAS lines for the DRAM
.moe_l (moe_l), // single output enable for DRAM
.mwe_l (mwe_l), // single write enable for DRAM
.ram_output (ram_output), // ram output for tristate check
.simm32_sel (simm32_sel) // YS for double density simm or single density simm
);
/*
********************************************************************
This is hooking up of the AFX stuff
*******************************************************************
*/
/* NEW AFX 2.0 hook up */
afx_slave Mafx(
.clk (ssparc.ssparc_core.w_gclk), // graphics clock
.aen (ssparc.ssparc_core.w_aen), // address enable
.write_l (mwe_l), // read/write select
.lo_addr (ssparc.ssparc_core.w_s_reply), // low address select
.ab ({ssparc.ssparc_core.w_ab_out,mem_addr}), // address bus
.db (b_memdata), // 64 bit bi-directional data bus
.s_reply ({ssparc.ssparc_core.w_s_reply, mwe_l}), // system_reply
// make sure p_reply is not hooked up or we'll get false ones - JP
.p_reply ( ), // port_reply
.reset_l (reset_l) // reset for slave
);
/*
##### COMMENT THIS OUT FOR EAGLE ######
pullups ssparc_pullups(
.input_reset_l (reset_l),
.sb_br_l (sb_br_l),
.sb_ack_l (sb_ack_l),
.sb_lerr_l (sb_lerr_l)
) ;
*/
pullup //rdv (weak1)
(frame_), (trdy_), (irdy_), (stop_),
// add weak pull up on RSTnn so that slave mode resets can work.
// otherwise input is Z JP
// (lock_), (devsel_), (perr_), (serr_);
(lock_), (devsel_), (perr_), (serr_), (RSTnn);
/*
pulldown
(ad[0]), (ad[1]), (ad[2]), (ad[3]), (ad[4]), (ad[5]),
(ad[6]), (ad[7]), (ad[8]), (ad[9]), (ad[10]), (ad[11]),
(ad[12]), (ad[13]), (ad[14]), (ad[15]), (ad[16]), (ad[17]),
(ad[18]), (ad[19]), (ad[20]), (ad[21]), (ad[22]), (ad[23]),
(ad[24]), (ad[25]), (ad[26]), (ad[27]), (ad[28]), (ad[29]),
(ad[30]), (ad[31]),
(cbe_[3]), (cbe_[2]), (cbe_[1]), (cbe_[0]),
*/
/* pulldown (par); */
Pci_target pciS (
.ad ( ad[31:0]), .cbe_ ( cbe_[3:0]), .par ( par ),
.frame_ ( frame_ ), .irdy_ ( irdy_ ), .trdy_ ( trdy_ ),
.stop_ ( stop_ ), .lock_ ( lock_ ), .perr_ ( perr_ ),
.serr_ ( serr_ ), .devsel_ ( devsel_ ), .idsel ( ad[19] ),
.clock ( pciClk1 ), .rst_ ( RSTnn ));
wire [3:0] pciM_idsel = 4'h0;
PciMaster pciM(
.gnt_ ( gnt0_ ), .req_ ( req0_ ), .ad ( ad[31:0]),
.cbe_ ( cbe_[3:0]), .par ( par ), .frame_ ( frame_ ),
.irdy_ ( irdy_ ), .trdy_ ( trdy_ ), .stop_ ( stop_ ),
.lock_ ( lock_ ), .perr_ ( perr_ ), .serr_ ( serr_ ),
.devsel_ ( devsel_ ), .idsel ( pciM_idsel ), .clock ( pciClk2 ),
.rst_ ( RSTnn ), //, .own_bus (bus_owner),
.int_ (irlpci[7:0]));
//.back2back (back2back) );
wire trdyi_ ; // in memcmd.s c_pa_rst.100.4 : @e00001fc master cannot see trdy_ !
wire stopi_ ;
assign #6 trdyi_ = trdy_ ;
assign #6 stopi_ = stop_ ;
MASTER pciM1(
.gnt_ ( gnt1_ ), .req_ ( req1_ ), .ad ( ad[31:0]),
.cbe_ ( cbe_[3:0]), .par ( par ), .frame_ ( frame_ ),
.irdy_ ( irdy_ ), .trdy_ ( trdyi_ ), .stop_ ( stopi_ ),
.lock_ ( lock_ ), .perr_ ( perr_ ), .serr_ ( serr_ ),
.devsel_ ( devsel_ ), .idsel ( pciM_idsel ), .clock ( pciClk3 ),
.rst_ ( RSTnn )); //, .own_bus (bus_owner),
//.back2back (back2back) );
MASTER pciM2(
.gnt_ ( gnt2_ ), .req_ ( req2_ ), .ad ( ad[31:0]),
.cbe_ ( cbe_[3:0]), .par ( par ), .frame_ ( frame_ ),
.irdy_ ( irdy_ ), .trdy_ ( trdy_ ), .stop_ ( stop_ ),
.lock_ ( lock_ ), .perr_ ( perr_ ), .serr_ ( serr_ ),
.devsel_ ( devsel_ ), .idsel ( pciM_idsel ), .clock ( pciClk3 ),
.rst_ ( RSTnn )); //, .own_bus (bus_owner),
//.back2back (back2back) );
MASTER pciM3(
.gnt_ ( vc_gnt3_ ), .req_ ( vc_req3_ ), .ad ( ad[31:0]),
.cbe_ ( cbe_[3:0]), .par ( par ), .frame_ ( frame_ ),
.irdy_ ( irdy_ ), .trdy_ ( trdy_ ), .stop_ ( stop_ ),
.lock_ ( lock_ ), .perr_ ( perr_ ), .serr_ ( serr_ ),
.devsel_ ( devsel_ ), .idsel ( pciM_idsel ), .clock ( pciClk3 ),
.rst_ ( RSTnn )); //, .own_bus (bus_owner),
//.back2back (back2back) );
// ->>> added ravicad pci protocol checker
checker check(
.ad ( ad[31:0]), .cbe_ ( cbe_[3:0] ), .par ( par ),
.frame_ ( frame_ ), .irdy_ ( irdy_ ), .trdy_ ( trdy_ ),
.stop_ ( stop_ ), .lock_ ( lock_ ), .perr_ (perr_ ),
.serr_ ( serr_ ), .req64_( lock_ ), .ack64_ (lock_ ),
.devsel_( devsel_ ), .clock ( pciClk3 ), .rst_ (RSTnn )
);
// ->>> following is defined for lmc stuff
wire [7:0] reqnn;
// reg reqnn_7, reqnn_6, reqnn_5, reqnn_4, reqnn_3, reqnn_2, reqnn_1, reqnn_0;
assign
reqnn[7] = 1'b1,
reqnn[6] = 1'b1,
reqnn[5] = 1'b1,
reqnn[4] = (`SSPARC_CORE.ssparc_pcic.arbiter.req_host_ & ~ext_arbit) | (e_gnt0_ & ext_arbit),
reqnn[3] = req3_,
reqnn[2] = req2_,
reqnn[1] = req1_,
reqnn[0] = req0_;
// reg gntnn_7, gntnn_6, gntnn_5, gntnn_4, gntnn_3, gntnn_2, gntnn_1, gntnn_0;
assign
gntnn[7] = 1'b1,
gntnn[6] = 1'b1,
gntnn[5] = 1'b1,
gntnn[4] = (`SSPARC_CORE.ssparc_pcic.arbiter.granto_host_ & ~ext_arbit) | (r_gnt4_ & ext_arbit),
gntnn[3] = gnt3_,
gntnn[2] = gnt2_,
gntnn[1] = gnt1_,
gntnn[0] = gnt0_;
reg disable_msg ;
initial disable_msg = 1'b0;
/*
no locking supported on eagle.
*/
wire plocknn;
assign plocknn = 1'b1;
wire [63:0] ad_m;
assign ad_m = {32'b0, ad} ;
wire [7:0 ] cbe_m;
assign cbe_m = {4'b0, cbe_} ;
pcimonitor u1 (
.clk ( pciClk0 ),
.rstnn ( RSTnn ),
.ad ( ad_m ),
.cxbenn ( cbe_m ),
.par ( par ),
.framenn ( frame_ ),
.trdynn ( trdy_ ),
.irdynn ( irdy_ ),
.stopnn ( stop_ ),
.devselnn ( devsel_ ),
.idsel ( ad[19:12] ),
.perrnn ( perr_ ),
.serrnn ( serr_ ),
.reqnn ( reqnn ),
.gntnn ( gntnn ),
.locknn ( ),
.par64 ( ),
.req64nn ( ),
.ack64nn ( ),
.sbonn ( ),
.sdone ( ),
.intann (irlpci[0]),
.intbnn (irlpci[1]),
.intcnn (irlpci[2]),
.intdnn (irlpci[3]),
.disablemsg (disable_msg) );
defparam u1.fm.version = "pci33";
defparam u1.fm.data_file = "pcimonitor.lst";
defparam u1.fm.arbitrate = `false;
defparam u1.fm.priority = 0;
defparam u1.fm.park_zero = `false;
defparam u1.fm.trace_file = `true;
defparam u1.fm.error_check = `true;
defparam u1.fm.gen_debug_level = 0;
defparam u1.fm.gen_global = `true,
u1.fm.gen_option = `lmv_maximum,
u1.fm.gen_time_check = `true,
u1.fm.gen_vlt = 5000,
u1.fm.gen_tmp = 300,
u1.fm.gen_DF = 100;
pcislave lmc_slave1(
.pclk ( pciClk0 ),
.prstnn ( RSTnn ),
.pad ( ad ),
.pcxbenn ( cbe_ ),
.ppar ( par ),
.pframenn ( frame_ ),
.ptrdynn ( trdy_ ),
.pirdynn ( irdy_ ),
.pstopnn ( stop_ ),
.pdevselnn ( devsel_ ),
.pidsel ( ad[12] ),
.pperrnn ( perr_ ),
.pserrnn ( serr_ ),
.plocknn ( 1'b1 ),
.ppar64 ( ), // 1'b1 ),
.preq64nn ( 1'b1 ),
.pack64nn ( ), // 1'b1 ),
.psbonn ( 1'b1 ),
.psdone ( 1'b1 ),
.pd ( ),
.pbenn ( ) );
// parameter values for pcislave.v
defparam lmc_slave1.gen_debug_level = 0; // debug level: 0 = no debugging
// parameter values for pcislave_fm.v
defparam lmc_slave1.fm.version = "pci33",
lmc_slave1.fm.cmd_file = "pcislave_tst.cmd",
lmc_slave1.fm.cfg_file = "pcislave_tst.cfg",
lmc_slave1.fm.mem_file = "pcislave_tst.dat",
lmc_slave1.fm.io_file = "pcislave_tst.io",
lmc_slave1.fm.x_transition = `false,
lmc_slave1.fm.device_id = 16'h1234,
lmc_slave1.fm.vendor_id = 16'h5678,
lmc_slave1.fm.revision_id = 8'h00,
lmc_slave1.fm.header_type = 8'h00,
lmc_slave1.fm.class_code = 24'h000000,
lmc_slave1.fm.mem_lower_0_init = 64'h0000000000100000,
lmc_slave1.fm.mem_upper_0_init = 64'h00000000001fffff,
lmc_slave1.fm.mem_lower_1_init = 64'h0000000021000000,
lmc_slave1.fm.mem_upper_1_init = 64'h0000000021002000, // 8 4k pages
lmc_slave1.fm.mem_lower_2_init = 64'h0000000030000000,
lmc_slave1.fm.mem_upper_2_init = 64'h00000000afffffff, // 8x256 MB = 2GB
lmc_slave1.fm.io_lower_0_init = 64'h0000000000000000,
lmc_slave1.fm.io_upper_0_init = 64'h0000000000002000, // 2 4k pages
lmc_slave1.fm.io_lower_1_init = 64'h0000000013004000,
lmc_slave1.fm.io_upper_1_init = 64'h0000000013008000, // 4 4k pages
lmc_slave1.fm.io_lower_2_init = 64'h0000000080008000,
lmc_slave1.fm.io_upper_2_init = 64'h0000000088ffffff, // 1 MB
lmc_slave1.fm.cache_line_size = 8'h20,
lmc_slave1.fm.addr64 = `false,
lmc_slave1.fm.data64 = `false,
lmc_slave1.fm.iack = `false,
lmc_slave1.fm.iack_vector = 32'h00000000,
// below are examples if gen_global is set to `false
lmc_slave1.fm.gen_global = `false, // use options from command line
lmc_slave1.fm.gen_option = `lmv_maximum, // select maximum delays
lmc_slave1.fm.gen_time_check = `true, // enable time checkings
lmc_slave1.fm.gen_x_check = `false, // enable x-checkings
lmc_slave1.fm.gen_annotated = `false, // not annotated
lmc_slave1.fm.gen_vlt = 5000, // voltage (mv)
lmc_slave1.fm.gen_tmp = 300, // temperature (k)
lmc_slave1.fm.gen_DF = 100; // deration (%)
wire pclkrunnn;
assign pclkrunnn = 1'b0;
wire [3:0] pbenn;
assign pbenn = 4'b1111; // enables for the upper 32 bits of a 64 bit
wire prim_req64;
assign (weak0, weak1) prim_req64 = 1'b1;
wire wire_one;
assign (weak0, weak1) wire_one = 1'b1;
wire [31:0] pd;
assign (weak0, weak1) pd = 32'hFFFF;
wire ppar64;
assign (weak0, weak1) ppar64 = 1'b0;
pcimaster lmc_master1
(
.pad (ad[31:0]),
.pcxbenn (cbe_[3:0]),
.ppar (par),
.pframenn (frame_),
.ptrdynn (trdy_),
.pirdynn (irdy_),
.pstopnn (stop_),
.pdevselnn (devsel_),
.pidsel (ad[14]),
.preqnn (lmc_req_),
.pgntnn (lmc_gnt_),
.pclk (pciClk0),
.pclkrunnn (pclkrunnn), // always enabled.
.prstnn (RSTnn),
.pd (pd[31:0]),
.pbenn (pbenn[3:0]), // (4'b1111),
.ppar64 (ppar64),
.preq64nn (prim_req64), // (wire_one),
.pack64nn (wire_one), // (1'b1),
.plocknn (plocknn),
.pperrnn (perr_),
.pserrnn (serr_),
.psbonn (1'b1),
.psdone (1'b1),
.syncin (8'hzz),
.syncout ( ) );
defparam
lmc_master1.fm.initial_max_cmd_mem_size = 1000,
lmc_master1.fm.max_ctrl_queue_size = 1000,
lmc_master1.gen_debug_level = 0,
lmc_master1.fm.cmd_file = "lmc_master1.cmd",
lmc_master1.fm.version = "pci33",
lmc_master1.fm.gen_global = `true, // use options from command file.
lmc_master1.fm.gen_option = `lmv_maximum,
lmc_master1.fm.max_clk_period = "0 ns", // ??
lmc_master1.fm.gen_time_check = `false, // ??
lmc_master1.fm.gen_x_check = `false, // ??
lmc_master1.fm.gen_annotated = `false,
lmc_master1.fm.gen_vlt = 5000,
lmc_master1.fm.gen_tmp = 300,
lmc_master1.fm.gen_DF = 100, // ??
lmc_master1.fm.x_transition = `false, // ??
lmc_master1.fm.device_id = 16'h0002,
lmc_master1.fm.vendor_id = 16'h1213,
lmc_master1.fm.revision_id = 8'h01,
lmc_master1.fm.class_code = 24'h000001,
lmc_master1.fm.cacheline_size = 8'h40,
lmc_master1.fm.to_limit = 128,
lmc_master1.fm.retry_limit = 9,
lmc_master1.fm.gen_debug_level = 0; // ??
endmodule
| This page: |
Created: | Thu Aug 19 11:56:45 1999 |
| From: |
../../../sparc_v8/system/rtl/eagle.v
|